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MIPS: Add base architecture support for RI and XI.

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Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
Architecture now defines an optional feature to implement these
TLB bits separately. Support for one or both features can be
checked by looking at the Config3.RXI bit.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Acked-by: David Daney <david.daney@cavium.com>
This commit is contained in:
Steven J. Hill
2012-09-13 16:47:58 -05:00
parent fea7a08acb
commit b2ab4f08e8
4 changed files with 10 additions and 1 deletions
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6
arch/mips/kernel/cpu-probe.c
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@@ -421,8 +421,12 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
config3 = read_c0_config3();
if (config3 & MIPS_CONF3_SM)
if (config3 & MIPS_CONF3_SM) {
c->ases |= MIPS_ASE_SMARTMIPS;
c->options |= MIPS_CPU_RIXI;
}
if (config3 & MIPS_CONF3_RXI)
c->options |= MIPS_CPU_RIXI;
if (config3 & MIPS_CONF3_DSP)
c->ases |= MIPS_ASE_DSP;
if (config3 & MIPS_CONF3_VINT)