Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann: "A large number of cleanups, all over the platforms. This is dominated largely by the Samsung platforms (s3c, s5p, exynos) and a few of the others moving code out of arch/arm into more appropriate subsystems. The clocksource and irqchip drivers are now abstracted to the point where platforms that are already cleaned up do not need to even specify the driver they use, it can all get configured from the device tree as we do for normal device drivers. The clocksource changes basically touch every single platform in the process. We further clean up the use of platform specific header files here, with the goal of turning more of the platforms over to being "multiplatform" enabled, which implies that they cannot expose their headers to architecture independent code any more. It is expected that no functional changes are part of the cleanup. The overall reduction in total code lines is mostly the result of removing broken and obsolete code." * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (133 commits) ARM: mvebu: correct gated clock documentation ARM: kirkwood: add missing include for nsa310 ARM: exynos: move exynos4210-combiner to drivers/irqchip mfd: db8500-prcmu: update resource passing drivers/db8500-cpufreq: delete dangling include ARM: at91: remove NEOCORE 926 board sunxi: Cleanup the reset code and add meaningful registers defines ARM: S3C24XX: header mach/regs-mem.h local ARM: S3C24XX: header mach/regs-power.h local ARM: S3C24XX: header mach/regs-s3c2412-mem.h local ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/ ARM: S3C24XX: transform s3c2443 subirqs into new structure ARM: S3C24XX: modify s3c2443 irq init to initialize all irqs ARM: S3C24XX: move s3c2443 irq code to irq.c ARM: S3C24XX: transform s3c2416 irqs into new structure ARM: S3C24XX: modify s3c2416 irq init to initialize all irqs ARM: S3C24XX: move s3c2416 irq init to common irq code ARM: S3C24XX: Modify s3c_irq_wake to use the hwirq property ARM: S3C24XX: Move irq syscore-ops to irq-pm clocksource: always define CLOCKSOURCE_OF_DECLARE ...
This commit is contained in:
Linus Torvalds
@@ -12,6 +12,7 @@
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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@@ -22,12 +23,13 @@
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#include <linux/of_irq.h>
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#include <linux/export.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/proc-fns.h>
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#include <asm/exception.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/cacheflush.h>
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@@ -35,7 +37,6 @@
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#include <mach/regs-irq.h>
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#include <mach/regs-pmu.h>
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#include <mach/regs-gpio.h>
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#include <mach/pmu.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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@@ -440,220 +441,6 @@ static void __init exynos5_init_clocks(int xtal)
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#endif
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}
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#define COMBINER_ENABLE_SET 0x0
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#define COMBINER_ENABLE_CLEAR 0x4
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#define COMBINER_INT_STATUS 0xC
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static DEFINE_SPINLOCK(irq_controller_lock);
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struct combiner_chip_data {
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unsigned int irq_offset;
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unsigned int irq_mask;
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void __iomem *base;
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};
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static struct irq_domain *combiner_irq_domain;
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static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
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static inline void __iomem *combiner_base(struct irq_data *data)
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{
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struct combiner_chip_data *combiner_data =
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irq_data_get_irq_chip_data(data);
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return combiner_data->base;
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}
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static void combiner_mask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
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}
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static void combiner_unmask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
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}
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static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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unsigned int cascade_irq, combiner_irq;
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unsigned long status;
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chained_irq_enter(chip, desc);
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spin_lock(&irq_controller_lock);
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status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
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spin_unlock(&irq_controller_lock);
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status &= chip_data->irq_mask;
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if (status == 0)
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goto out;
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combiner_irq = __ffs(status);
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cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
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if (unlikely(cascade_irq >= NR_IRQS))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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chained_irq_exit(chip, desc);
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}
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static struct irq_chip combiner_chip = {
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.name = "COMBINER",
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.irq_mask = combiner_mask_irq,
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.irq_unmask = combiner_unmask_irq,
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};
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static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
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{
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unsigned int max_nr;
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if (soc_is_exynos5250())
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max_nr = EXYNOS5_MAX_COMBINER_NR;
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else
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max_nr = EXYNOS4_MAX_COMBINER_NR;
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if (combiner_nr >= max_nr)
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BUG();
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if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
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BUG();
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irq_set_chained_handler(irq, combiner_handle_cascade_irq);
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}
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static void __init combiner_init_one(unsigned int combiner_nr,
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void __iomem *base)
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{
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combiner_data[combiner_nr].base = base;
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combiner_data[combiner_nr].irq_offset = irq_find_mapping(
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combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
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combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
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/* Disable all interrupts */
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__raw_writel(combiner_data[combiner_nr].irq_mask,
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base + COMBINER_ENABLE_CLEAR);
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}
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#ifdef CONFIG_OF
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static int combiner_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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if (d->of_node != controller)
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return -EINVAL;
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if (intsize < 2)
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return -EINVAL;
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*out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
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*out_type = 0;
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return 0;
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}
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#else
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static int combiner_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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return -EINVAL;
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}
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#endif
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static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
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irq_set_chip_data(irq, &combiner_data[hw >> 3]);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops combiner_irq_domain_ops = {
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.xlate = combiner_irq_domain_xlate,
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.map = combiner_irq_domain_map,
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};
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static void __init combiner_init(void __iomem *combiner_base,
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struct device_node *np)
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{
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int i, irq, irq_base;
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unsigned int max_nr, nr_irq;
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if (np) {
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if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
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pr_warning("%s: number of combiners not specified, "
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"setting default as %d.\n",
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__func__, EXYNOS4_MAX_COMBINER_NR);
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max_nr = EXYNOS4_MAX_COMBINER_NR;
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}
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} else {
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max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
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EXYNOS4_MAX_COMBINER_NR;
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}
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nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
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irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
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if (IS_ERR_VALUE(irq_base)) {
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irq_base = COMBINER_IRQ(0, 0);
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pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
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}
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combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
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&combiner_irq_domain_ops, &combiner_data);
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if (WARN_ON(!combiner_irq_domain)) {
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pr_warning("%s: irq domain init failed\n", __func__);
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return;
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}
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for (i = 0; i < max_nr; i++) {
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combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
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irq = IRQ_SPI(i);
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#ifdef CONFIG_OF
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if (np)
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irq = irq_of_parse_and_map(np, i);
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#endif
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combiner_cascade_irq(i, irq);
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}
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}
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#ifdef CONFIG_OF
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static int __init combiner_of_init(struct device_node *np,
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struct device_node *parent)
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{
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void __iomem *combiner_base;
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combiner_base = of_iomap(np, 0);
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if (!combiner_base) {
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pr_err("%s: failed to map combiner registers\n", __func__);
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return -ENXIO;
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}
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combiner_init(combiner_base, np);
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return 0;
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}
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static const struct of_device_id exynos_dt_irq_match[] = {
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
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{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
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{ .compatible = "samsung,exynos4210-combiner",
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.data = combiner_of_init, },
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{},
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};
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#endif
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void __init exynos4_init_irq(void)
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{
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unsigned int gic_bank_offset;
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@@ -664,7 +451,7 @@ void __init exynos4_init_irq(void)
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gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
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#ifdef CONFIG_OF
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else
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of_irq_init(exynos_dt_irq_match);
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irqchip_init();
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#endif
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if (!of_have_populated_dt())
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@@ -681,7 +468,7 @@ void __init exynos4_init_irq(void)
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void __init exynos5_init_irq(void)
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{
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#ifdef CONFIG_OF
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of_irq_init(exynos_dt_irq_match);
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irqchip_init();
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#endif
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/*
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* The parameters of s5p_init_irq() are for VIC init.
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