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clk: tegra: Define PLLD_DSI and remove dsia(b)_mux

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PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.

So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
This commit is contained in:
Mark Zhang
2014-12-09 14:59:59 +08:00
committed by Peter De Schrijver
parent 08acae34e8
commit b270491eb9
5 changed files with 27 additions and 29 deletions
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6
include/dt-bindings/clock/tegra124-car-common.h
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@@ -297,7 +297,7 @@
#define TEGRA124_CLK_PLL_C4 270
#define TEGRA124_CLK_PLL_DP 271
#define TEGRA124_CLK_PLL_E_MUX 272
/* 273 */
#define TEGRA124_CLK_PLLD_DSI 273
/* 274 */
/* 275 */
/* 276 */
@@ -334,8 +334,8 @@
#define TEGRA124_CLK_CLK_OUT_1_MUX 306
#define TEGRA124_CLK_CLK_OUT_2_MUX 307
#define TEGRA124_CLK_CLK_OUT_3_MUX 308
#define TEGRA124_CLK_DSIA_MUX 309
#define TEGRA124_CLK_DSIB_MUX 310
/* 309 */
/* 310 */
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_XUSB_SS_DIV2 312