Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"The most noteworthy SoC driver changes this time include:
- The TEE subsystem gains an in-kernel interface to access the TEE
from device drivers.
- The reset controller subsystem gains a driver for the Qualcomm
Snapdragon 845 Power Domain Controller.
- The Xilinx Zynq platform now has a firmware interface for its
platform management unit. This contains a firmware "ioctl"
interface that was a little controversial at first, but the version
we merged solved that by not exposing arbitrary firmware calls to
user space.
- The Amlogic Meson platform gains a "canvas" driver that is used for
video processing and shared between different high-level drivers.
The rest is more of the usual, mostly related to SoC specific power
management support and core drivers in drivers/soc:
- Several Renesas SoCs (RZ/G1N, RZ/G2M, R-Car V3M, RZ/A2M) gain new
features related to power and reset control.
- The Mediatek mt8183 and mt6765 SoC platforms gain support for their
respective power management chips.
- A new driver for NXP i.MX8, which need a firmware interface for
power management.
- The SCPI firmware interface now contains support estimating power
usage of performance states
- The NVIDIA Tegra "pmc" driver gains a few new features, in
particular a pinctrl interface for configuring the pads.
- Lots of small changes for Qualcomm, in particular the "smem" device
driver.
- Some cleanups for the TI OMAP series related to their sysc
controller.
Additional cleanups and bugfixes in SoC specific drivers include the
Meson, Keystone, NXP, AT91, Sunxi, Actions, and Tegra platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (129 commits)
firmware: tegra: bpmp: Implement suspend/resume support
drivers: clk: Add ZynqMP clock driver
dt-bindings: clock: Add bindings for ZynqMP clock driver
firmware: xilinx: Add zynqmp IOCTL API for device control
Documentation: xilinx: Add documentation for eemi APIs
MAINTAINERS: imx: include drivers/firmware/imx path
firmware: imx: add misc svc support
firmware: imx: add SCU firmware driver support
reset: Fix potential use-after-free in __of_reset_control_get()
dt-bindings: arm: fsl: add scu binding doc
soc: fsl: qbman: add interrupt coalesce changing APIs
soc: fsl: bman_portals: defer probe after bman's probe
soc: fsl: qbman: Use last response to determine valid bit
soc: fsl: qbman: Add 64 bit DMA addressing requirement to QBMan
soc: fsl: qbman: replace CPU 0 with any online CPU in hotplug handlers
soc: fsl: qbman: Check if CPU is offline when initializing portals
reset: qcom: PDC Global (Power Domain Controller) reset controller
dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
reset: Grammar s/more then once/more than once/
bus: ti-sysc: Just use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS
...
This commit is contained in:
Linus Torvalds
@@ -98,6 +98,15 @@ config RESET_QCOM_AOSS
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reset signals provided by AOSS for Modem, Venus, ADSP,
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GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
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config RESET_QCOM_PDC
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tristate "Qualcomm PDC Reset Driver"
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depends on ARCH_QCOM || COMPILE_TEST
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help
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This enables the PDC (Power Domain Controller) reset driver
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for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
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to control reset signals provided by PDC for Modem, Compute,
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Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
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config RESET_SIMPLE
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bool "Simple Reset Controller Driver" if COMPILE_TEST
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default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
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@@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
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obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
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obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
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obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
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obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
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obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
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obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
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@@ -496,28 +496,29 @@ struct reset_control *__of_reset_control_get(struct device_node *node,
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break;
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}
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}
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of_node_put(args.np);
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if (!rcdev) {
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mutex_unlock(&reset_list_mutex);
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return ERR_PTR(-EPROBE_DEFER);
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rstc = ERR_PTR(-EPROBE_DEFER);
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goto out;
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}
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if (WARN_ON(args.args_count != rcdev->of_reset_n_cells)) {
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mutex_unlock(&reset_list_mutex);
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return ERR_PTR(-EINVAL);
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rstc = ERR_PTR(-EINVAL);
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goto out;
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}
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rstc_id = rcdev->of_xlate(rcdev, &args);
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if (rstc_id < 0) {
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mutex_unlock(&reset_list_mutex);
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return ERR_PTR(rstc_id);
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rstc = ERR_PTR(rstc_id);
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goto out;
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}
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/* reset_list_mutex also protects the rcdev's reset_control list */
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rstc = __reset_control_get_internal(rcdev, rstc_id, shared);
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out:
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mutex_unlock(&reset_list_mutex);
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of_node_put(args.np);
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return rstc;
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}
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124
drivers/reset/reset-qcom-pdc.c
Normal file
124
drivers/reset/reset-qcom-pdc.c
Normal file
@@ -0,0 +1,124 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 The Linux Foundation. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/reset/qcom,sdm845-pdc.h>
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#define RPMH_PDC_SYNC_RESET 0x100
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struct qcom_pdc_reset_map {
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u8 bit;
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};
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struct qcom_pdc_reset_data {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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};
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static const struct regmap_config sdm845_pdc_regmap_config = {
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.name = "pdc-reset",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x20000,
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.fast_io = true,
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};
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static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
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[PDC_APPS_SYNC_RESET] = {0},
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[PDC_SP_SYNC_RESET] = {1},
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[PDC_AUDIO_SYNC_RESET] = {2},
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[PDC_SENSORS_SYNC_RESET] = {3},
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[PDC_AOP_SYNC_RESET] = {4},
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[PDC_DEBUG_SYNC_RESET] = {5},
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[PDC_GPU_SYNC_RESET] = {6},
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[PDC_DISPLAY_SYNC_RESET] = {7},
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[PDC_COMPUTE_SYNC_RESET] = {8},
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[PDC_MODEM_SYNC_RESET] = {9},
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};
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static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
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struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
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}
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static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
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return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
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BIT(sdm845_pdc_resets[idx].bit),
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BIT(sdm845_pdc_resets[idx].bit));
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}
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static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
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return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
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BIT(sdm845_pdc_resets[idx].bit), 0);
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}
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static const struct reset_control_ops qcom_pdc_reset_ops = {
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.assert = qcom_pdc_control_assert,
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.deassert = qcom_pdc_control_deassert,
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};
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static int qcom_pdc_reset_probe(struct platform_device *pdev)
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{
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struct qcom_pdc_reset_data *data;
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struct device *dev = &pdev->dev;
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void __iomem *base;
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struct resource *res;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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data->regmap = devm_regmap_init_mmio(dev, base,
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&sdm845_pdc_regmap_config);
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if (IS_ERR(data->regmap)) {
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dev_err(dev, "Unable to initialize regmap\n");
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return PTR_ERR(data->regmap);
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}
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.ops = &qcom_pdc_reset_ops;
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data->rcdev.nr_resets = ARRAY_SIZE(sdm845_pdc_resets);
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data->rcdev.of_node = dev->of_node;
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return devm_reset_controller_register(dev, &data->rcdev);
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}
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static const struct of_device_id qcom_pdc_reset_of_match[] = {
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{ .compatible = "qcom,sdm845-pdc-global" },
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{}
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};
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MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
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static struct platform_driver qcom_pdc_reset_driver = {
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.probe = qcom_pdc_reset_probe,
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.driver = {
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.name = "qcom_pdc_reset",
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.of_match_table = qcom_pdc_reset_of_match,
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},
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};
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module_platform_driver(qcom_pdc_reset_driver);
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MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
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MODULE_LICENSE("GPL v2");
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