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net: dsa: felix: support half-duplex link modes

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Ping tested:

  [   11.808455] mscc_felix 0000:00:00.5 swp0: Link is Up - 1Gbps/Full - flow control rx/tx
  [   11.816497] IPv6: ADDRCONF(NETDEV_CHANGE): swp0: link becomes ready

  [root@LS1028ARDB ~] # ethtool -s swp0 advertise 0x4
  [   18.844591] mscc_felix 0000:00:00.5 swp0: Link is Down
  [   22.048337] mscc_felix 0000:00:00.5 swp0: Link is Up - 100Mbps/Half - flow control off

  [root@LS1028ARDB ~] # ip addr add 192.168.1.1/24 dev swp0

  [root@LS1028ARDB ~] # ping 192.168.1.2
  PING 192.168.1.2 (192.168.1.2): 56 data bytes
  (...)
  ^C--- 192.168.1.2 ping statistics ---
  3 packets transmitted, 3 packets received, 0% packet loss
  round-trip min/avg/max = 0.383/0.611/1.051 ms

  [root@LS1028ARDB ~] # ethtool -s swp0 advertise 0x10
  [  355.637747] mscc_felix 0000:00:00.5 swp0: Link is Down
  [  358.788034] mscc_felix 0000:00:00.5 swp0: Link is Up - 1Gbps/Half - flow control off

  [root@LS1028ARDB ~] # ping 192.168.1.2
  PING 192.168.1.2 (192.168.1.2): 56 data bytes
  (...)
  ^C
  --- 192.168.1.2 ping statistics ---
  16 packets transmitted, 16 packets received, 0% packet loss
  round-trip min/avg/max = 0.301/0.384/1.138 ms

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vladimir Oltean
2020-07-05 19:16:22 +03:00
committed by David S. Miller
parent 3f2628d62d
commit b1c7b87443
3 changed files with 17 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/dsa/ocelot/felix.c
View File

@@ -194,13 +194,15 @@ static void felix_phylink_validate(struct dsa_switch *ds, int port,
return; return;
} }
/* No half-duplex. */
phylink_set_port_modes(mask); phylink_set_port_modes(mask);
phylink_set(mask, Autoneg); phylink_set(mask, Autoneg);
phylink_set(mask, Pause); phylink_set(mask, Pause);
phylink_set(mask, Asym_Pause); phylink_set(mask, Asym_Pause);
phylink_set(mask, 10baseT_Half);
phylink_set(mask, 10baseT_Full); phylink_set(mask, 10baseT_Full);
phylink_set(mask, 100baseT_Half);
phylink_set(mask, 100baseT_Full); phylink_set(mask, 100baseT_Full);
phylink_set(mask, 1000baseT_Half);
phylink_set(mask, 1000baseT_Full); phylink_set(mask, 1000baseT_Full);
if (state->interface == PHY_INTERFACE_MODE_INTERNAL || if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||

23
drivers/net/dsa/ocelot/felix_vsc9959.c
View File

@@ -817,12 +817,9 @@ static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE); phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE);
} else { } else {
u16 if_mode = ENETC_PCS_IF_MODE_SGMII_EN;
int speed; int speed;
if (state->duplex == DUPLEX_HALF) {
phydev_err(pcs, "Half duplex not supported\n");
return;
}
switch (state->speed) { switch (state->speed) {
case SPEED_1000: case SPEED_1000:
speed = ENETC_PCS_SPEED_1000; speed = ENETC_PCS_SPEED_1000;
@@ -841,9 +838,9 @@ static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
return; return;
} }
phy_write(pcs, ENETC_PCS_IF_MODE, if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(speed);
ENETC_PCS_IF_MODE_SGMII_EN | if (state->duplex == DUPLEX_HALF)
ENETC_PCS_IF_MODE_SGMII_SPEED(speed)); if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE); phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
} }
@@ -870,15 +867,18 @@ static void vsc9959_pcs_init_2500basex(struct phy_device *pcs,
unsigned int link_an_mode, unsigned int link_an_mode,
const struct phylink_link_state *state) const struct phylink_link_state *state)
{ {
u16 if_mode = ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500) |
ENETC_PCS_IF_MODE_SGMII_EN;
if (link_an_mode == MLO_AN_INBAND) { if (link_an_mode == MLO_AN_INBAND) {
phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n"); phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n");
return; return;
} }
phy_write(pcs, ENETC_PCS_IF_MODE, if (state->duplex == DUPLEX_HALF)
ENETC_PCS_IF_MODE_SGMII_EN | if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500));
phy_write(pcs, ENETC_PCS_IF_MODE, if_mode);
phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE); phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
} }
@@ -919,8 +919,11 @@ static void vsc9959_pcs_init(struct ocelot *ocelot, int port,
linkmode_set_bit_array(phy_basic_ports_array, linkmode_set_bit_array(phy_basic_ports_array,
ARRAY_SIZE(phy_basic_ports_array), ARRAY_SIZE(phy_basic_ports_array),
pcs->supported); pcs->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, pcs->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported); linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, pcs->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported); linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, pcs->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported); linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported);
if (pcs->interface == PHY_INTERFACE_MODE_2500BASEX || if (pcs->interface == PHY_INTERFACE_MODE_2500BASEX ||
pcs->interface == PHY_INTERFACE_MODE_USXGMII) pcs->interface == PHY_INTERFACE_MODE_USXGMII)

1
include/linux/fsl/enetc_mdio.h
View File

@@ -15,6 +15,7 @@
#define ENETC_PCS_IF_MODE_SGMII_EN BIT(0) #define ENETC_PCS_IF_MODE_SGMII_EN BIT(0)
#define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1) #define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1)
#define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2)) #define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2))
#define ENETC_PCS_IF_MODE_DUPLEX_HALF BIT(3)
/* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset /* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset
* Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS * Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS