mpt3sas: Added support for high port count HBA variants.
Updated hardware description headers with MPI v2.6 and mpt3sas_pci_table[] with vendor_ids, device_ids of Cutlass and Intruder HBA which have support for 4 ports. Signed-off-by: Suganath prabu Subramani <suganath-prabu.subramani@avagotech.com> Signed-off-by: Chaitra P B <chaitra.basappa@avagotech.com> Reviewed-by: Tomas Henzl <thenzl@redhat.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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committed by
Martin K. Petersen

parent
8038e6456a
commit
b130b0d56f
@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2000-2014 LSI Corporation.
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* Copyright 2000-2015 Avago Technologies. All rights reserved.
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*
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*
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* Name: mpi2.h
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@@ -8,7 +8,7 @@
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* scatter/gather formats.
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* Creation Date: June 21, 2006
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*
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* mpi2.h Version: 02.00.35
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* mpi2.h Version: 02.00.37
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*
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* NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
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* prefix are for use only on MPI v2.5 products, and must not be used
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@@ -92,6 +92,12 @@
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* 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
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* 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT
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* 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
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* 11-18-14 02.00.36 Updated copyright information.
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* Bumped MPI2_HEADER_VERSION_UNIT.
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* 03-xx-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT.
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* Added Scratchpad registers to
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* MPI2_SYSTEM_INTERFACE_REGS.
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* Added MPI2_DIAG_SBR_RELOAD.
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* --------------------------------------------------------------------------
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*/
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@@ -124,6 +130,12 @@
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MPI25_VERSION_MINOR)
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#define MPI2_VERSION_02_05 (0x0205)
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/*minor version for MPI v2.6 compatible products */
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#define MPI26_VERSION_MINOR (0x06)
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#define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
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MPI26_VERSION_MINOR)
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#define MPI2_VERSION_02_06 (0x0206)
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/*Unit and Dev versioning for this MPI header set */
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#define MPI2_HEADER_VERSION_UNIT (0x23)
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#define MPI2_HEADER_VERSION_DEV (0x00)
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@@ -179,10 +191,12 @@ typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
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U32 HCBSize; /*0x74 */
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U32 HCBAddressLow; /*0x78 */
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U32 HCBAddressHigh; /*0x7C */
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U32 Reserved6[16]; /*0x80 */
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U32 Reserved6[12]; /*0x80 */
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U32 Scratchpad[4]; /*0xB0 */
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U32 RequestDescriptorPostLow; /*0xC0 */
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U32 RequestDescriptorPostHigh; /*0xC4 */
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U32 Reserved7[14]; /*0xC8 */
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U32 AtomicRequestDescriptorPost;/*0xC8 */
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U32 Reserved7[13]; /*0xCC */
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} MPI2_SYSTEM_INTERFACE_REGS,
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*PTR_MPI2_SYSTEM_INTERFACE_REGS,
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Mpi2SystemInterfaceRegs_t,
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@@ -224,6 +238,8 @@ typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
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*/
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#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
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#define MPI2_DIAG_SBR_RELOAD (0x00002000)
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#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
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#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
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#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
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@@ -298,10 +314,19 @@ typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
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#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
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/*
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*Offsets for the Request Queue
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*Offsets for the Scratchpad registers
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*/
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#define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
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#define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
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#define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
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#define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
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/*
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*Offsets for the Request Descriptor Post Queue
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*/
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#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
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#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
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#define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
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/*Hard Reset delay timings */
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#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
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@@ -329,7 +354,8 @@ typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
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*pMpi2DefaultRequestDescriptor_t;
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/*defines for the RequestFlags field */
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#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
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#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
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#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1)
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#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
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#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
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#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
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@@ -337,7 +363,7 @@ typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
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#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
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#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
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#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
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#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
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/*High Priority Request Descriptor */
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typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
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@@ -408,6 +434,33 @@ typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
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Mpi2RequestDescriptorUnion_t,
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*pMpi2RequestDescriptorUnion_t;
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/*Atomic Request Descriptors */
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/*
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* All Atomic Request Descriptors have the same format, so the following
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* structure is used for all Atomic Request Descriptors:
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* Atomic Default Request Descriptor
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* Atomic High Priority Request Descriptor
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* Atomic SCSI IO Request Descriptor
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* Atomic SCSI Target Request Descriptor
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* Atomic RAID Accelerator Request Descriptor
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* Atomic Fast Path SCSI IO Request Descriptor
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*/
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/*Atomic Request Descriptor */
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typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR {
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U8 RequestFlags; /* 0x00 */
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U8 MSIxIndex; /* 0x01 */
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U16 SMID; /* 0x02 */
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} MPI26_ATOMIC_REQUEST_DESCRIPTOR,
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*PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
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Mpi26AtomicRequestDescriptor_t,
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*pMpi26AtomicRequestDescriptor_t;
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/*for the RequestFlags field, use the same
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*defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR
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*/
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/*Reply Descriptors */
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/*Default Reply Descriptor */
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@@ -548,6 +601,7 @@ typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
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#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
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#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
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#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
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#define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B)
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#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
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#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
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#define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
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@@ -587,6 +641,7 @@ typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
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#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
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#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
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#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
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#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
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/****************************************************************************
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* Config IOCStatus values
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@@ -1045,7 +1100,7 @@ typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
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Mpi2IeeeSgeChainUnion_t,
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*pMpi2IeeeSgeChainUnion_t;
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/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */
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/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
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typedef struct _MPI25_IEEE_SGE_CHAIN64 {
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U64 Address;
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U32 Length;
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@@ -1098,6 +1153,11 @@ typedef union _MPI25_SGE_IO_UNION {
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#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
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#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
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/*Next Segment Format */
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#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
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#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
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/*Data Location Address Space */
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#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
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@@ -1108,6 +1168,7 @@ typedef union _MPI25_SGE_IO_UNION {
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#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
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#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
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(MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
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#define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02)
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/****************************************************************************
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* IEEE SGE operation Macros
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@@ -1166,6 +1227,7 @@ typedef union _MPI2_SGE_IO_UNION {
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#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
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#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
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#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
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#define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
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#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
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/*values for SGL Type subfield */
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#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
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