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Merge commit 'v3.17' into next

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This commit is contained in:
James Morris
2014-11-19 21:32:12 +11:00
parent 594081ee71 bfe01a5ba2
commit b10778a00d
10177 changed files with 437869 additions and 456249 deletions
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18
include/acpi/acconfig.h
View File

@@ -217,6 +217,24 @@
#define ACPI_NUM_sx_d_METHODS 4
#define ACPI_NUM_sx_w_METHODS 5
/******************************************************************************
*
* Miscellaneous constants
*
*****************************************************************************/
/* UUID constants */
#define UUID_BUFFER_LENGTH 16 /* Length of UUID in memory */
#define UUID_STRING_LENGTH 36 /* Total length of a UUID string */
/* Positions for required hyphens (dashes) in UUID strings */
#define UUID_HYPHEN1_OFFSET 8
#define UUID_HYPHEN2_OFFSET 13
#define UUID_HYPHEN3_OFFSET 18
#define UUID_HYPHEN4_OFFSET 23
/******************************************************************************
*
* ACPI AML Debugger

1
include/acpi/acnames.h
View File

@@ -55,6 +55,7 @@
#define METHOD_NAME__HID "_HID"
#define METHOD_NAME__INI "_INI"
#define METHOD_NAME__PLD "_PLD"
#define METHOD_NAME__DSD "_DSD"
#define METHOD_NAME__PRS "_PRS"
#define METHOD_NAME__PRT "_PRT"
#define METHOD_NAME__PRW "_PRW"

48
include/acpi/acpi_bus.h
View File

@@ -118,6 +118,7 @@ struct acpi_device;
struct acpi_hotplug_profile {
struct kobject kobj;
int (*scan_dependent)(struct acpi_device *adev);
void (*notify_online)(struct acpi_device *adev);
bool enabled:1;
bool demand_offline:1;
};
@@ -204,10 +205,9 @@ struct acpi_device_flags {
u32 match_driver:1;
u32 initialized:1;
u32 visited:1;
u32 no_hotplug:1;
u32 hotplug_notify:1;
u32 is_dock_station:1;
u32 reserved:22;
u32 reserved:23;
};
/* File System */
@@ -246,7 +246,6 @@ struct acpi_device_pnp {
acpi_device_name device_name; /* Driver-determined */
acpi_device_class device_class; /* " */
union acpi_object *str_obj; /* unicode string for _STR method */
unsigned long sun; /* _SUN */
};
#define acpi_device_bid(d) ((d)->pnp.bus_id)
@@ -315,12 +314,19 @@ struct acpi_device_wakeup_flags {
u8 notifier_present:1; /* Wake-up notify handler has been installed */
};
struct acpi_device_wakeup_context {
struct work_struct work;
struct device *dev;
};
struct acpi_device_wakeup {
acpi_handle gpe_device;
u64 gpe_number;
u64 sleep_state;
struct list_head resources;
struct acpi_device_wakeup_flags flags;
struct acpi_device_wakeup_context context;
struct wakeup_source *ws;
int prepare_count;
};
@@ -372,15 +378,9 @@ static inline void acpi_set_device_status(struct acpi_device *adev, u32 sta)
}
static inline void acpi_set_hp_context(struct acpi_device *adev,
struct acpi_hotplug_context *hp,
int (*notify)(struct acpi_device *, u32),
void (*uevent)(struct acpi_device *, u32),
void (*fixup)(struct acpi_device *))
struct acpi_hotplug_context *hp)
{
hp->self = adev;
hp->notify = notify;
hp->uevent = uevent;
hp->fixup = fixup;
adev->hp = hp;
}
@@ -411,7 +411,6 @@ void acpi_bus_private_data_handler(acpi_handle, void *);
int acpi_bus_get_private_data(acpi_handle, void **);
int acpi_bus_attach_private_data(acpi_handle, void *);
void acpi_bus_detach_private_data(acpi_handle);
void acpi_bus_no_hotplug(acpi_handle handle);
extern int acpi_notifier_call_chain(struct acpi_device *, u32, u32);
extern int register_acpi_notifier(struct notifier_block *);
extern int unregister_acpi_notifier(struct notifier_block *);
@@ -487,6 +486,8 @@ struct acpi_bus_type {
};
int register_acpi_bus_type(struct acpi_bus_type *);
int unregister_acpi_bus_type(struct acpi_bus_type *);
int acpi_bind_one(struct device *dev, struct acpi_device *adev);
int acpi_unbind_one(struct device *dev);
struct acpi_pci_root {
struct acpi_device * device;
@@ -510,20 +511,18 @@ int acpi_enable_wakeup_device_power(struct acpi_device *dev, int state);
int acpi_disable_wakeup_device_power(struct acpi_device *dev);
#ifdef CONFIG_PM
acpi_status acpi_add_pm_notifier(struct acpi_device *adev,
acpi_notify_handler handler, void *context);
acpi_status acpi_remove_pm_notifier(struct acpi_device *adev,
acpi_notify_handler handler);
acpi_status acpi_add_pm_notifier(struct acpi_device *adev, struct device *dev,
void (*work_func)(struct work_struct *work));
acpi_status acpi_remove_pm_notifier(struct acpi_device *adev);
int acpi_pm_device_sleep_state(struct device *, int *, int);
#else
static inline acpi_status acpi_add_pm_notifier(struct acpi_device *adev,
acpi_notify_handler handler,
void *context)
struct device *dev,
void (*work_func)(struct work_struct *work))
{
return AE_SUPPORT;
}
static inline acpi_status acpi_remove_pm_notifier(struct acpi_device *adev,
acpi_notify_handler handler)
static inline acpi_status acpi_remove_pm_notifier(struct acpi_device *adev)
{
return AE_SUPPORT;
}
@@ -538,13 +537,8 @@ static inline int acpi_pm_device_sleep_state(struct device *d, int *p, int m)
#endif
#ifdef CONFIG_PM_RUNTIME
int __acpi_device_run_wake(struct acpi_device *, bool);
int acpi_pm_device_run_wake(struct device *, bool);
#else
static inline int __acpi_device_run_wake(struct acpi_device *adev, bool en)
{
return -ENODEV;
}
static inline int acpi_pm_device_run_wake(struct device *dev, bool enable)
{
return -ENODEV;
@@ -552,14 +546,8 @@ static inline int acpi_pm_device_run_wake(struct device *dev, bool enable)
#endif
#ifdef CONFIG_PM_SLEEP
int __acpi_device_sleep_wake(struct acpi_device *, u32, bool);
int acpi_pm_device_sleep_wake(struct device *, bool);
#else
static inline int __acpi_device_sleep_wake(struct acpi_device *adev,
u32 target_state, bool enable)
{
return -ENODEV;
}
static inline int acpi_pm_device_sleep_wake(struct device *dev, bool enable)
{
return -ENODEV;

31
include/acpi/acpiosxf.h
View File

@@ -399,4 +399,35 @@ char *acpi_os_get_next_filename(void *dir_handle);
void acpi_os_close_directory(void *dir_handle);
#endif
/*
* File I/O and related support
*/
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_open_file
ACPI_FILE acpi_os_open_file(const char *path, u8 modes);
#endif
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_close_file
void acpi_os_close_file(ACPI_FILE file);
#endif
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_read_file
int
acpi_os_read_file(ACPI_FILE file,
void *buffer, acpi_size size, acpi_size count);
#endif
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_write_file
int
acpi_os_write_file(ACPI_FILE file,
void *buffer, acpi_size size, acpi_size count);
#endif
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_get_file_offset
long acpi_os_get_file_offset(ACPI_FILE file);
#endif
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_set_file_offset
acpi_status acpi_os_set_file_offset(ACPI_FILE file, long offset, u8 from);
#endif
#endif /* __ACPIOSXF_H__ */

54
include/acpi/acpixf.h
View File

@@ -46,15 +46,13 @@
/* Current ACPICA subsystem version in YYYYMMDD format */
#define ACPI_CA_VERSION 0x20140424
#define ACPI_CA_VERSION 0x20140724
#include <acpi/acconfig.h>
#include <acpi/actypes.h>
#include <acpi/actbl.h>
#include <acpi/acbuffer.h>
extern u8 acpi_gbl_permanent_mmap;
/*****************************************************************************
*
* Macros used for ACPICA globals and configuration
@@ -335,6 +333,23 @@ ACPI_GLOBAL(u8, acpi_gbl_system_awake_and_running);
#endif /* ACPI_DEBUG_OUTPUT */
/*
* Application prototypes
*
* All interfaces used by application will be configured
* out of the ACPICA build unless the ACPI_APPLICATION
* flag is defined.
*/
#ifdef ACPI_APPLICATION
#define ACPI_APP_DEPENDENT_RETURN_VOID(prototype) \
prototype;
#else
#define ACPI_APP_DEPENDENT_RETURN_VOID(prototype) \
static ACPI_INLINE prototype {return;}
#endif /* ACPI_APPLICATION */
/*****************************************************************************
*
* ACPICA public interface prototypes
@@ -657,6 +672,10 @@ ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status
acpi_finish_gpe(acpi_handle gpe_device,
u32 gpe_number))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status
acpi_mark_gpe_for_wake(acpi_handle gpe_device,
u32 gpe_number))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status
acpi_setup_gpe_for_wake(acpi_handle
parent_device,
@@ -861,21 +880,32 @@ ACPI_DBG_DEPENDENT_RETURN_VOID(ACPI_PRINTF_LIKE(6)
const char *module_name,
u32 component_id,
const char *format, ...))
ACPI_APP_DEPENDENT_RETURN_VOID(ACPI_PRINTF_LIKE(1)
void ACPI_INTERNAL_VAR_XFACE
acpi_log_error(const char *format, ...))
/*
* Divergences
*/
acpi_status acpi_get_id(acpi_handle object, acpi_owner_id * out_type);
ACPI_GLOBAL(u8, acpi_gbl_permanent_mmap);
acpi_status acpi_unload_table_id(acpi_owner_id id);
ACPI_EXTERNAL_RETURN_STATUS(acpi_status
acpi_get_id(acpi_handle object,
acpi_owner_id * out_type))
acpi_status
acpi_get_table_with_size(acpi_string signature,
u32 instance, struct acpi_table_header **out_table,
acpi_size *tbl_size);
ACPI_EXTERNAL_RETURN_STATUS(acpi_status acpi_unload_table_id(acpi_owner_id id))
acpi_status
acpi_get_data_full(acpi_handle object, acpi_object_handler handler, void **data,
void (*callback)(void *));
ACPI_EXTERNAL_RETURN_STATUS(acpi_status
acpi_get_table_with_size(acpi_string signature,
u32 instance,
struct acpi_table_header
**out_table,
acpi_size *tbl_size))
ACPI_EXTERNAL_RETURN_STATUS(acpi_status
acpi_get_data_full(acpi_handle object,
acpi_object_handler handler,
void **data,
void (*callback)(void *)))
#endif /* __ACXFACE_H__ */

12
include/acpi/actbl.h
View File

@@ -270,7 +270,8 @@ struct acpi_table_fadt {
u32 flags; /* Miscellaneous flag bits (see below for individual flags) */
struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */
u8 reset_value; /* Value to write to the reset_register port to reset the system */
u8 reserved4[3]; /* Reserved, must be zero */
u16 arm_boot_flags; /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
u8 minor_revision; /* FADT Minor Revision (ACPI 5.1) */
u64 Xfacs; /* 64-bit physical address of FACS */
u64 Xdsdt; /* 64-bit physical address of DSDT */
struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
@@ -285,7 +286,7 @@ struct acpi_table_fadt {
struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */
};
/* Masks for FADT Boot Architecture Flags (boot_flags) [Vx]=Introduced in this FADT revision */
/* Masks for FADT IA-PC Boot Architecture Flags (boot_flags) [Vx]=Introduced in this FADT revision */
#define ACPI_FADT_LEGACY_DEVICES (1) /* 00: [V2] System has LPC or ISA bus devices */
#define ACPI_FADT_8042 (1<<1) /* 01: [V3] System has an 8042 controller on port 60/64 */
@@ -296,6 +297,11 @@ struct acpi_table_fadt {
#define FADT2_REVISION_ID 3
/* Masks for FADT ARM Boot Architecture Flags (arm_boot_flags) ACPI 5.1 */
#define ACPI_FADT_PSCI_COMPLIANT (1) /* 00: [V5+] PSCI 0.2+ is implemented */
#define ACPI_FADT_PSCI_USE_HVC (1<<1) /* 01: [V5+] HVC must be used instead of SMC as the PSCI conduit */
/* Masks for FADT flags */
#define ACPI_FADT_WBINVD (1) /* 00: [V1] The WBINVD instruction works properly */
@@ -399,7 +405,7 @@ struct acpi_table_desc {
* FADT V5 size: 0x10C
*/
#define ACPI_FADT_V1_SIZE (u32) (ACPI_FADT_OFFSET (flags) + 4)
#define ACPI_FADT_V2_SIZE (u32) (ACPI_FADT_OFFSET (reserved4[0]) + 3)
#define ACPI_FADT_V2_SIZE (u32) (ACPI_FADT_OFFSET (minor_revision) + 1)
#define ACPI_FADT_V3_SIZE (u32) (ACPI_FADT_OFFSET (sleep_control))
#define ACPI_FADT_V5_SIZE (u32) (sizeof (struct acpi_table_fadt))

58
include/acpi/actbl1.h
View File

@@ -604,7 +604,7 @@ struct acpi_hest_generic {
/* Generic Error Status block */
struct acpi_generic_status {
struct acpi_hest_generic_status {
u32 block_status;
u32 raw_data_offset;
u32 raw_data_length;
@@ -614,15 +614,15 @@ struct acpi_generic_status {
/* Values for block_status flags above */
#define ACPI_GEN_ERR_UC BIT(0)
#define ACPI_GEN_ERR_CE BIT(1)
#define ACPI_GEN_ERR_MULTI_UC BIT(2)
#define ACPI_GEN_ERR_MULTI_CE BIT(3)
#define ACPI_GEN_ERR_COUNT_SHIFT (0xFF<<4) /* 8 bits, error count */
#define ACPI_HEST_UNCORRECTABLE (1)
#define ACPI_HEST_CORRECTABLE (1<<1)
#define ACPI_HEST_MULTIPLE_UNCORRECTABLE (1<<2)
#define ACPI_HEST_MULTIPLE_CORRECTABLE (1<<3)
#define ACPI_HEST_ERROR_ENTRY_COUNT (0xFF<<4) /* 8 bits, error count */
/* Generic Error Data entry */
struct acpi_generic_data {
struct acpi_hest_generic_data {
u8 section_type[16];
u32 error_severity;
u16 revision;
@@ -671,7 +671,9 @@ enum acpi_madt_type {
ACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,
ACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,
ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,
ACPI_MADT_TYPE_RESERVED = 13 /* 13 and greater are reserved */
ACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,
ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,
ACPI_MADT_TYPE_RESERVED = 15 /* 15 and greater are reserved */
};
/*
@@ -797,15 +799,26 @@ struct acpi_madt_local_x2apic_nmi {
struct acpi_madt_generic_interrupt {
struct acpi_subtable_header header;
u16 reserved; /* reserved - must be zero */
u32 gic_id;
u32 cpu_interface_number;
u32 uid;
u32 flags;
u32 parking_version;
u32 performance_interrupt;
u64 parked_address;
u64 base_address;
u64 gicv_base_address;
u64 gich_base_address;
u32 vgic_interrupt;
u64 gicr_base_address;
u64 arm_mpidr;
};
/* Masks for Flags field above */
/* ACPI_MADT_ENABLED (1) Processor is usable if set */
#define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */
#define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */
/* 12: Generic Distributor (ACPI 5.0) */
struct acpi_madt_generic_distributor {
@@ -817,11 +830,36 @@ struct acpi_madt_generic_distributor {
u32 reserved2; /* reserved - must be zero */
};
/* 13: Generic MSI Frame (ACPI 5.1) */
struct acpi_madt_generic_msi_frame {
struct acpi_subtable_header header;
u16 reserved; /* reserved - must be zero */
u32 msi_frame_id;
u64 base_address;
u32 flags;
u16 spi_count;
u16 spi_base;
};
/* Masks for Flags field above */
#define ACPI_MADT_OVERRIDE_SPI_VALUES (1)
/* 14: Generic Redistributor (ACPI 5.1) */
struct acpi_madt_generic_redistributor {
struct acpi_subtable_header header;
u16 reserved; /* reserved - must be zero */
u64 base_address;
u32 length;
};
/*
* Common flags fields for MADT subtables
*/
/* MADT Local APIC flags (lapic_flags) and GIC flags */
/* MADT Local APIC flags */
#define ACPI_MADT_ENABLED (1) /* 00: Processor is usable if set */

14
include/acpi/actbl2.h
View File

@@ -396,7 +396,7 @@ struct acpi_table_dbgp {
* Version 1
*
* Conforms to "Intel Virtualization Technology for Directed I/O",
* Version 1.2, Sept. 2008
* Version 2.2, Sept. 2013
*
******************************************************************************/
@@ -423,9 +423,9 @@ struct acpi_dmar_header {
enum acpi_dmar_type {
ACPI_DMAR_TYPE_HARDWARE_UNIT = 0,
ACPI_DMAR_TYPE_RESERVED_MEMORY = 1,
ACPI_DMAR_TYPE_ATSR = 2,
ACPI_DMAR_HARDWARE_AFFINITY = 3,
ACPI_DMAR_TYPE_ANDD = 4,
ACPI_DMAR_TYPE_ROOT_ATS = 2,
ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,
ACPI_DMAR_TYPE_NAMESPACE = 4,
ACPI_DMAR_TYPE_RESERVED = 5 /* 5 and greater are reserved */
};
@@ -439,7 +439,7 @@ struct acpi_dmar_device_scope {
u8 bus;
};
/* Values for entry_type in struct acpi_dmar_device_scope */
/* Values for entry_type in struct acpi_dmar_device_scope - device types */
enum acpi_dmar_scope_type {
ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0,
@@ -447,7 +447,7 @@ enum acpi_dmar_scope_type {
ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2,
ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3,
ACPI_DMAR_SCOPE_TYPE_HPET = 4,
ACPI_DMAR_SCOPE_TYPE_ACPI = 5,
ACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5,
ACPI_DMAR_SCOPE_TYPE_RESERVED = 6 /* 6 and greater are reserved */
};
@@ -516,7 +516,7 @@ struct acpi_dmar_andd {
struct acpi_dmar_header header;
u8 reserved[3];
u8 device_number;
u8 object_name[];
char device_name[1];
};
/*******************************************************************************

118
include/acpi/actbl3.h
View File

@@ -241,33 +241,96 @@ struct acpi_s3pt_suspend {
/*******************************************************************************
*
* GTDT - Generic Timer Description Table (ACPI 5.0)
* Version 1
* GTDT - Generic Timer Description Table (ACPI 5.1)
* Version 2
*
******************************************************************************/
struct acpi_table_gtdt {
struct acpi_table_header header; /* Common ACPI table header */
u64 address;
u32 flags;
u32 secure_pl1_interrupt;
u32 secure_pl1_flags;
u32 non_secure_pl1_interrupt;
u32 non_secure_pl1_flags;
u64 counter_block_addresss;
u32 reserved;
u32 secure_el1_interrupt;
u32 secure_el1_flags;
u32 non_secure_el1_interrupt;
u32 non_secure_el1_flags;
u32 virtual_timer_interrupt;
u32 virtual_timer_flags;
u32 non_secure_pl2_interrupt;
u32 non_secure_pl2_flags;
u32 non_secure_el2_interrupt;
u32 non_secure_el2_flags;
u64 counter_read_block_address;
u32 platform_timer_count;
u32 platform_timer_offset;
};
/* Values for Flags field above */
/* Flag Definitions: Timer Block Physical Timers and Virtual timers */
#define ACPI_GTDT_MAPPED_BLOCK_PRESENT 1
#define ACPI_GTDT_INTERRUPT_MODE (1)
#define ACPI_GTDT_INTERRUPT_POLARITY (1<<1)
#define ACPI_GTDT_ALWAYS_ON (1<<2)
/* Values for all "TimerFlags" fields above */
/* Common GTDT subtable header */
#define ACPI_GTDT_INTERRUPT_MODE 1
#define ACPI_GTDT_INTERRUPT_POLARITY 2
struct acpi_gtdt_header {
u8 type;
u16 length;
};
/* Values for GTDT subtable type above */
enum acpi_gtdt_type {
ACPI_GTDT_TYPE_TIMER_BLOCK = 0,
ACPI_GTDT_TYPE_WATCHDOG = 1,
ACPI_GTDT_TYPE_RESERVED = 2 /* 2 and greater are reserved */
};
/* GTDT Subtables, correspond to Type in struct acpi_gtdt_header */
/* 0: Generic Timer Block */
struct acpi_gtdt_timer_block {
struct acpi_gtdt_header header;
u8 reserved;
u64 block_address;
u32 timer_count;
u32 timer_offset;
};
/* Timer Sub-Structure, one per timer */
struct acpi_gtdt_timer_entry {
u8 frame_number;
u8 reserved[3];
u64 base_address;
u64 el0_base_address;
u32 timer_interrupt;
u32 timer_flags;
u32 virtual_timer_interrupt;
u32 virtual_timer_flags;
u32 common_flags;
};
/* Flag Definitions: common_flags above */
#define ACPI_GTDT_GT_IS_SECURE_TIMER (1)
#define ACPI_GTDT_GT_ALWAYS_ON (1<<1)
/* 1: SBSA Generic Watchdog Structure */
struct acpi_gtdt_watchdog {
struct acpi_gtdt_header header;
u8 reserved;
u64 refresh_frame_address;
u64 control_frame_address;
u32 timer_interrupt;
u32 timer_flags;
};
/* Flag Definitions: timer_flags above */
#define ACPI_GTDT_WATCHDOG_IRQ_MODE (1)
#define ACPI_GTDT_WATCHDOG_IRQ_POLARITY (1<<1)
#define ACPI_GTDT_WATCHDOG_SECURE (1<<2)
/*******************************************************************************
*
@@ -385,7 +448,8 @@ struct acpi_table_pcct {
enum acpi_pcct_type {
ACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,
ACPI_PCCT_TYPE_RESERVED = 1 /* 1 and greater are reserved */
ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,
ACPI_PCCT_TYPE_RESERVED = 2 /* 2 and greater are reserved */
};
/*
@@ -407,6 +471,28 @@ struct acpi_pcct_subspace {
u16 min_turnaround_time;
};
/* 1: HW-reduced Communications Subspace (ACPI 5.1) */
struct acpi_pcct_hw_reduced {
struct acpi_subtable_header header;
u32 doorbell_interrupt;
u8 flags;
u8 reserved;
u64 base_address;
u64 length;
struct acpi_generic_address doorbell_register;
u64 preserve_mask;
u64 write_mask;
u32 latency;
u32 max_access_rate;
u16 min_turnaround_time;
};
/* Values for doorbell flags above */
#define ACPI_PCCT_INTERRUPT_POLARITY (1)
#define ACPI_PCCT_INTERRUPT_MODE (1<<1)
/*
* PCC memory structures (not part of the ACPI table)
*/

19
include/acpi/actypes.h
View File

@@ -126,6 +126,7 @@
typedef unsigned char u8;
typedef unsigned char u8;
typedef unsigned short u16;
typedef short s16;
typedef COMPILER_DEPENDENT_UINT64 u64;
typedef COMPILER_DEPENDENT_INT64 s64;
@@ -516,7 +517,7 @@ typedef u64 acpi_integer;
#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void, (void *) NULL,(acpi_size) i)
#define ACPI_TO_INTEGER(p) ACPI_PTR_DIFF (p, (void *) NULL)
#define ACPI_OFFSET(d, f) (acpi_size) ACPI_PTR_DIFF (&(((d *)0)->f), (void *) NULL)
#define ACPI_OFFSET(d, f) ACPI_PTR_DIFF (&(((d *) 0)->f), (void *) NULL)
#define ACPI_PHYSADDR_TO_PTR(i) ACPI_TO_POINTER(i)
#define ACPI_PTR_TO_PHYSADDR(i) ACPI_TO_INTEGER(i)
@@ -611,8 +612,9 @@ typedef u64 acpi_integer;
#define ACPI_NOTIFY_RESERVED (u8) 0x0A
#define ACPI_NOTIFY_LOCALITY_UPDATE (u8) 0x0B
#define ACPI_NOTIFY_SHUTDOWN_REQUEST (u8) 0x0C
#define ACPI_NOTIFY_AFFINITY_UPDATE (u8) 0x0D
#define ACPI_NOTIFY_MAX 0x0C
#define ACPI_NOTIFY_MAX 0x0D
/*
* Types associated with ACPI names and objects. The first group of
@@ -1244,4 +1246,17 @@ struct acpi_memory_list {
#define ACPI_OSI_WIN_7 0x0B
#define ACPI_OSI_WIN_8 0x0C
/* Definitions of file IO */
#define ACPI_FILE_READING 0x01
#define ACPI_FILE_WRITING 0x02
#define ACPI_FILE_BINARY 0x04
#define ACPI_FILE_BEGIN 0x01
#define ACPI_FILE_END 0x02
/* Definitions of getopt */
#define ACPI_OPT_END -1
#endif /* __ACTYPES_H__ */

4
include/acpi/apei.h
View File

@@ -42,5 +42,9 @@ ssize_t erst_read(u64 record_id, struct cper_record_header *record,
size_t buflen);
int erst_clear(u64 record_id);
int arch_apei_enable_cmcff(struct acpi_hest_header *hest_hdr, void *data);
void arch_apei_report_mem_error(int sev, struct cper_sec_mem_err *mem_err);
void arch_apei_flush_tlb_one(unsigned long addr);
#endif
#endif

2
include/acpi/ghes.h
View File

@@ -14,7 +14,7 @@
struct ghes {
struct acpi_hest_generic *generic;
struct acpi_generic_status *estatus;
struct acpi_hest_generic_status *estatus;
u64 buffer_paddr;
unsigned long flags;
union {

53
include/acpi/platform/acenv.h
View File

@@ -87,20 +87,14 @@
#define ACPI_DBG_TRACK_ALLOCATIONS
#endif
/* acpi_names configuration. Single threaded with debugger output enabled. */
#ifdef ACPI_NAMES_APP
#define ACPI_DEBUGGER
#define ACPI_APPLICATION
#define ACPI_SINGLE_THREADED
#endif
/*
* acpi_bin/acpi_dump/acpi_src/acpi_xtract/Example configuration. All single
* threaded, with no debug output.
* acpi_bin/acpi_dump/acpi_help/acpi_names/acpi_src/acpi_xtract/Example configuration.
* All single threaded.
*/
#if (defined ACPI_BIN_APP) || \
(defined ACPI_DUMP_APP) || \
(defined ACPI_HELP_APP) || \
(defined ACPI_NAMES_APP) || \
(defined ACPI_SRC_APP) || \
(defined ACPI_XTRACT_APP) || \
(defined ACPI_EXAMPLE_APP)
@@ -108,12 +102,40 @@
#define ACPI_SINGLE_THREADED
#endif
/* acpi_help configuration. Error messages disabled. */
#ifdef ACPI_HELP_APP
#define ACPI_APPLICATION
#define ACPI_SINGLE_THREADED
#define ACPI_NO_ERROR_MESSAGES
#endif
/* acpi_names configuration. Debug output enabled. */
#ifdef ACPI_NAMES_APP
#define ACPI_DEBUG_OUTPUT
#endif
/* acpi_exec/acpi_names/Example configuration. Native RSDP used. */
#if (defined ACPI_EXEC_APP) || \
(defined ACPI_EXAMPLE_APP) || \
(defined ACPI_NAMES_APP)
#define ACPI_USE_NATIVE_RSDP_POINTER
#endif
/* acpi_dump configuration. Native mapping used if provied by OSPMs */
#ifdef ACPI_DUMP_APP
#define ACPI_USE_NATIVE_MEMORY_MAPPING
#define USE_NATIVE_ALLOCATE_ZEROED
#endif
/* acpi_names/Example configuration. Hardware disabled */
#if (defined ACPI_EXAMPLE_APP) || \
(defined ACPI_NAMES_APP)
#define ACPI_REDUCED_HARDWARE 1
#endif
/* Linkable ACPICA library */
#ifdef ACPI_LIBRARY
@@ -185,6 +207,9 @@
#elif defined(_AED_EFI)
#include "acefi.h"
#elif defined(_GNU_EFI)
#include "acefi.h"
#elif defined(__HAIKU__)
#include "achaiku.h"
@@ -399,8 +424,12 @@ typedef char *va_list;
#ifdef ACPI_APPLICATION
#include <stdio.h>
#define ACPI_FILE FILE *
#define ACPI_FILE_OUT stdout
#define ACPI_FILE_ERR stderr
#else
#define ACPI_FILE void *
#define ACPI_FILE_OUT NULL
#define ACPI_FILE_ERR NULL
#endif /* ACPI_APPLICATION */
#endif /* ACPI_FILE */

12
include/acpi/platform/aclinux.h
View File

@@ -44,6 +44,16 @@
#ifndef __ACLINUX_H__
#define __ACLINUX_H__
#ifdef __KERNEL__
/* ACPICA external files should not include ACPICA headers directly. */
#if !defined(BUILDING_ACPICA) && !defined(_LINUX_ACPI_H)
#error "Please don't include <acpi/acpi.h> directly, include <linux/acpi.h> instead."
#endif
#endif
/* Common (in-kernel/user-space) ACPICA configuration */
#define ACPI_USE_SYSTEM_CLIBRARY
@@ -70,7 +80,9 @@
#ifdef EXPORT_ACPI_INTERFACES
#include <linux/export.h>
#endif
#ifdef CONFIG_ACPI
#include <asm/acenv.h>
#endif
#ifndef CONFIG_ACPI

22
include/acpi/platform/aclinuxex.h
View File

@@ -46,6 +46,28 @@
#ifdef __KERNEL__
#ifndef ACPI_USE_NATIVE_DIVIDE
#ifndef ACPI_DIV_64_BY_32
#define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \
do { \
u64 (__n) = ((u64) n_hi) << 32 | (n_lo); \
(r32) = do_div ((__n), (d32)); \
(q32) = (u32) (__n); \
} while (0)
#endif
#ifndef ACPI_SHIFT_RIGHT_64
#define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \
do { \
(n_lo) >>= 1; \
(n_lo) |= (((n_hi) & 1) << 31); \
(n_hi) >>= 1; \
} while (0)
#endif
#endif
/*
* Overrides for in-kernel ACPICA
*/

3
include/asm-generic/gpio.h
View File

@@ -110,9 +110,6 @@ static inline int __gpio_to_irq(unsigned gpio)
return gpiod_to_irq(gpio_to_desc(gpio));
}
extern int gpio_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
extern void gpio_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
extern int gpio_request_one(unsigned gpio, unsigned long flags, const char *label);
extern int gpio_request_array(const struct gpio *array, size_t num);
extern void gpio_free_array(const struct gpio *array, size_t num);

14
include/asm-generic/io-64-nonatomic-hi-lo.h
View File

@@ -4,8 +4,7 @@
#include <linux/io.h>
#include <asm-generic/int-ll64.h>
#ifndef readq
static inline __u64 readq(const volatile void __iomem *addr)
static inline __u64 hi_lo_readq(const volatile void __iomem *addr)
{
const volatile u32 __iomem *p = addr;
u32 low, high;
@@ -15,14 +14,19 @@ static inline __u64 readq(const volatile void __iomem *addr)
return low + ((u64)high << 32);
}
#endif
#ifndef writeq
static inline void writeq(__u64 val, volatile void __iomem *addr)
static inline void hi_lo_writeq(__u64 val, volatile void __iomem *addr)
{
writel(val >> 32, addr + 4);
writel(val, addr);
}
#ifndef readq
#define readq hi_lo_readq
#endif
#ifndef writeq
#define writeq hi_lo_writeq
#endif
#endif /* _ASM_IO_64_NONATOMIC_HI_LO_H_ */

14
include/asm-generic/io-64-nonatomic-lo-hi.h
View File

@@ -4,8 +4,7 @@
#include <linux/io.h>
#include <asm-generic/int-ll64.h>
#ifndef readq
static inline __u64 readq(const volatile void __iomem *addr)
static inline __u64 lo_hi_readq(const volatile void __iomem *addr)
{
const volatile u32 __iomem *p = addr;
u32 low, high;
@@ -15,14 +14,19 @@ static inline __u64 readq(const volatile void __iomem *addr)
return low + ((u64)high << 32);
}
#endif
#ifndef writeq
static inline void writeq(__u64 val, volatile void __iomem *addr)
static inline void lo_hi_writeq(__u64 val, volatile void __iomem *addr)
{
writel(val, addr);
writel(val >> 32, addr + 4);
}
#ifndef readq
#define readq lo_hi_readq
#endif
#ifndef writeq
#define writeq lo_hi_writeq
#endif
#endif /* _ASM_IO_64_NONATOMIC_LO_HI_H_ */

8
include/asm-generic/pci-dma-compat.h
View File

@@ -19,6 +19,14 @@ pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
return dma_alloc_coherent(hwdev == NULL ? NULL : &hwdev->dev, size, dma_handle, GFP_ATOMIC);
}
static inline void *
pci_zalloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t *dma_handle)
{
return dma_zalloc_coherent(hwdev == NULL ? NULL : &hwdev->dev,
size, dma_handle, GFP_ATOMIC);
}
static inline void
pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)

418
include/asm-generic/percpu.h
View File

@@ -36,55 +36,17 @@ extern unsigned long __per_cpu_offset[NR_CPUS];
#endif
/*
* Add a offset to a pointer but keep the pointer as is.
*
* Only S390 provides its own means of moving the pointer.
* Arch may define arch_raw_cpu_ptr() to provide more efficient address
* translations for raw_cpu_ptr().
*/
#ifndef SHIFT_PERCPU_PTR
/* Weird cast keeps both GCC and sparse happy. */
#define SHIFT_PERCPU_PTR(__p, __offset) ({ \
__verify_pcpu_ptr((__p)); \
RELOC_HIDE((typeof(*(__p)) __kernel __force *)(__p), (__offset)); \
})
#ifndef arch_raw_cpu_ptr
#define arch_raw_cpu_ptr(ptr) SHIFT_PERCPU_PTR(ptr, __my_cpu_offset)
#endif
/*
* A percpu variable may point to a discarded regions. The following are
* established ways to produce a usable pointer from the percpu variable
* offset.
*/
#define per_cpu(var, cpu) \
(*SHIFT_PERCPU_PTR(&(var), per_cpu_offset(cpu)))
#ifndef raw_cpu_ptr
#define raw_cpu_ptr(ptr) SHIFT_PERCPU_PTR(ptr, __my_cpu_offset)
#endif
#ifdef CONFIG_DEBUG_PREEMPT
#define this_cpu_ptr(ptr) SHIFT_PERCPU_PTR(ptr, my_cpu_offset)
#else
#define this_cpu_ptr(ptr) raw_cpu_ptr(ptr)
#endif
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
#define __raw_get_cpu_var(var) (*raw_cpu_ptr(&(var)))
#ifdef CONFIG_HAVE_SETUP_PER_CPU_AREA
extern void setup_per_cpu_areas(void);
#endif
#else /* ! SMP */
#define VERIFY_PERCPU_PTR(__p) ({ \
__verify_pcpu_ptr((__p)); \
(typeof(*(__p)) __kernel __force *)(__p); \
})
#define per_cpu(var, cpu) (*((void)(cpu), VERIFY_PERCPU_PTR(&(var))))
#define __get_cpu_var(var) (*VERIFY_PERCPU_PTR(&(var)))
#define __raw_get_cpu_var(var) (*VERIFY_PERCPU_PTR(&(var)))
#define this_cpu_ptr(ptr) per_cpu_ptr(ptr, 0)
#define raw_cpu_ptr(ptr) this_cpu_ptr(ptr)
#endif /* SMP */
#ifndef PER_CPU_BASE_SECTION
@@ -95,25 +57,6 @@ extern void setup_per_cpu_areas(void);
#endif
#endif
#ifdef CONFIG_SMP
#ifdef MODULE
#define PER_CPU_SHARED_ALIGNED_SECTION ""
#define PER_CPU_ALIGNED_SECTION ""
#else
#define PER_CPU_SHARED_ALIGNED_SECTION "..shared_aligned"
#define PER_CPU_ALIGNED_SECTION "..shared_aligned"
#endif
#define PER_CPU_FIRST_SECTION "..first"
#else
#define PER_CPU_SHARED_ALIGNED_SECTION ""
#define PER_CPU_ALIGNED_SECTION "..shared_aligned"
#define PER_CPU_FIRST_SECTION ""
#endif
#ifndef PER_CPU_ATTRIBUTES
#define PER_CPU_ATTRIBUTES
#endif
@@ -122,7 +65,356 @@ extern void setup_per_cpu_areas(void);
#define PER_CPU_DEF_ATTRIBUTES
#endif
/* Keep until we have removed all uses of __this_cpu_ptr */
#define __this_cpu_ptr raw_cpu_ptr
#define raw_cpu_generic_to_op(pcp, val, op) \
do { \
*raw_cpu_ptr(&(pcp)) op val; \
} while (0)
#define raw_cpu_generic_add_return(pcp, val) \
({ \
raw_cpu_add(pcp, val); \
raw_cpu_read(pcp); \
})
#define raw_cpu_generic_xchg(pcp, nval) \
({ \
typeof(pcp) __ret; \
__ret = raw_cpu_read(pcp); \
raw_cpu_write(pcp, nval); \
__ret; \
})
#define raw_cpu_generic_cmpxchg(pcp, oval, nval) \
({ \
typeof(pcp) __ret; \
__ret = raw_cpu_read(pcp); \
if (__ret == (oval)) \
raw_cpu_write(pcp, nval); \
__ret; \
})
#define raw_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2) \
({ \
int __ret = 0; \
if (raw_cpu_read(pcp1) == (oval1) && \
raw_cpu_read(pcp2) == (oval2)) { \
raw_cpu_write(pcp1, nval1); \
raw_cpu_write(pcp2, nval2); \
__ret = 1; \
} \
(__ret); \
})
#define this_cpu_generic_read(pcp) \
({ \
typeof(pcp) __ret; \
preempt_disable(); \
__ret = *this_cpu_ptr(&(pcp)); \
preempt_enable(); \
__ret; \
})
#define this_cpu_generic_to_op(pcp, val, op) \
do { \
unsigned long __flags; \
raw_local_irq_save(__flags); \
*raw_cpu_ptr(&(pcp)) op val; \
raw_local_irq_restore(__flags); \
} while (0)
#define this_cpu_generic_add_return(pcp, val) \
({ \
typeof(pcp) __ret; \
unsigned long __flags; \
raw_local_irq_save(__flags); \
raw_cpu_add(pcp, val); \
__ret = raw_cpu_read(pcp); \
raw_local_irq_restore(__flags); \
__ret; \
})
#define this_cpu_generic_xchg(pcp, nval) \
({ \
typeof(pcp) __ret; \
unsigned long __flags; \
raw_local_irq_save(__flags); \
__ret = raw_cpu_read(pcp); \
raw_cpu_write(pcp, nval); \
raw_local_irq_restore(__flags); \
__ret; \
})
#define this_cpu_generic_cmpxchg(pcp, oval, nval) \
({ \
typeof(pcp) __ret; \
unsigned long __flags; \
raw_local_irq_save(__flags); \
__ret = raw_cpu_read(pcp); \
if (__ret == (oval)) \
raw_cpu_write(pcp, nval); \
raw_local_irq_restore(__flags); \
__ret; \
})
#define this_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2) \
({ \
int __ret; \
unsigned long __flags; \
raw_local_irq_save(__flags); \
__ret = raw_cpu_generic_cmpxchg_double(pcp1, pcp2, \
oval1, oval2, nval1, nval2); \
raw_local_irq_restore(__flags); \
__ret; \
})
#ifndef raw_cpu_read_1
#define raw_cpu_read_1(pcp) (*raw_cpu_ptr(&(pcp)))
#endif
#ifndef raw_cpu_read_2
#define raw_cpu_read_2(pcp) (*raw_cpu_ptr(&(pcp)))
#endif
#ifndef raw_cpu_read_4
#define raw_cpu_read_4(pcp) (*raw_cpu_ptr(&(pcp)))
#endif
#ifndef raw_cpu_read_8
#define raw_cpu_read_8(pcp) (*raw_cpu_ptr(&(pcp)))
#endif
#ifndef raw_cpu_write_1
#define raw_cpu_write_1(pcp, val) raw_cpu_generic_to_op(pcp, val, =)
#endif
#ifndef raw_cpu_write_2
#define raw_cpu_write_2(pcp, val) raw_cpu_generic_to_op(pcp, val, =)
#endif
#ifndef raw_cpu_write_4
#define raw_cpu_write_4(pcp, val) raw_cpu_generic_to_op(pcp, val, =)
#endif
#ifndef raw_cpu_write_8
#define raw_cpu_write_8(pcp, val) raw_cpu_generic_to_op(pcp, val, =)
#endif
#ifndef raw_cpu_add_1
#define raw_cpu_add_1(pcp, val) raw_cpu_generic_to_op(pcp, val, +=)
#endif
#ifndef raw_cpu_add_2
#define raw_cpu_add_2(pcp, val) raw_cpu_generic_to_op(pcp, val, +=)
#endif
#ifndef raw_cpu_add_4
#define raw_cpu_add_4(pcp, val) raw_cpu_generic_to_op(pcp, val, +=)
#endif
#ifndef raw_cpu_add_8
#define raw_cpu_add_8(pcp, val) raw_cpu_generic_to_op(pcp, val, +=)
#endif
#ifndef raw_cpu_and_1
#define raw_cpu_and_1(pcp, val) raw_cpu_generic_to_op(pcp, val, &=)
#endif
#ifndef raw_cpu_and_2
#define raw_cpu_and_2(pcp, val) raw_cpu_generic_to_op(pcp, val, &=)
#endif
#ifndef raw_cpu_and_4
#define raw_cpu_and_4(pcp, val) raw_cpu_generic_to_op(pcp, val, &=)
#endif
#ifndef raw_cpu_and_8
#define raw_cpu_and_8(pcp, val) raw_cpu_generic_to_op(pcp, val, &=)
#endif
#ifndef raw_cpu_or_1
#define raw_cpu_or_1(pcp, val) raw_cpu_generic_to_op(pcp, val, |=)
#endif
#ifndef raw_cpu_or_2
#define raw_cpu_or_2(pcp, val) raw_cpu_generic_to_op(pcp, val, |=)
#endif
#ifndef raw_cpu_or_4
#define raw_cpu_or_4(pcp, val) raw_cpu_generic_to_op(pcp, val, |=)
#endif
#ifndef raw_cpu_or_8
#define raw_cpu_or_8(pcp, val) raw_cpu_generic_to_op(pcp, val, |=)
#endif
#ifndef raw_cpu_add_return_1
#define raw_cpu_add_return_1(pcp, val) raw_cpu_generic_add_return(pcp, val)
#endif
#ifndef raw_cpu_add_return_2
#define raw_cpu_add_return_2(pcp, val) raw_cpu_generic_add_return(pcp, val)
#endif
#ifndef raw_cpu_add_return_4
#define raw_cpu_add_return_4(pcp, val) raw_cpu_generic_add_return(pcp, val)
#endif
#ifndef raw_cpu_add_return_8
#define raw_cpu_add_return_8(pcp, val) raw_cpu_generic_add_return(pcp, val)
#endif
#ifndef raw_cpu_xchg_1
#define raw_cpu_xchg_1(pcp, nval) raw_cpu_generic_xchg(pcp, nval)
#endif
#ifndef raw_cpu_xchg_2
#define raw_cpu_xchg_2(pcp, nval) raw_cpu_generic_xchg(pcp, nval)
#endif
#ifndef raw_cpu_xchg_4
#define raw_cpu_xchg_4(pcp, nval) raw_cpu_generic_xchg(pcp, nval)
#endif
#ifndef raw_cpu_xchg_8
#define raw_cpu_xchg_8(pcp, nval) raw_cpu_generic_xchg(pcp, nval)
#endif
#ifndef raw_cpu_cmpxchg_1
#define raw_cpu_cmpxchg_1(pcp, oval, nval) \
raw_cpu_generic_cmpxchg(pcp, oval, nval)
#endif
#ifndef raw_cpu_cmpxchg_2
#define raw_cpu_cmpxchg_2(pcp, oval, nval) \
raw_cpu_generic_cmpxchg(pcp, oval, nval)
#endif
#ifndef raw_cpu_cmpxchg_4
#define raw_cpu_cmpxchg_4(pcp, oval, nval) \
raw_cpu_generic_cmpxchg(pcp, oval, nval)
#endif
#ifndef raw_cpu_cmpxchg_8
#define raw_cpu_cmpxchg_8(pcp, oval, nval) \
raw_cpu_generic_cmpxchg(pcp, oval, nval)
#endif
#ifndef raw_cpu_cmpxchg_double_1
#define raw_cpu_cmpxchg_double_1(pcp1, pcp2, oval1, oval2, nval1, nval2) \
raw_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
#endif
#ifndef raw_cpu_cmpxchg_double_2
#define raw_cpu_cmpxchg_double_2(pcp1, pcp2, oval1, oval2, nval1, nval2) \
raw_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
#endif
#ifndef raw_cpu_cmpxchg_double_4
#define raw_cpu_cmpxchg_double_4(pcp1, pcp2, oval1, oval2, nval1, nval2) \
raw_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
#endif
#ifndef raw_cpu_cmpxchg_double_8
#define raw_cpu_cmpxchg_double_8(pcp1, pcp2, oval1, oval2, nval1, nval2) \
raw_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
#endif
#ifndef this_cpu_read_1
#define this_cpu_read_1(pcp) this_cpu_generic_read(pcp)
#endif
#ifndef this_cpu_read_2
#define this_cpu_read_2(pcp) this_cpu_generic_read(pcp)
#endif
#ifndef this_cpu_read_4
#define this_cpu_read_4(pcp) this_cpu_generic_read(pcp)
#endif
#ifndef this_cpu_read_8
#define this_cpu_read_8(pcp) this_cpu_generic_read(pcp)
#endif
#ifndef this_cpu_write_1
#define this_cpu_write_1(pcp, val) this_cpu_generic_to_op(pcp, val, =)
#endif
#ifndef this_cpu_write_2
#define this_cpu_write_2(pcp, val) this_cpu_generic_to_op(pcp, val, =)
#endif
#ifndef this_cpu_write_4
#define this_cpu_write_4(pcp, val) this_cpu_generic_to_op(pcp, val, =)
#endif
#ifndef this_cpu_write_8
#define this_cpu_write_8(pcp, val) this_cpu_generic_to_op(pcp, val, =)
#endif
#ifndef this_cpu_add_1
#define this_cpu_add_1(pcp, val) this_cpu_generic_to_op(pcp, val, +=)
#endif
#ifndef this_cpu_add_2
#define this_cpu_add_2(pcp, val) this_cpu_generic_to_op(pcp, val, +=)
#endif
#ifndef this_cpu_add_4
#define this_cpu_add_4(pcp, val) this_cpu_generic_to_op(pcp, val, +=)
#endif
#ifndef this_cpu_add_8
#define this_cpu_add_8(pcp, val) this_cpu_generic_to_op(pcp, val, +=)
#endif
#ifndef this_cpu_and_1
#define this_cpu_and_1(pcp, val) this_cpu_generic_to_op(pcp, val, &=)
#endif
#ifndef this_cpu_and_2
#define this_cpu_and_2(pcp, val) this_cpu_generic_to_op(pcp, val, &=)
#endif
#ifndef this_cpu_and_4
#define this_cpu_and_4(pcp, val) this_cpu_generic_to_op(pcp, val, &=)
#endif
#ifndef this_cpu_and_8
#define this_cpu_and_8(pcp, val) this_cpu_generic_to_op(pcp, val, &=)
#endif
#ifndef this_cpu_or_1
#define this_cpu_or_1(pcp, val) this_cpu_generic_to_op(pcp, val, |=)
#endif
#ifndef this_cpu_or_2
#define this_cpu_or_2(pcp, val) this_cpu_generic_to_op(pcp, val, |=)
#endif
#ifndef this_cpu_or_4
#define this_cpu_or_4(pcp, val) this_cpu_generic_to_op(pcp, val, |=)
#endif
#ifndef this_cpu_or_8
#define this_cpu_or_8(pcp, val) this_cpu_generic_to_op(pcp, val, |=)
#endif
#ifndef this_cpu_add_return_1
#define this_cpu_add_return_1(pcp, val) this_cpu_generic_add_return(pcp, val)
#endif
#ifndef this_cpu_add_return_2
#define this_cpu_add_return_2(pcp, val) this_cpu_generic_add_return(pcp, val)
#endif
#ifndef this_cpu_add_return_4
#define this_cpu_add_return_4(pcp, val) this_cpu_generic_add_return(pcp, val)
#endif
#ifndef this_cpu_add_return_8
#define this_cpu_add_return_8(pcp, val) this_cpu_generic_add_return(pcp, val)
#endif
#ifndef this_cpu_xchg_1
#define this_cpu_xchg_1(pcp, nval) this_cpu_generic_xchg(pcp, nval)
#endif
#ifndef this_cpu_xchg_2
#define this_cpu_xchg_2(pcp, nval) this_cpu_generic_xchg(pcp, nval)
#endif
#ifndef this_cpu_xchg_4
#define this_cpu_xchg_4(pcp, nval) this_cpu_generic_xchg(pcp, nval)
#endif
#ifndef this_cpu_xchg_8
#define this_cpu_xchg_8(pcp, nval) this_cpu_generic_xchg(pcp, nval)
#endif
#ifndef this_cpu_cmpxchg_1
#define this_cpu_cmpxchg_1(pcp, oval, nval) \
this_cpu_generic_cmpxchg(pcp, oval, nval)
#endif
#ifndef this_cpu_cmpxchg_2
#define this_cpu_cmpxchg_2(pcp, oval, nval) \
this_cpu_generic_cmpxchg(pcp, oval, nval)
#endif
#ifndef this_cpu_cmpxchg_4
#define this_cpu_cmpxchg_4(pcp, oval, nval) \
this_cpu_generic_cmpxchg(pcp, oval, nval)
#endif
#ifndef this_cpu_cmpxchg_8
#define this_cpu_cmpxchg_8(pcp, oval, nval) \
this_cpu_generic_cmpxchg(pcp, oval, nval)
#endif
#ifndef this_cpu_cmpxchg_double_1
#define this_cpu_cmpxchg_double_1(pcp1, pcp2, oval1, oval2, nval1, nval2) \
this_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
#endif
#ifndef this_cpu_cmpxchg_double_2
#define this_cpu_cmpxchg_double_2(pcp1, pcp2, oval1, oval2, nval1, nval2) \
this_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
#endif
#ifndef this_cpu_cmpxchg_double_4
#define this_cpu_cmpxchg_double_4(pcp1, pcp2, oval1, oval2, nval1, nval2) \
this_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
#endif
#ifndef this_cpu_cmpxchg_double_8
#define this_cpu_cmpxchg_double_8(pcp1, pcp2, oval1, oval2, nval1, nval2) \
this_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
#endif
#endif /* _ASM_GENERIC_PERCPU_H_ */

3
include/asm-generic/vmlinux.lds.h
View File

@@ -268,6 +268,9 @@
VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \
*(.pci_fixup_suspend) \
VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_suspend_late) = .; \
*(.pci_fixup_suspend_late) \
VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \
} \
\
/* Built-in firmware blobs */ \

18
include/clocksource/pxa.h Normal file
View File

@@ -0,0 +1,18 @@
/*
* PXA clocksource, clockevents, and OST interrupt handlers.
*
* Copyright (C) 2014 Robert Jarzmik
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*/
#ifndef _CLOCKSOURCE_PXA_H
#define _CLOCKSOURCE_PXA_H
extern void pxa_timer_nodt_init(int irq, void __iomem *base,
unsigned long clock_tick_rate);
#endif

4
include/crypto/aead.h
View File

@@ -75,9 +75,9 @@ static inline void aead_givcrypt_free(struct aead_givcrypt_request *req)
static inline void aead_givcrypt_set_callback(
struct aead_givcrypt_request *req, u32 flags,
crypto_completion_t complete, void *data)
crypto_completion_t compl, void *data)
{
aead_request_set_callback(&req->areq, flags, complete, data);
aead_request_set_callback(&req->areq, flags, compl, data);
}
static inline void aead_givcrypt_set_crypt(struct aead_givcrypt_request *req,

6
include/crypto/algapi.h
View File

@@ -410,4 +410,10 @@ static inline int crypto_memneq(const void *a, const void *b, size_t size)
return __crypto_memneq(a, b, size) != 0UL ? 1 : 0;
}
static inline void crypto_yield(u32 flags)
{
if (flags & CRYPTO_TFM_REQ_MAY_SLEEP)
cond_resched();
}
#endif /* _CRYPTO_ALGAPI_H */

3
include/crypto/des.h
View File

@@ -16,4 +16,7 @@
extern unsigned long des_ekey(u32 *pe, const u8 *k);
extern int __des3_ede_setkey(u32 *expkey, u32 *flags, const u8 *key,
unsigned int keylen);
#endif /* __CRYPTO_DES_H */

303
include/crypto/drbg.h Normal file
View File

@@ -0,0 +1,303 @@
/*
* DRBG based on NIST SP800-90A
*
* Copyright Stephan Mueller <smueller@chronox.de>, 2014
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, and the entire permission notice in its entirety,
* including the disclaimer of warranties.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote
* products derived from this software without specific prior
* written permission.
*
* ALTERNATIVELY, this product may be distributed under the terms of
* the GNU General Public License, in which case the provisions of the GPL are
* required INSTEAD OF the above restrictions. (This clause is
* necessary due to a potential bad interaction between the GPL and
* the restrictions contained in a BSD-style copyright.)
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ALL OF
* WHICH ARE HEREBY DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF NOT ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*/
#ifndef _DRBG_H
#define _DRBG_H
#include <linux/random.h>
#include <linux/scatterlist.h>
#include <crypto/hash.h>
#include <linux/module.h>
#include <linux/crypto.h>
#include <linux/slab.h>
#include <crypto/internal/rng.h>
#include <crypto/rng.h>
#include <linux/fips.h>
#include <linux/spinlock.h>
#include <linux/list.h>
/*
* Concatenation Helper and string operation helper
*
* SP800-90A requires the concatenation of different data. To avoid copying
* buffers around or allocate additional memory, the following data structure
* is used to point to the original memory with its size. In addition, it
* is used to build a linked list. The linked list defines the concatenation
* of individual buffers. The order of memory block referenced in that
* linked list determines the order of concatenation.
*/
struct drbg_string {
const unsigned char *buf;
size_t len;
struct list_head list;
};
static inline void drbg_string_fill(struct drbg_string *string,
const unsigned char *buf, size_t len)
{
string->buf = buf;
string->len = len;
INIT_LIST_HEAD(&string->list);
}
struct drbg_state;
typedef uint32_t drbg_flag_t;
struct drbg_core {
drbg_flag_t flags; /* flags for the cipher */
__u8 statelen; /* maximum state length */
/*
* maximum length of personalization string or additional input
* string -- exponent for base 2
*/
__u8 max_addtllen;
/* maximum bits per RNG request -- exponent for base 2*/
__u8 max_bits;
/* maximum number of requests -- exponent for base 2 */
__u8 max_req;
__u8 blocklen_bytes; /* block size of output in bytes */
char cra_name[CRYPTO_MAX_ALG_NAME]; /* mapping to kernel crypto API */
/* kernel crypto API backend cipher name */
char backend_cra_name[CRYPTO_MAX_ALG_NAME];
};
struct drbg_state_ops {
int (*update)(struct drbg_state *drbg, struct list_head *seed,
int reseed);
int (*generate)(struct drbg_state *drbg,
unsigned char *buf, unsigned int buflen,
struct list_head *addtl);
int (*crypto_init)(struct drbg_state *drbg);
int (*crypto_fini)(struct drbg_state *drbg);
};
struct drbg_test_data {
struct drbg_string *testentropy; /* TEST PARAMETER: test entropy */
};
struct drbg_state {
spinlock_t drbg_lock; /* lock around DRBG */
unsigned char *V; /* internal state 10.1.1.1 1a) */
/* hash: static value 10.1.1.1 1b) hmac / ctr: key */
unsigned char *C;
/* Number of RNG requests since last reseed -- 10.1.1.1 1c) */
size_t reseed_ctr;
/* some memory the DRBG can use for its operation */
unsigned char *scratchpad;
void *priv_data; /* Cipher handle */
bool seeded; /* DRBG fully seeded? */
bool pr; /* Prediction resistance enabled? */
#ifdef CONFIG_CRYPTO_FIPS
bool fips_primed; /* Continuous test primed? */
unsigned char *prev; /* FIPS 140-2 continuous test value */
#endif
const struct drbg_state_ops *d_ops;
const struct drbg_core *core;
struct drbg_test_data *test_data;
};
static inline __u8 drbg_statelen(struct drbg_state *drbg)
{
if (drbg && drbg->core)
return drbg->core->statelen;
return 0;
}
static inline __u8 drbg_blocklen(struct drbg_state *drbg)
{
if (drbg && drbg->core)
return drbg->core->blocklen_bytes;
return 0;
}
static inline __u8 drbg_keylen(struct drbg_state *drbg)
{
if (drbg && drbg->core)
return (drbg->core->statelen - drbg->core->blocklen_bytes);
return 0;
}
static inline size_t drbg_max_request_bytes(struct drbg_state *drbg)
{
/* max_bits is in bits, but buflen is in bytes */
return (1 << (drbg->core->max_bits - 3));
}
static inline size_t drbg_max_addtl(struct drbg_state *drbg)
{
#if (__BITS_PER_LONG == 32)
/*
* SP800-90A allows smaller maximum numbers to be returned -- we
* return SIZE_MAX - 1 to allow the verification of the enforcement
* of this value in drbg_healthcheck_sanity.
*/
return (SIZE_MAX - 1);
#else
return (1UL<<(drbg->core->max_addtllen));
#endif
}
static inline size_t drbg_max_requests(struct drbg_state *drbg)
{
#if (__BITS_PER_LONG == 32)
return SIZE_MAX;
#else
return (1UL<<(drbg->core->max_req));
#endif
}
/*
* kernel crypto API input data structure for DRBG generate in case dlen
* is set to 0
*/
struct drbg_gen {
unsigned char *outbuf; /* output buffer for random numbers */
unsigned int outlen; /* size of output buffer */
struct drbg_string *addtl; /* additional information string */
struct drbg_test_data *test_data; /* test data */
};
/*
* This is a wrapper to the kernel crypto API function of
* crypto_rng_get_bytes() to allow the caller to provide additional data.
*
* @drng DRBG handle -- see crypto_rng_get_bytes
* @outbuf output buffer -- see crypto_rng_get_bytes
* @outlen length of output buffer -- see crypto_rng_get_bytes
* @addtl_input additional information string input buffer
* @addtllen length of additional information string buffer
*
* return
* see crypto_rng_get_bytes
*/
static inline int crypto_drbg_get_bytes_addtl(struct crypto_rng *drng,
unsigned char *outbuf, unsigned int outlen,
struct drbg_string *addtl)
{
int ret;
struct drbg_gen genbuf;
genbuf.outbuf = outbuf;
genbuf.outlen = outlen;
genbuf.addtl = addtl;
genbuf.test_data = NULL;
ret = crypto_rng_get_bytes(drng, (u8 *)&genbuf, 0);
return ret;
}
/*
* TEST code
*
* This is a wrapper to the kernel crypto API function of
* crypto_rng_get_bytes() to allow the caller to provide additional data and
* allow furnishing of test_data
*
* @drng DRBG handle -- see crypto_rng_get_bytes
* @outbuf output buffer -- see crypto_rng_get_bytes
* @outlen length of output buffer -- see crypto_rng_get_bytes
* @addtl_input additional information string input buffer
* @addtllen length of additional information string buffer
* @test_data filled test data
*
* return
* see crypto_rng_get_bytes
*/
static inline int crypto_drbg_get_bytes_addtl_test(struct crypto_rng *drng,
unsigned char *outbuf, unsigned int outlen,
struct drbg_string *addtl,
struct drbg_test_data *test_data)
{
int ret;
struct drbg_gen genbuf;
genbuf.outbuf = outbuf;
genbuf.outlen = outlen;
genbuf.addtl = addtl;
genbuf.test_data = test_data;
ret = crypto_rng_get_bytes(drng, (u8 *)&genbuf, 0);
return ret;
}
/*
* TEST code
*
* This is a wrapper to the kernel crypto API function of
* crypto_rng_reset() to allow the caller to provide test_data
*
* @drng DRBG handle -- see crypto_rng_reset
* @pers personalization string input buffer
* @perslen length of additional information string buffer
* @test_data filled test data
*
* return
* see crypto_rng_reset
*/
static inline int crypto_drbg_reset_test(struct crypto_rng *drng,
struct drbg_string *pers,
struct drbg_test_data *test_data)
{
int ret;
struct drbg_gen genbuf;
genbuf.outbuf = NULL;
genbuf.outlen = 0;
genbuf.addtl = pers;
genbuf.test_data = test_data;
ret = crypto_rng_reset(drng, (u8 *)&genbuf, 0);
return ret;
}
/* DRBG type flags */
#define DRBG_CTR ((drbg_flag_t)1<<0)
#define DRBG_HMAC ((drbg_flag_t)1<<1)
#define DRBG_HASH ((drbg_flag_t)1<<2)
#define DRBG_TYPE_MASK (DRBG_CTR | DRBG_HMAC | DRBG_HASH)
/* DRBG strength flags */
#define DRBG_STRENGTH128 ((drbg_flag_t)1<<3)
#define DRBG_STRENGTH192 ((drbg_flag_t)1<<4)
#define DRBG_STRENGTH256 ((drbg_flag_t)1<<5)
#define DRBG_STRENGTH_MASK (DRBG_STRENGTH128 | DRBG_STRENGTH192 | \
DRBG_STRENGTH256)
enum drbg_prefixes {
DRBG_PREFIX0 = 0x00,
DRBG_PREFIX1,
DRBG_PREFIX2,
DRBG_PREFIX3
};
#endif /* _DRBG_H */

4
include/crypto/hash.h
View File

@@ -238,10 +238,10 @@ static inline struct ahash_request *ahash_request_cast(
static inline void ahash_request_set_callback(struct ahash_request *req,
u32 flags,
crypto_completion_t complete,
crypto_completion_t compl,
void *data)
{
req->base.complete = complete;
req->base.complete = compl;
req->base.data = data;
req->base.flags = flags;
}

3
include/crypto/internal/skcipher.h
View File

@@ -81,8 +81,7 @@ static inline int skcipher_enqueue_givcrypt(
static inline struct skcipher_givcrypt_request *skcipher_dequeue_givcrypt(
struct crypto_queue *queue)
{
return __crypto_dequeue_request(
queue, offsetof(struct skcipher_givcrypt_request, creq.base));
return skcipher_givcrypt_cast(crypto_dequeue_request(queue));
}
static inline void *skcipher_givcrypt_reqctx(

6
include/crypto/scatterwalk.h
View File

@@ -25,12 +25,6 @@
#include <linux/scatterlist.h>
#include <linux/sched.h>
static inline void crypto_yield(u32 flags)
{
if (flags & CRYPTO_TFM_REQ_MAY_SLEEP)
cond_resched();
}
static inline void scatterwalk_sg_chain(struct scatterlist *sg1, int num,
struct scatterlist *sg2)
{

4
include/crypto/skcipher.h
View File

@@ -86,9 +86,9 @@ static inline void skcipher_givcrypt_free(struct skcipher_givcrypt_request *req)
static inline void skcipher_givcrypt_set_callback(
struct skcipher_givcrypt_request *req, u32 flags,
crypto_completion_t complete, void *data)
crypto_completion_t compl, void *data)
{
ablkcipher_request_set_callback(&req->creq, flags, complete, data);
ablkcipher_request_set_callback(&req->creq, flags, compl, data);
}
static inline void skcipher_givcrypt_set_crypt(

92
include/drm/drmP.h
View File

@@ -83,6 +83,7 @@ struct drm_device;
struct device_node;
struct videomode;
struct reservation_object;
#include <drm/drm_os_linux.h>
#include <drm/drm_hashtab.h>
@@ -151,8 +152,6 @@ int drm_err(const char *func, const char *format, ...);
also include looping detection. */
#define DRM_MAGIC_HASH_ORDER 4 /**< Size of key hash table. Must be power of 2. */
#define DRM_KERNEL_CONTEXT 0 /**< Change drm_resctx if changed */
#define DRM_RESERVED_CONTEXTS 1 /**< Change drm_resctx if changed */
#define DRM_MAP_HASH_OFFSET 0x10000000
@@ -346,18 +345,6 @@ struct drm_waitlist {
spinlock_t write_lock;
};
struct drm_freelist {
int initialized; /**< Freelist in use */
atomic_t count; /**< Number of free buffers */
struct drm_buf *next; /**< End pointer */
wait_queue_head_t waiting; /**< Processes waiting on free bufs */
int low_mark; /**< Low water mark */
int high_mark; /**< High water mark */
atomic_t wfh; /**< If waiting for high mark */
spinlock_t lock;
};
typedef struct drm_dma_handle {
dma_addr_t busaddr;
void *vaddr;
@@ -375,7 +362,8 @@ struct drm_buf_entry {
int page_order;
struct drm_dma_handle **seglist;
struct drm_freelist freelist;
int low_mark; /**< Low water mark */
int high_mark; /**< High water mark */
};
/* Event queued up for userspace to read */
@@ -396,7 +384,6 @@ struct drm_prime_file_private {
/** File private data */
struct drm_file {
unsigned always_authenticated :1;
unsigned authenticated :1;
/* Whether we're master for a minor. Protected by master_mutex */
unsigned is_master :1;
@@ -441,23 +428,6 @@ struct drm_file {
struct drm_prime_file_private prime;
};
/** Wait queue */
struct drm_queue {
atomic_t use_count; /**< Outstanding uses (+1) */
atomic_t finalization; /**< Finalization in progress */
atomic_t block_count; /**< Count of processes waiting */
atomic_t block_read; /**< Queue blocked for reads */
wait_queue_head_t read_queue; /**< Processes waiting on block_read */
atomic_t block_write; /**< Queue blocked for writes */
wait_queue_head_t write_queue; /**< Processes waiting on block_write */
atomic_t total_queued; /**< Total queued statistic */
atomic_t total_flushed; /**< Total flushes statistic */
atomic_t total_locks; /**< Total locks statistics */
enum drm_ctx_flags flags; /**< Context preserving and 2D-only */
struct drm_waitlist waitlist; /**< Pending buffers */
wait_queue_head_t flush_queue; /**< Processes waiting until flush */
};
/**
* Lock data.
*/
@@ -566,15 +536,6 @@ struct drm_map_list {
struct drm_master *master;
};
/**
* Context handle list
*/
struct drm_ctx_list {
struct list_head head; /**< list head */
drm_context_t handle; /**< context handle */
struct drm_file *tag; /**< associated fd private data */
};
/* location of GART table */
#define DRM_ATI_GART_MAIN 1
#define DRM_ATI_GART_FB 2
@@ -923,6 +884,8 @@ struct drm_driver {
/* low-level interface used by drm_gem_prime_{import,export} */
int (*gem_prime_pin)(struct drm_gem_object *obj);
void (*gem_prime_unpin)(struct drm_gem_object *obj);
struct reservation_object * (*gem_prime_res_obj)(
struct drm_gem_object *obj);
struct sg_table *(*gem_prime_get_sg_table)(struct drm_gem_object *obj);
struct drm_gem_object *(*gem_prime_import_sg_table)(
struct drm_device *dev, size_t size,
@@ -1215,7 +1178,6 @@ extern bool drm_ioctl_flags(unsigned int nr, unsigned int *flags);
/* Device support (drm_fops.h) */
extern struct mutex drm_global_mutex;
extern int drm_open(struct inode *inode, struct file *filp);
extern int drm_stub_open(struct inode *inode, struct file *filp);
extern ssize_t drm_read(struct file *filp, char __user *buffer,
size_t count, loff_t *offset);
extern int drm_release(struct inode *inode, struct file *filp);
@@ -1253,29 +1215,6 @@ extern int drm_setversion(struct drm_device *dev, void *data,
extern int drm_noop(struct drm_device *dev, void *data,
struct drm_file *file_priv);
/* Context IOCTL support (drm_context.h) */
extern int drm_resctx(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int drm_addctx(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int drm_getctx(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int drm_switchctx(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int drm_newctx(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int drm_rmctx(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int drm_ctxbitmap_init(struct drm_device *dev);
extern void drm_ctxbitmap_cleanup(struct drm_device *dev);
extern void drm_ctxbitmap_free(struct drm_device *dev, int ctx_handle);
extern int drm_setsareactx(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int drm_getsareactx(struct drm_device *dev, void *data,
struct drm_file *file_priv);
/* Authentication IOCTL support (drm_auth.h) */
extern int drm_getmagic(struct drm_device *dev, void *data,
struct drm_file *file_priv);
@@ -1395,17 +1334,12 @@ extern void drm_master_put(struct drm_master **master);
extern void drm_put_dev(struct drm_device *dev);
extern void drm_unplug_dev(struct drm_device *dev);
extern unsigned int drm_debug;
extern unsigned int drm_rnodes;
extern unsigned int drm_universal_planes;
extern unsigned int drm_vblank_offdelay;
extern unsigned int drm_timestamp_precision;
extern unsigned int drm_timestamp_monotonic;
extern struct class *drm_class;
extern struct dentry *drm_debugfs_root;
extern struct idr drm_minors_idr;
extern struct drm_local_map *drm_getsarea(struct drm_device *dev);
@@ -1419,6 +1353,8 @@ extern int drm_debugfs_create_files(const struct drm_info_list *files,
extern int drm_debugfs_remove_files(const struct drm_info_list *files,
int count, struct drm_minor *minor);
extern int drm_debugfs_cleanup(struct drm_minor *minor);
extern int drm_debugfs_connector_add(struct drm_connector *connector);
extern void drm_debugfs_connector_remove(struct drm_connector *connector);
#else
static inline int drm_debugfs_init(struct drm_minor *minor, int minor_id,
struct dentry *root)
@@ -1443,6 +1379,15 @@ static inline int drm_debugfs_cleanup(struct drm_minor *minor)
{
return 0;
}
static inline int drm_debugfs_connector_add(struct drm_connector *connector)
{
return 0;
}
static inline void drm_debugfs_connector_remove(struct drm_connector *connector)
{
}
#endif
/* Info file support */
@@ -1512,9 +1457,8 @@ extern int drm_pci_set_unique(struct drm_device *dev,
struct drm_sysfs_class;
extern struct class *drm_sysfs_create(struct module *owner, char *name);
extern void drm_sysfs_destroy(void);
extern int drm_sysfs_device_add(struct drm_minor *minor);
extern struct device *drm_sysfs_minor_alloc(struct drm_minor *minor);
extern void drm_sysfs_hotplug_event(struct drm_device *dev);
extern void drm_sysfs_device_remove(struct drm_minor *minor);
extern int drm_sysfs_connector_add(struct drm_connector *connector);
extern void drm_sysfs_connector_remove(struct drm_connector *connector);
@@ -1574,7 +1518,7 @@ void drm_gem_free_mmap_offset(struct drm_gem_object *obj);
int drm_gem_create_mmap_offset(struct drm_gem_object *obj);
int drm_gem_create_mmap_offset_size(struct drm_gem_object *obj, size_t size);
struct page **drm_gem_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
struct page **drm_gem_get_pages(struct drm_gem_object *obj);
void drm_gem_put_pages(struct drm_gem_object *obj, struct page **pages,
bool dirty, bool accessed);

36
include/drm/drm_crtc.h
View File

@@ -41,6 +41,7 @@ struct drm_framebuffer;
struct drm_object_properties;
struct drm_file;
struct drm_clip_rect;
struct device_node;
#define DRM_MODE_OBJECT_CRTC 0xcccccccc
#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
@@ -75,6 +76,14 @@ static inline uint64_t I642U64(int64_t val)
return (uint64_t)*((uint64_t *)&val);
}
/* rotation property bits */
#define DRM_ROTATE_0 0
#define DRM_ROTATE_90 1
#define DRM_ROTATE_180 2
#define DRM_ROTATE_270 3
#define DRM_REFLECT_X 4
#define DRM_REFLECT_Y 5
enum drm_connector_force {
DRM_FORCE_UNSPECIFIED,
DRM_FORCE_OFF,
@@ -314,6 +323,7 @@ struct drm_crtc_funcs {
*/
struct drm_crtc {
struct drm_device *dev;
struct device_node *port;
struct list_head head;
/**
@@ -331,6 +341,10 @@ struct drm_crtc {
struct drm_plane *primary;
struct drm_plane *cursor;
/* position of cursor plane on crtc */
int cursor_x;
int cursor_y;
/* Temporary tracking of the old fb while a modeset is ongoing. Used
* by drm_mode_set_config_internal to implement correct refcounting. */
struct drm_framebuffer *old_fb;
@@ -524,6 +538,8 @@ struct drm_connector {
struct drm_property_blob *edid_blob_ptr;
struct drm_object_properties properties;
struct drm_property_blob *path_blob_ptr;
uint8_t polled; /* DRM_CONNECTOR_POLL_* */
/* requested DPMS state */
@@ -533,6 +549,7 @@ struct drm_connector {
/* forced on connector */
enum drm_connector_force force;
bool override_edid;
uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER];
struct drm_encoder *encoder; /* currently active encoder */
@@ -545,6 +562,8 @@ struct drm_connector {
int audio_latency[2];
int null_edid_counter; /* needed to workaround some HW bugs where we get all 0s */
unsigned bad_edid_counter;
struct dentry *debugfs_entry;
};
/**
@@ -800,6 +819,7 @@ struct drm_mode_config {
struct list_head property_blob_list;
struct drm_property *edid_property;
struct drm_property *dpms_property;
struct drm_property *path_property;
struct drm_property *plane_type_property;
/* DVI-I properties */
@@ -823,6 +843,7 @@ struct drm_mode_config {
/* Optional properties */
struct drm_property *scaling_mode_property;
struct drm_property *aspect_ratio_property;
struct drm_property *dirty_info_property;
/* dumb ioctl parameters */
@@ -852,7 +873,7 @@ struct drm_prop_enum_list {
extern int drm_crtc_init_with_planes(struct drm_device *dev,
struct drm_crtc *crtc,
struct drm_plane *primary,
void *cursor,
struct drm_plane *cursor,
const struct drm_crtc_funcs *funcs);
extern int drm_crtc_init(struct drm_device *dev,
struct drm_crtc *crtc,
@@ -878,6 +899,8 @@ extern int drm_connector_init(struct drm_device *dev,
struct drm_connector *connector,
const struct drm_connector_funcs *funcs,
int connector_type);
int drm_connector_register(struct drm_connector *connector);
void drm_connector_unregister(struct drm_connector *connector);
extern void drm_connector_cleanup(struct drm_connector *connector);
/* helper to unplug all connectors from sysfs for device */
@@ -937,6 +960,7 @@ extern const char *drm_get_tv_select_name(int val);
extern void drm_fb_release(struct drm_file *file_priv);
extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group);
extern void drm_mode_group_destroy(struct drm_mode_group *group);
extern void drm_reinit_primary_mode_group(struct drm_device *dev);
extern bool drm_probe_ddc(struct i2c_adapter *adapter);
extern struct edid *drm_get_edid(struct drm_connector *connector,
struct i2c_adapter *adapter);
@@ -946,6 +970,8 @@ extern void drm_mode_config_init(struct drm_device *dev);
extern void drm_mode_config_reset(struct drm_device *dev);
extern void drm_mode_config_cleanup(struct drm_device *dev);
extern int drm_mode_connector_set_path_property(struct drm_connector *connector,
char *path);
extern int drm_mode_connector_update_edid_property(struct drm_connector *connector,
struct edid *edid);
@@ -994,7 +1020,8 @@ extern struct drm_property *drm_property_create_enum(struct drm_device *dev, int
struct drm_property *drm_property_create_bitmask(struct drm_device *dev,
int flags, const char *name,
const struct drm_prop_enum_list *props,
int num_values);
int num_props,
uint64_t supported_bits);
struct drm_property *drm_property_create_range(struct drm_device *dev, int flags,
const char *name,
uint64_t min, uint64_t max);
@@ -1010,6 +1037,7 @@ extern int drm_mode_create_dvi_i_properties(struct drm_device *dev);
extern int drm_mode_create_tv_properties(struct drm_device *dev, int num_formats,
char *formats[]);
extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
extern int drm_mode_connector_attach_encoder(struct drm_connector *connector,
@@ -1100,6 +1128,10 @@ extern int drm_format_plane_cpp(uint32_t format, int plane);
extern int drm_format_horz_chroma_subsampling(uint32_t format);
extern int drm_format_vert_chroma_subsampling(uint32_t format);
extern const char *drm_get_format_name(uint32_t format);
extern struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
unsigned int supported_rotations);
extern unsigned int drm_rotation_simplify(unsigned int rotation,
unsigned int supported_rotations);
/* Helpers */

509
include/drm/drm_dp_mst_helper.h Normal file
View File

@@ -0,0 +1,509 @@
/*
* Copyright © 2014 Red Hat.
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that copyright
* notice and this permission notice appear in supporting documentation, and
* that the name of the copyright holders not be used in advertising or
* publicity pertaining to distribution of the software without specific,
* written prior permission. The copyright holders make no representations
* about the suitability of this software for any purpose. It is provided "as
* is" without express or implied warranty.
*
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
* OF THIS SOFTWARE.
*/
#ifndef _DRM_DP_MST_HELPER_H_
#define _DRM_DP_MST_HELPER_H_
#include <linux/types.h>
#include <drm/drm_dp_helper.h>
struct drm_dp_mst_branch;
/**
* struct drm_dp_vcpi - Virtual Channel Payload Identifer
* @vcpi: Virtual channel ID.
* @pbn: Payload Bandwidth Number for this channel
* @aligned_pbn: PBN aligned with slot size
* @num_slots: number of slots for this PBN
*/
struct drm_dp_vcpi {
int vcpi;
int pbn;
int aligned_pbn;
int num_slots;
};
/**
* struct drm_dp_mst_port - MST port
* @kref: reference count for this port.
* @guid_valid: for DP 1.2 devices if we have validated the GUID.
* @guid: guid for DP 1.2 device on this port.
* @port_num: port number
* @input: if this port is an input port.
* @mcs: message capability status - DP 1.2 spec.
* @ddps: DisplayPort Device Plug Status - DP 1.2
* @pdt: Peer Device Type
* @ldps: Legacy Device Plug Status
* @dpcd_rev: DPCD revision of device on this port
* @num_sdp_streams: Number of simultaneous streams
* @num_sdp_stream_sinks: Number of stream sinks
* @available_pbn: Available bandwidth for this port.
* @next: link to next port on this branch device
* @mstb: branch device attach below this port
* @aux: i2c aux transport to talk to device connected to this port.
* @parent: branch device parent of this port
* @vcpi: Virtual Channel Payload info for this port.
* @connector: DRM connector this port is connected to.
* @mgr: topology manager this port lives under.
*
* This structure represents an MST port endpoint on a device somewhere
* in the MST topology.
*/
struct drm_dp_mst_port {
struct kref kref;
/* if dpcd 1.2 device is on this port - its GUID info */
bool guid_valid;
u8 guid[16];
u8 port_num;
bool input;
bool mcs;
bool ddps;
u8 pdt;
bool ldps;
u8 dpcd_rev;
u8 num_sdp_streams;
u8 num_sdp_stream_sinks;
uint16_t available_pbn;
struct list_head next;
struct drm_dp_mst_branch *mstb; /* pointer to an mstb if this port has one */
struct drm_dp_aux aux; /* i2c bus for this port? */
struct drm_dp_mst_branch *parent;
struct drm_dp_vcpi vcpi;
struct drm_connector *connector;
struct drm_dp_mst_topology_mgr *mgr;
};
/**
* struct drm_dp_mst_branch - MST branch device.
* @kref: reference count for this port.
* @rad: Relative Address to talk to this branch device.
* @lct: Link count total to talk to this branch device.
* @num_ports: number of ports on the branch.
* @msg_slots: one bit per transmitted msg slot.
* @ports: linked list of ports on this branch.
* @port_parent: pointer to the port parent, NULL if toplevel.
* @mgr: topology manager for this branch device.
* @tx_slots: transmission slots for this device.
* @last_seqno: last sequence number used to talk to this.
* @link_address_sent: if a link address message has been sent to this device yet.
*
* This structure represents an MST branch device, there is one
* primary branch device at the root, along with any others connected
* to downstream ports
*/
struct drm_dp_mst_branch {
struct kref kref;
u8 rad[8];
u8 lct;
int num_ports;
int msg_slots;
struct list_head ports;
/* list of tx ops queue for this port */
struct drm_dp_mst_port *port_parent;
struct drm_dp_mst_topology_mgr *mgr;
/* slots are protected by mstb->mgr->qlock */
struct drm_dp_sideband_msg_tx *tx_slots[2];
int last_seqno;
bool link_address_sent;
};
/* sideband msg header - not bit struct */
struct drm_dp_sideband_msg_hdr {
u8 lct;
u8 lcr;
u8 rad[8];
bool broadcast;
bool path_msg;
u8 msg_len;
bool somt;
bool eomt;
bool seqno;
};
struct drm_dp_nak_reply {
u8 guid[16];
u8 reason;
u8 nak_data;
};
struct drm_dp_link_address_ack_reply {
u8 guid[16];
u8 nports;
struct drm_dp_link_addr_reply_port {
bool input_port;
u8 peer_device_type;
u8 port_number;
bool mcs;
bool ddps;
bool legacy_device_plug_status;
u8 dpcd_revision;
u8 peer_guid[16];
u8 num_sdp_streams;
u8 num_sdp_stream_sinks;
} ports[16];
};
struct drm_dp_remote_dpcd_read_ack_reply {
u8 port_number;
u8 num_bytes;
u8 bytes[255];
};
struct drm_dp_remote_dpcd_write_ack_reply {
u8 port_number;
};
struct drm_dp_remote_dpcd_write_nak_reply {
u8 port_number;
u8 reason;
u8 bytes_written_before_failure;
};
struct drm_dp_remote_i2c_read_ack_reply {
u8 port_number;
u8 num_bytes;
u8 bytes[255];
};
struct drm_dp_remote_i2c_read_nak_reply {
u8 port_number;
u8 nak_reason;
u8 i2c_nak_transaction;
};
struct drm_dp_remote_i2c_write_ack_reply {
u8 port_number;
};
struct drm_dp_sideband_msg_rx {
u8 chunk[48];
u8 msg[256];
u8 curchunk_len;
u8 curchunk_idx; /* chunk we are parsing now */
u8 curchunk_hdrlen;
u8 curlen; /* total length of the msg */
bool have_somt;
bool have_eomt;
struct drm_dp_sideband_msg_hdr initial_hdr;
};
struct drm_dp_allocate_payload {
u8 port_number;
u8 number_sdp_streams;
u8 vcpi;
u16 pbn;
u8 sdp_stream_sink[8];
};
struct drm_dp_allocate_payload_ack_reply {
u8 port_number;
u8 vcpi;
u16 allocated_pbn;
};
struct drm_dp_connection_status_notify {
u8 guid[16];
u8 port_number;
bool legacy_device_plug_status;
bool displayport_device_plug_status;
bool message_capability_status;
bool input_port;
u8 peer_device_type;
};
struct drm_dp_remote_dpcd_read {
u8 port_number;
u32 dpcd_address;
u8 num_bytes;
};
struct drm_dp_remote_dpcd_write {
u8 port_number;
u32 dpcd_address;
u8 num_bytes;
u8 *bytes;
};
struct drm_dp_remote_i2c_read {
u8 num_transactions;
u8 port_number;
struct {
u8 i2c_dev_id;
u8 num_bytes;
u8 *bytes;
u8 no_stop_bit;
u8 i2c_transaction_delay;
} transactions[4];
u8 read_i2c_device_id;
u8 num_bytes_read;
};
struct drm_dp_remote_i2c_write {
u8 port_number;
u8 write_i2c_device_id;
u8 num_bytes;
u8 *bytes;
};
/* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */
struct drm_dp_port_number_req {
u8 port_number;
};
struct drm_dp_enum_path_resources_ack_reply {
u8 port_number;
u16 full_payload_bw_number;
u16 avail_payload_bw_number;
};
/* covers POWER_DOWN_PHY, POWER_UP_PHY */
struct drm_dp_port_number_rep {
u8 port_number;
};
struct drm_dp_query_payload {
u8 port_number;
u8 vcpi;
};
struct drm_dp_resource_status_notify {
u8 port_number;
u8 guid[16];
u16 available_pbn;
};
struct drm_dp_query_payload_ack_reply {
u8 port_number;
u8 allocated_pbn;
};
struct drm_dp_sideband_msg_req_body {
u8 req_type;
union ack_req {
struct drm_dp_connection_status_notify conn_stat;
struct drm_dp_port_number_req port_num;
struct drm_dp_resource_status_notify resource_stat;
struct drm_dp_query_payload query_payload;
struct drm_dp_allocate_payload allocate_payload;
struct drm_dp_remote_dpcd_read dpcd_read;
struct drm_dp_remote_dpcd_write dpcd_write;
struct drm_dp_remote_i2c_read i2c_read;
struct drm_dp_remote_i2c_write i2c_write;
} u;
};
struct drm_dp_sideband_msg_reply_body {
u8 reply_type;
u8 req_type;
union ack_replies {
struct drm_dp_nak_reply nak;
struct drm_dp_link_address_ack_reply link_addr;
struct drm_dp_port_number_rep port_number;
struct drm_dp_enum_path_resources_ack_reply path_resources;
struct drm_dp_allocate_payload_ack_reply allocate_payload;
struct drm_dp_query_payload_ack_reply query_payload;
struct drm_dp_remote_dpcd_read_ack_reply remote_dpcd_read_ack;
struct drm_dp_remote_dpcd_write_ack_reply remote_dpcd_write_ack;
struct drm_dp_remote_dpcd_write_nak_reply remote_dpcd_write_nack;
struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack;
struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack;
struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;
} u;
};
/* msg is queued to be put into a slot */
#define DRM_DP_SIDEBAND_TX_QUEUED 0
/* msg has started transmitting on a slot - still on msgq */
#define DRM_DP_SIDEBAND_TX_START_SEND 1
/* msg has finished transmitting on a slot - removed from msgq only in slot */
#define DRM_DP_SIDEBAND_TX_SENT 2
/* msg has received a response - removed from slot */
#define DRM_DP_SIDEBAND_TX_RX 3
#define DRM_DP_SIDEBAND_TX_TIMEOUT 4
struct drm_dp_sideband_msg_tx {
u8 msg[256];
u8 chunk[48];
u8 cur_offset;
u8 cur_len;
struct drm_dp_mst_branch *dst;
struct list_head next;
int seqno;
int state;
bool path_msg;
struct drm_dp_sideband_msg_reply_body reply;
};
/* sideband msg handler */
struct drm_dp_mst_topology_mgr;
struct drm_dp_mst_topology_cbs {
/* create a connector for a port */
struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, char *path);
void (*destroy_connector)(struct drm_dp_mst_topology_mgr *mgr,
struct drm_connector *connector);
void (*hotplug)(struct drm_dp_mst_topology_mgr *mgr);
};
#define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8)
#define DP_PAYLOAD_LOCAL 1
#define DP_PAYLOAD_REMOTE 2
#define DP_PAYLOAD_DELETE_LOCAL 3
struct drm_dp_payload {
int payload_state;
int start_slot;
int num_slots;
};
/**
* struct drm_dp_mst_topology_mgr - DisplayPort MST manager
* @dev: device pointer for adding i2c devices etc.
* @cbs: callbacks for connector addition and destruction.
* @max_dpcd_transaction_bytes - maximum number of bytes to read/write in one go.
* @aux: aux channel for the DP connector.
* @max_payloads: maximum number of payloads the GPU can generate.
* @conn_base_id: DRM connector ID this mgr is connected to.
* @down_rep_recv: msg receiver state for down replies.
* @up_req_recv: msg receiver state for up requests.
* @lock: protects mst state, primary, guid, dpcd.
* @mst_state: if this manager is enabled for an MST capable port.
* @mst_primary: pointer to the primary branch device.
* @guid_valid: GUID valid for the primary branch device.
* @guid: GUID for primary port.
* @dpcd: cache of DPCD for primary port.
* @pbn_div: PBN to slots divisor.
*
* This struct represents the toplevel displayport MST topology manager.
* There should be one instance of this for every MST capable DP connector
* on the GPU.
*/
struct drm_dp_mst_topology_mgr {
struct device *dev;
struct drm_dp_mst_topology_cbs *cbs;
int max_dpcd_transaction_bytes;
struct drm_dp_aux *aux; /* auxch for this topology mgr to use */
int max_payloads;
int conn_base_id;
/* only ever accessed from the workqueue - which should be serialised */
struct drm_dp_sideband_msg_rx down_rep_recv;
struct drm_dp_sideband_msg_rx up_req_recv;
/* pointer to info about the initial MST device */
struct mutex lock; /* protects mst_state + primary + guid + dpcd */
bool mst_state;
struct drm_dp_mst_branch *mst_primary;
/* primary MST device GUID */
bool guid_valid;
u8 guid[16];
u8 dpcd[DP_RECEIVER_CAP_SIZE];
u8 sink_count;
int pbn_div;
int total_slots;
int avail_slots;
int total_pbn;
/* messages to be transmitted */
/* qlock protects the upq/downq and in_progress,
the mstb tx_slots and txmsg->state once they are queued */
struct mutex qlock;
struct list_head tx_msg_downq;
struct list_head tx_msg_upq;
bool tx_down_in_progress;
bool tx_up_in_progress;
/* payload info + lock for it */
struct mutex payload_lock;
struct drm_dp_vcpi **proposed_vcpis;
struct drm_dp_payload *payloads;
unsigned long payload_mask;
wait_queue_head_t tx_waitq;
struct work_struct work;
struct work_struct tx_work;
};
int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, int conn_base_id);
void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr);
int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state);
int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled);
enum drm_connector_status drm_dp_mst_detect_port(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
int drm_dp_calc_pbn_mode(int clock, int bpp);
bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int pbn, int *slots);
void drm_dp_mst_reset_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port);
int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr,
int pbn);
int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr);
int drm_dp_update_payload_part2(struct drm_dp_mst_topology_mgr *mgr);
int drm_dp_check_act_status(struct drm_dp_mst_topology_mgr *mgr);
void drm_dp_mst_dump_topology(struct seq_file *m,
struct drm_dp_mst_topology_mgr *mgr);
void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr);
int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr);
#endif

8
include/drm/drm_fb_helper.h
View File

@@ -86,8 +86,9 @@ struct drm_fb_helper {
int crtc_count;
struct drm_fb_helper_crtc *crtc_info;
int connector_count;
int connector_info_alloc_count;
struct drm_fb_helper_connector **connector_info;
struct drm_fb_helper_funcs *funcs;
const struct drm_fb_helper_funcs *funcs;
struct fb_info *fbdev;
u32 pseudo_palette[17];
struct list_head kernel_fb_list;
@@ -97,6 +98,8 @@ struct drm_fb_helper {
bool delayed_hotplug;
};
void drm_fb_helper_prepare(struct drm_device *dev, struct drm_fb_helper *helper,
const struct drm_fb_helper_funcs *funcs);
int drm_fb_helper_init(struct drm_device *dev,
struct drm_fb_helper *helper, int crtc_count,
int max_conn);
@@ -128,4 +131,7 @@ struct drm_display_mode *
drm_pick_cmdline_mode(struct drm_fb_helper_connector *fb_helper_conn,
int width, int height);
int drm_fb_helper_add_one_connector(struct drm_fb_helper *fb_helper, struct drm_connector *connector);
int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper,
struct drm_connector *connector);
#endif

21
include/drm/drm_mipi_dsi.h
View File

@@ -94,6 +94,8 @@ void mipi_dsi_host_unregister(struct mipi_dsi_host *host);
#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8)
/* disable EoT packets in HS mode */
#define MIPI_DSI_MODE_EOT_PACKET BIT(9)
/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)
enum mipi_dsi_pixel_format {
MIPI_DSI_FMT_RGB888,
@@ -121,14 +123,17 @@ struct mipi_dsi_device {
unsigned long mode_flags;
};
#define to_mipi_dsi_device(d) container_of(d, struct mipi_dsi_device, dev)
static inline struct mipi_dsi_device *to_mipi_dsi_device(struct device *dev)
{
return container_of(dev, struct mipi_dsi_device, dev);
}
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
int mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, unsigned int channel,
const void *data, size_t len);
ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, unsigned int channel,
u8 cmd, void *data, size_t len);
ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, const void *data,
size_t len);
ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,
size_t len);
/**
* struct mipi_dsi_driver - DSI driver
@@ -144,7 +149,11 @@ struct mipi_dsi_driver {
void (*shutdown)(struct mipi_dsi_device *dsi);
};
#define to_mipi_dsi_driver(d) container_of(d, struct mipi_dsi_driver, driver)
static inline struct mipi_dsi_driver *
to_mipi_dsi_driver(struct device_driver *driver)
{
return container_of(driver, struct mipi_dsi_driver, driver);
}
static inline void *mipi_dsi_get_drvdata(const struct mipi_dsi_device *dsi)
{

18
include/drm/drm_of.h Normal file
View File

@@ -0,0 +1,18 @@
#ifndef __DRM_OF_H__
#define __DRM_OF_H__
struct drm_device;
struct device_node;
#ifdef CONFIG_OF
extern uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
struct device_node *port);
#else
static inline uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
struct device_node *port)
{
return 0;
}
#endif
#endif /* __DRM_OF_H__ */

58
include/drm/drm_panel.h
View File

@@ -30,8 +30,42 @@ struct drm_connector;
struct drm_device;
struct drm_panel;
/**
* struct drm_panel_funcs - perform operations on a given panel
* @disable: disable panel (turn off back light, etc.)
* @unprepare: turn off panel
* @prepare: turn on panel and perform set up
* @enable: enable panel (turn on back light, etc.)
* @get_modes: add modes to the connector that the panel is attached to and
* return the number of modes added
*
* The .prepare() function is typically called before the display controller
* starts to transmit video data. Panel drivers can use this to turn the panel
* on and wait for it to become ready. If additional configuration is required
* (via a control bus such as I2C, SPI or DSI for example) this is a good time
* to do that.
*
* After the display controller has started transmitting video data, it's safe
* to call the .enable() function. This will typically enable the backlight to
* make the image on screen visible. Some panels require a certain amount of
* time or frames before the image is displayed. This function is responsible
* for taking this into account before enabling the backlight to avoid visual
* glitches.
*
* Before stopping video transmission from the display controller it can be
* necessary to turn off the panel to avoid visual glitches. This is done in
* the .disable() function. Analogously to .enable() this typically involves
* turning off the backlight and waiting for some time to make sure no image
* is visible on the panel. It is then safe for the display controller to
* cease transmission of video data.
*
* To save power when no video data is transmitted, a driver can power down
* the panel. This is the job of the .unprepare() function.
*/
struct drm_panel_funcs {
int (*disable)(struct drm_panel *panel);
int (*unprepare)(struct drm_panel *panel);
int (*prepare)(struct drm_panel *panel);
int (*enable)(struct drm_panel *panel);
int (*get_modes)(struct drm_panel *panel);
};
@@ -46,6 +80,14 @@ struct drm_panel {
struct list_head list;
};
static inline int drm_panel_unprepare(struct drm_panel *panel)
{
if (panel && panel->funcs && panel->funcs->unprepare)
return panel->funcs->unprepare(panel);
return panel ? -ENOSYS : -EINVAL;
}
static inline int drm_panel_disable(struct drm_panel *panel)
{
if (panel && panel->funcs && panel->funcs->disable)
@@ -54,6 +96,14 @@ static inline int drm_panel_disable(struct drm_panel *panel)
return panel ? -ENOSYS : -EINVAL;
}
static inline int drm_panel_prepare(struct drm_panel *panel)
{
if (panel && panel->funcs && panel->funcs->prepare)
return panel->funcs->prepare(panel);
return panel ? -ENOSYS : -EINVAL;
}
static inline int drm_panel_enable(struct drm_panel *panel)
{
if (panel && panel->funcs && panel->funcs->enable)
@@ -62,6 +112,14 @@ static inline int drm_panel_enable(struct drm_panel *panel)
return panel ? -ENOSYS : -EINVAL;
}
static inline int drm_panel_get_modes(struct drm_panel *panel)
{
if (panel && panel->funcs && panel->funcs->get_modes)
return panel->funcs->get_modes(panel);
return panel ? -ENOSYS : -EINVAL;
}
void drm_panel_init(struct drm_panel *panel);
int drm_panel_add(struct drm_panel *panel);

7
include/drm/drm_pciids.h
View File

@@ -17,6 +17,7 @@
{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
@@ -164,8 +165,11 @@
{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
@@ -175,6 +179,8 @@
{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
@@ -297,6 +303,7 @@
{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

6
include/drm/drm_rect.h
View File

@@ -163,5 +163,11 @@ int drm_rect_calc_vscale_relaxed(struct drm_rect *src,
struct drm_rect *dst,
int min_vscale, int max_vscale);
void drm_rect_debug_print(const struct drm_rect *r, bool fixed_point);
void drm_rect_rotate(struct drm_rect *r,
int width, int height,
unsigned int rotation);
void drm_rect_rotate_inv(struct drm_rect *r,
int width, int height,
unsigned int rotation);
#endif

16
include/drm/ttm/ttm_bo_driver.h
View File

@@ -133,6 +133,7 @@ struct ttm_tt {
* struct ttm_dma_tt
*
* @ttm: Base ttm_tt struct.
* @cpu_address: The CPU address of the pages
* @dma_address: The DMA (bus) addresses of the pages
* @pages_list: used by some page allocation backend
*
@@ -142,6 +143,7 @@ struct ttm_tt {
*/
struct ttm_dma_tt {
struct ttm_tt ttm;
void **cpu_address;
dma_addr_t *dma_address;
struct list_head pages_list;
};
@@ -182,6 +184,7 @@ struct ttm_mem_type_manager_func {
* @man: Pointer to a memory type manager.
* @bo: Pointer to the buffer object we're allocating space for.
* @placement: Placement details.
* @flags: Additional placement flags.
* @mem: Pointer to a struct ttm_mem_reg to be filled in.
*
* This function should allocate space in the memory type managed
@@ -206,6 +209,7 @@ struct ttm_mem_type_manager_func {
int (*get_node)(struct ttm_mem_type_manager *man,
struct ttm_buffer_object *bo,
struct ttm_placement *placement,
uint32_t flags,
struct ttm_mem_reg *mem);
/**
@@ -652,18 +656,6 @@ extern void ttm_tt_unbind(struct ttm_tt *ttm);
*/
extern int ttm_tt_swapin(struct ttm_tt *ttm);
/**
* ttm_tt_cache_flush:
*
* @pages: An array of pointers to struct page:s to flush.
* @num_pages: Number of pages to flush.
*
* Flush the data of the indicated pages from the cpu caches.
* This is used when changing caching attributes of the pages from
* cache-coherent.
*/
extern void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages);
/**
* ttm_tt_set_placement_caching:
*

27
include/dt-bindings/clock/clps711x-clock.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H
#define __DT_BINDINGS_CLOCK_CLPS711X_H
#define CLPS711X_CLK_DUMMY 0
#define CLPS711X_CLK_CPU 1
#define CLPS711X_CLK_BUS 2
#define CLPS711X_CLK_PLL 3
#define CLPS711X_CLK_TIMERREF 4
#define CLPS711X_CLK_TIMER1 5
#define CLPS711X_CLK_TIMER2 6
#define CLPS711X_CLK_PWM 7
#define CLPS711X_CLK_SPIREF 8
#define CLPS711X_CLK_SPI 9
#define CLPS711X_CLK_UART 10
#define CLPS711X_CLK_TICK 11
#define CLPS711X_CLK_MAX 12
#endif

25
include/dt-bindings/clock/exynos4.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda@samsung.com>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -34,6 +34,11 @@
#define CLK_MOUT_CORE 19
#define CLK_MOUT_APLL 20
#define CLK_SCLK_HDMIPHY 22
#define CLK_OUT_DMC 23
#define CLK_OUT_TOP 24
#define CLK_OUT_LEFTBUS 25
#define CLK_OUT_RIGHTBUS 26
#define CLK_OUT_CPU 27
/* gate for special clocks (sclk) */
#define CLK_SCLK_FIMC0 128
@@ -230,6 +235,24 @@
#define CLK_MOUT_G3D 394
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
/* gate clocks - ppmu */
#define CLK_PPMULEFT 400
#define CLK_PPMURIGHT 401
#define CLK_PPMUCAMIF 402
#define CLK_PPMUTV 403
#define CLK_PPMUMFC_L 404
#define CLK_PPMUMFC_R 405
#define CLK_PPMUG3D 406
#define CLK_PPMUIMAGE 407
#define CLK_PPMULCD0 408
#define CLK_PPMULCD1 409 /* Exynos4210 only */
#define CLK_PPMUFILE 410
#define CLK_PPMUGPS 411
#define CLK_PPMUDMC0 412
#define CLK_PPMUDMC1 413
#define CLK_PPMUCPU 414
#define CLK_PPMUACP 415
/* div clocks */
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
#define CLK_DIV_ISP1 451 /* Exynos4x12 only */

2
include/dt-bindings/clock/exynos5250.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda@samsung.com>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

2
include/dt-bindings/clock/exynos5420.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda@samsung.com>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

2
include/dt-bindings/clock/exynos5440.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

40
include/dt-bindings/clock/imx1-clock.h Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX1_H
#define __DT_BINDINGS_CLOCK_IMX1_H
#define IMX1_CLK_DUMMY 0
#define IMX1_CLK_CLK32 1
#define IMX1_CLK_CLK16M_EXT 2
#define IMX1_CLK_CLK16M 3
#define IMX1_CLK_CLK32_PREMULT 4
#define IMX1_CLK_PREM 5
#define IMX1_CLK_MPLL 6
#define IMX1_CLK_MPLL_GATE 7
#define IMX1_CLK_SPLL 8
#define IMX1_CLK_SPLL_GATE 9
#define IMX1_CLK_MCU 10
#define IMX1_CLK_FCLK 11
#define IMX1_CLK_HCLK 12
#define IMX1_CLK_CLK48M 13
#define IMX1_CLK_PER1 14
#define IMX1_CLK_PER2 15
#define IMX1_CLK_PER3 16
#define IMX1_CLK_CLKO 17
#define IMX1_CLK_UART3_GATE 18
#define IMX1_CLK_SSI2_GATE 19
#define IMX1_CLK_BROM_GATE 20
#define IMX1_CLK_DMA_GATE 21
#define IMX1_CLK_CSI_GATE 22
#define IMX1_CLK_MMA_GATE 23
#define IMX1_CLK_USBD_GATE 24
#define IMX1_CLK_MAX 25
#endif

80
include/dt-bindings/clock/imx21-clock.h Normal file
View File

@@ -0,0 +1,80 @@
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX21_H
#define __DT_BINDINGS_CLOCK_IMX21_H
#define IMX21_CLK_DUMMY 0
#define IMX21_CLK_CKIL 1
#define IMX21_CLK_CKIH 2
#define IMX21_CLK_FPM 3
#define IMX21_CLK_CKIH_DIV1P5 4
#define IMX21_CLK_MPLL_GATE 5
#define IMX21_CLK_SPLL_GATE 6
#define IMX21_CLK_FPM_GATE 7
#define IMX21_CLK_CKIH_GATE 8
#define IMX21_CLK_MPLL_OSC_SEL 9
#define IMX21_CLK_IPG 10
#define IMX21_CLK_HCLK 11
#define IMX21_CLK_MPLL_SEL 12
#define IMX21_CLK_SPLL_SEL 13
#define IMX21_CLK_SSI1_SEL 14
#define IMX21_CLK_SSI2_SEL 15
#define IMX21_CLK_USB_DIV 16
#define IMX21_CLK_FCLK 17
#define IMX21_CLK_MPLL 18
#define IMX21_CLK_SPLL 19
#define IMX21_CLK_NFC_DIV 20
#define IMX21_CLK_SSI1_DIV 21
#define IMX21_CLK_SSI2_DIV 22
#define IMX21_CLK_PER1 23
#define IMX21_CLK_PER2 24
#define IMX21_CLK_PER3 25
#define IMX21_CLK_PER4 26
#define IMX21_CLK_UART1_IPG_GATE 27
#define IMX21_CLK_UART2_IPG_GATE 28
#define IMX21_CLK_UART3_IPG_GATE 29
#define IMX21_CLK_UART4_IPG_GATE 30
#define IMX21_CLK_CSPI1_IPG_GATE 31
#define IMX21_CLK_CSPI2_IPG_GATE 32
#define IMX21_CLK_SSI1_GATE 33
#define IMX21_CLK_SSI2_GATE 34
#define IMX21_CLK_SDHC1_IPG_GATE 35
#define IMX21_CLK_SDHC2_IPG_GATE 36
#define IMX21_CLK_GPIO_GATE 37
#define IMX21_CLK_I2C_GATE 38
#define IMX21_CLK_DMA_GATE 39
#define IMX21_CLK_USB_GATE 40
#define IMX21_CLK_EMMA_GATE 41
#define IMX21_CLK_SSI2_BAUD_GATE 42
#define IMX21_CLK_SSI1_BAUD_GATE 43
#define IMX21_CLK_LCDC_IPG_GATE 44
#define IMX21_CLK_NFC_GATE 45
#define IMX21_CLK_LCDC_HCLK_GATE 46
#define IMX21_CLK_PER4_GATE 47
#define IMX21_CLK_BMI_GATE 48
#define IMX21_CLK_USB_HCLK_GATE 49
#define IMX21_CLK_SLCDC_GATE 50
#define IMX21_CLK_SLCDC_HCLK_GATE 51
#define IMX21_CLK_EMMA_HCLK_GATE 52
#define IMX21_CLK_BROM_GATE 53
#define IMX21_CLK_DMA_HCLK_GATE 54
#define IMX21_CLK_CSI_HCLK_GATE 55
#define IMX21_CLK_CSPI3_IPG_GATE 56
#define IMX21_CLK_WDOG_GATE 57
#define IMX21_CLK_GPT1_IPG_GATE 58
#define IMX21_CLK_GPT2_IPG_GATE 59
#define IMX21_CLK_GPT3_IPG_GATE 60
#define IMX21_CLK_PWM_IPG_GATE 61
#define IMX21_CLK_RTC_GATE 62
#define IMX21_CLK_KPP_GATE 63
#define IMX21_CLK_OWIRE_GATE 64
#define IMX21_CLK_MAX 65
#endif

108
include/dt-bindings/clock/imx27-clock.h Normal file
View File

@@ -0,0 +1,108 @@
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX27_H
#define __DT_BINDINGS_CLOCK_IMX27_H
#define IMX27_CLK_DUMMY 0
#define IMX27_CLK_CKIH 1
#define IMX27_CLK_CKIL 2
#define IMX27_CLK_MPLL 3
#define IMX27_CLK_SPLL 4
#define IMX27_CLK_MPLL_MAIN2 5
#define IMX27_CLK_AHB 6
#define IMX27_CLK_IPG 7
#define IMX27_CLK_NFC_DIV 8
#define IMX27_CLK_PER1_DIV 9
#define IMX27_CLK_PER2_DIV 10
#define IMX27_CLK_PER3_DIV 11
#define IMX27_CLK_PER4_DIV 12
#define IMX27_CLK_VPU_SEL 13
#define IMX27_CLK_VPU_DIV 14
#define IMX27_CLK_USB_DIV 15
#define IMX27_CLK_CPU_SEL 16
#define IMX27_CLK_CLKO_SEL 17
#define IMX27_CLK_CPU_DIV 18
#define IMX27_CLK_CLKO_DIV 19
#define IMX27_CLK_SSI1_SEL 20
#define IMX27_CLK_SSI2_SEL 21
#define IMX27_CLK_SSI1_DIV 22
#define IMX27_CLK_SSI2_DIV 23
#define IMX27_CLK_CLKO_EN 24
#define IMX27_CLK_SSI2_IPG_GATE 25
#define IMX27_CLK_SSI1_IPG_GATE 26
#define IMX27_CLK_SLCDC_IPG_GATE 27
#define IMX27_CLK_SDHC3_IPG_GATE 28
#define IMX27_CLK_SDHC2_IPG_GATE 29
#define IMX27_CLK_SDHC1_IPG_GATE 30
#define IMX27_CLK_SCC_IPG_GATE 31
#define IMX27_CLK_SAHARA_IPG_GATE 32
#define IMX27_CLK_RTC_IPG_GATE 33
#define IMX27_CLK_PWM_IPG_GATE 34
#define IMX27_CLK_OWIRE_IPG_GATE 35
#define IMX27_CLK_LCDC_IPG_GATE 36
#define IMX27_CLK_KPP_IPG_GATE 37
#define IMX27_CLK_IIM_IPG_GATE 38
#define IMX27_CLK_I2C2_IPG_GATE 39
#define IMX27_CLK_I2C1_IPG_GATE 40
#define IMX27_CLK_GPT6_IPG_GATE 41
#define IMX27_CLK_GPT5_IPG_GATE 42
#define IMX27_CLK_GPT4_IPG_GATE 43
#define IMX27_CLK_GPT3_IPG_GATE 44
#define IMX27_CLK_GPT2_IPG_GATE 45
#define IMX27_CLK_GPT1_IPG_GATE 46
#define IMX27_CLK_GPIO_IPG_GATE 47
#define IMX27_CLK_FEC_IPG_GATE 48
#define IMX27_CLK_EMMA_IPG_GATE 49
#define IMX27_CLK_DMA_IPG_GATE 50
#define IMX27_CLK_CSPI3_IPG_GATE 51
#define IMX27_CLK_CSPI2_IPG_GATE 52
#define IMX27_CLK_CSPI1_IPG_GATE 53
#define IMX27_CLK_NFC_BAUD_GATE 54
#define IMX27_CLK_SSI2_BAUD_GATE 55
#define IMX27_CLK_SSI1_BAUD_GATE 56
#define IMX27_CLK_VPU_BAUD_GATE 57
#define IMX27_CLK_PER4_GATE 58
#define IMX27_CLK_PER3_GATE 59
#define IMX27_CLK_PER2_GATE 60
#define IMX27_CLK_PER1_GATE 61
#define IMX27_CLK_USB_AHB_GATE 62
#define IMX27_CLK_SLCDC_AHB_GATE 63
#define IMX27_CLK_SAHARA_AHB_GATE 64
#define IMX27_CLK_LCDC_AHB_GATE 65
#define IMX27_CLK_VPU_AHB_GATE 66
#define IMX27_CLK_FEC_AHB_GATE 67
#define IMX27_CLK_EMMA_AHB_GATE 68
#define IMX27_CLK_EMI_AHB_GATE 69
#define IMX27_CLK_DMA_AHB_GATE 70
#define IMX27_CLK_CSI_AHB_GATE 71
#define IMX27_CLK_BROM_AHB_GATE 72
#define IMX27_CLK_ATA_AHB_GATE 73
#define IMX27_CLK_WDOG_IPG_GATE 74
#define IMX27_CLK_USB_IPG_GATE 75
#define IMX27_CLK_UART6_IPG_GATE 76
#define IMX27_CLK_UART5_IPG_GATE 77
#define IMX27_CLK_UART4_IPG_GATE 78
#define IMX27_CLK_UART3_IPG_GATE 79
#define IMX27_CLK_UART2_IPG_GATE 80
#define IMX27_CLK_UART1_IPG_GATE 81
#define IMX27_CLK_CKIH_DIV1P5 82
#define IMX27_CLK_FPM 83
#define IMX27_CLK_MPLL_OSC_SEL 84
#define IMX27_CLK_MPLL_SEL 85
#define IMX27_CLK_SPLL_GATE 86
#define IMX27_CLK_MSHC_DIV 87
#define IMX27_CLK_RTIC_IPG_GATE 88
#define IMX27_CLK_MSHC_IPG_GATE 89
#define IMX27_CLK_RTIC_AHB_GATE 90
#define IMX27_CLK_MSHC_BAUD_GATE 91
#define IMX27_CLK_CKIH_GATE 92
#define IMX27_CLK_MAX 93
#endif

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include/dt-bindings/clock/imx6qdl-clock.h Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
#define __DT_BINDINGS_CLOCK_IMX6QDL_H
#define IMX6QDL_CLK_DUMMY 0
#define IMX6QDL_CLK_CKIL 1
#define IMX6QDL_CLK_CKIH 2
#define IMX6QDL_CLK_OSC 3
#define IMX6QDL_CLK_PLL2_PFD0_352M 4
#define IMX6QDL_CLK_PLL2_PFD1_594M 5
#define IMX6QDL_CLK_PLL2_PFD2_396M 6
#define IMX6QDL_CLK_PLL3_PFD0_720M 7
#define IMX6QDL_CLK_PLL3_PFD1_540M 8
#define IMX6QDL_CLK_PLL3_PFD2_508M 9
#define IMX6QDL_CLK_PLL3_PFD3_454M 10
#define IMX6QDL_CLK_PLL2_198M 11
#define IMX6QDL_CLK_PLL3_120M 12
#define IMX6QDL_CLK_PLL3_80M 13
#define IMX6QDL_CLK_PLL3_60M 14
#define IMX6QDL_CLK_TWD 15
#define IMX6QDL_CLK_STEP 16
#define IMX6QDL_CLK_PLL1_SW 17
#define IMX6QDL_CLK_PERIPH_PRE 18
#define IMX6QDL_CLK_PERIPH2_PRE 19
#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
#define IMX6QDL_CLK_AXI_SEL 22
#define IMX6QDL_CLK_ESAI_SEL 23
#define IMX6QDL_CLK_ASRC_SEL 24
#define IMX6QDL_CLK_SPDIF_SEL 25
#define IMX6QDL_CLK_GPU2D_AXI 26
#define IMX6QDL_CLK_GPU3D_AXI 27
#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
#define IMX6QDL_CLK_IPU1_SEL 31
#define IMX6QDL_CLK_IPU2_SEL 32
#define IMX6QDL_CLK_LDB_DI0_SEL 33
#define IMX6QDL_CLK_LDB_DI1_SEL 34
#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
#define IMX6QDL_CLK_IPU1_DI0_SEL 39
#define IMX6QDL_CLK_IPU1_DI1_SEL 40
#define IMX6QDL_CLK_IPU2_DI0_SEL 41
#define IMX6QDL_CLK_IPU2_DI1_SEL 42
#define IMX6QDL_CLK_HSI_TX_SEL 43
#define IMX6QDL_CLK_PCIE_AXI_SEL 44
#define IMX6QDL_CLK_SSI1_SEL 45
#define IMX6QDL_CLK_SSI2_SEL 46
#define IMX6QDL_CLK_SSI3_SEL 47
#define IMX6QDL_CLK_USDHC1_SEL 48
#define IMX6QDL_CLK_USDHC2_SEL 49
#define IMX6QDL_CLK_USDHC3_SEL 50
#define IMX6QDL_CLK_USDHC4_SEL 51
#define IMX6QDL_CLK_ENFC_SEL 52
#define IMX6QDL_CLK_EMI_SEL 53
#define IMX6QDL_CLK_EMI_SLOW_SEL 54
#define IMX6QDL_CLK_VDO_AXI_SEL 55
#define IMX6QDL_CLK_VPU_AXI_SEL 56
#define IMX6QDL_CLK_CKO1_SEL 57
#define IMX6QDL_CLK_PERIPH 58
#define IMX6QDL_CLK_PERIPH2 59
#define IMX6QDL_CLK_PERIPH_CLK2 60
#define IMX6QDL_CLK_PERIPH2_CLK2 61
#define IMX6QDL_CLK_IPG 62
#define IMX6QDL_CLK_IPG_PER 63
#define IMX6QDL_CLK_ESAI_PRED 64
#define IMX6QDL_CLK_ESAI_PODF 65
#define IMX6QDL_CLK_ASRC_PRED 66
#define IMX6QDL_CLK_ASRC_PODF 67
#define IMX6QDL_CLK_SPDIF_PRED 68
#define IMX6QDL_CLK_SPDIF_PODF 69
#define IMX6QDL_CLK_CAN_ROOT 70
#define IMX6QDL_CLK_ECSPI_ROOT 71
#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
#define IMX6QDL_CLK_GPU3D_SHADER 74
#define IMX6QDL_CLK_IPU1_PODF 75
#define IMX6QDL_CLK_IPU2_PODF 76
#define IMX6QDL_CLK_LDB_DI0_PODF 77
#define IMX6QDL_CLK_LDB_DI1_PODF 78
#define IMX6QDL_CLK_IPU1_DI0_PRE 79
#define IMX6QDL_CLK_IPU1_DI1_PRE 80
#define IMX6QDL_CLK_IPU2_DI0_PRE 81
#define IMX6QDL_CLK_IPU2_DI1_PRE 82
#define IMX6QDL_CLK_HSI_TX_PODF 83
#define IMX6QDL_CLK_SSI1_PRED 84
#define IMX6QDL_CLK_SSI1_PODF 85
#define IMX6QDL_CLK_SSI2_PRED 86
#define IMX6QDL_CLK_SSI2_PODF 87
#define IMX6QDL_CLK_SSI3_PRED 88
#define IMX6QDL_CLK_SSI3_PODF 89
#define IMX6QDL_CLK_UART_SERIAL_PODF 90
#define IMX6QDL_CLK_USDHC1_PODF 91
#define IMX6QDL_CLK_USDHC2_PODF 92
#define IMX6QDL_CLK_USDHC3_PODF 93
#define IMX6QDL_CLK_USDHC4_PODF 94
#define IMX6QDL_CLK_ENFC_PRED 95
#define IMX6QDL_CLK_ENFC_PODF 96
#define IMX6QDL_CLK_EMI_PODF 97
#define IMX6QDL_CLK_EMI_SLOW_PODF 98
#define IMX6QDL_CLK_VPU_AXI_PODF 99
#define IMX6QDL_CLK_CKO1_PODF 100
#define IMX6QDL_CLK_AXI 101
#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
#define IMX6QDL_CLK_ARM 104
#define IMX6QDL_CLK_AHB 105
#define IMX6QDL_CLK_APBH_DMA 106
#define IMX6QDL_CLK_ASRC 107
#define IMX6QDL_CLK_CAN1_IPG 108
#define IMX6QDL_CLK_CAN1_SERIAL 109
#define IMX6QDL_CLK_CAN2_IPG 110
#define IMX6QDL_CLK_CAN2_SERIAL 111
#define IMX6QDL_CLK_ECSPI1 112
#define IMX6QDL_CLK_ECSPI2 113
#define IMX6QDL_CLK_ECSPI3 114
#define IMX6QDL_CLK_ECSPI4 115
#define IMX6Q_CLK_ECSPI5 116
#define IMX6DL_CLK_I2C4 116
#define IMX6QDL_CLK_ENET 117
#define IMX6QDL_CLK_ESAI 118
#define IMX6QDL_CLK_GPT_IPG 119
#define IMX6QDL_CLK_GPT_IPG_PER 120
#define IMX6QDL_CLK_GPU2D_CORE 121
#define IMX6QDL_CLK_GPU3D_CORE 122
#define IMX6QDL_CLK_HDMI_IAHB 123
#define IMX6QDL_CLK_HDMI_ISFR 124
#define IMX6QDL_CLK_I2C1 125
#define IMX6QDL_CLK_I2C2 126
#define IMX6QDL_CLK_I2C3 127
#define IMX6QDL_CLK_IIM 128
#define IMX6QDL_CLK_ENFC 129
#define IMX6QDL_CLK_IPU1 130
#define IMX6QDL_CLK_IPU1_DI0 131
#define IMX6QDL_CLK_IPU1_DI1 132
#define IMX6QDL_CLK_IPU2 133
#define IMX6QDL_CLK_IPU2_DI0 134
#define IMX6QDL_CLK_LDB_DI0 135
#define IMX6QDL_CLK_LDB_DI1 136
#define IMX6QDL_CLK_IPU2_DI1 137
#define IMX6QDL_CLK_HSI_TX 138
#define IMX6QDL_CLK_MLB 139
#define IMX6QDL_CLK_MMDC_CH0_AXI 140
#define IMX6QDL_CLK_MMDC_CH1_AXI 141
#define IMX6QDL_CLK_OCRAM 142
#define IMX6QDL_CLK_OPENVG_AXI 143
#define IMX6QDL_CLK_PCIE_AXI 144
#define IMX6QDL_CLK_PWM1 145
#define IMX6QDL_CLK_PWM2 146
#define IMX6QDL_CLK_PWM3 147
#define IMX6QDL_CLK_PWM4 148
#define IMX6QDL_CLK_PER1_BCH 149
#define IMX6QDL_CLK_GPMI_BCH_APB 150
#define IMX6QDL_CLK_GPMI_BCH 151
#define IMX6QDL_CLK_GPMI_IO 152
#define IMX6QDL_CLK_GPMI_APB 153
#define IMX6QDL_CLK_SATA 154
#define IMX6QDL_CLK_SDMA 155
#define IMX6QDL_CLK_SPBA 156
#define IMX6QDL_CLK_SSI1 157
#define IMX6QDL_CLK_SSI2 158
#define IMX6QDL_CLK_SSI3 159
#define IMX6QDL_CLK_UART_IPG 160
#define IMX6QDL_CLK_UART_SERIAL 161
#define IMX6QDL_CLK_USBOH3 162
#define IMX6QDL_CLK_USDHC1 163
#define IMX6QDL_CLK_USDHC2 164
#define IMX6QDL_CLK_USDHC3 165
#define IMX6QDL_CLK_USDHC4 166
#define IMX6QDL_CLK_VDO_AXI 167
#define IMX6QDL_CLK_VPU_AXI 168
#define IMX6QDL_CLK_CKO1 169
#define IMX6QDL_CLK_PLL1_SYS 170
#define IMX6QDL_CLK_PLL2_BUS 171
#define IMX6QDL_CLK_PLL3_USB_OTG 172
#define IMX6QDL_CLK_PLL4_AUDIO 173
#define IMX6QDL_CLK_PLL5_VIDEO 174
#define IMX6QDL_CLK_PLL8_MLB 175
#define IMX6QDL_CLK_PLL7_USB_HOST 176
#define IMX6QDL_CLK_PLL6_ENET 177
#define IMX6QDL_CLK_SSI1_IPG 178
#define IMX6QDL_CLK_SSI2_IPG 179
#define IMX6QDL_CLK_SSI3_IPG 180
#define IMX6QDL_CLK_ROM 181
#define IMX6QDL_CLK_USBPHY1 182
#define IMX6QDL_CLK_USBPHY2 183
#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
#define IMX6QDL_CLK_SATA_REF 186
#define IMX6QDL_CLK_SATA_REF_100M 187
#define IMX6QDL_CLK_PCIE_REF 188
#define IMX6QDL_CLK_PCIE_REF_125M 189
#define IMX6QDL_CLK_ENET_REF 190
#define IMX6QDL_CLK_USBPHY1_GATE 191
#define IMX6QDL_CLK_USBPHY2_GATE 192
#define IMX6QDL_CLK_PLL4_POST_DIV 193
#define IMX6QDL_CLK_PLL5_POST_DIV 194
#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
#define IMX6QDL_CLK_EIM_SLOW 196
#define IMX6QDL_CLK_SPDIF 197
#define IMX6QDL_CLK_CKO2_SEL 198
#define IMX6QDL_CLK_CKO2_PODF 199
#define IMX6QDL_CLK_CKO2 200
#define IMX6QDL_CLK_CKO 201
#define IMX6QDL_CLK_VDOA 202
#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
#define IMX6QDL_CLK_LVDS1_SEL 204
#define IMX6QDL_CLK_LVDS2_SEL 205
#define IMX6QDL_CLK_LVDS1_GATE 206
#define IMX6QDL_CLK_LVDS2_GATE 207
#define IMX6QDL_CLK_ESAI_AHB 208
#define IMX6QDL_CLK_END 209
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

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include/dt-bindings/clock/qcom,gcc-apq8084.h Normal file
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/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H
#define _DT_BINDINGS_CLK_APQ_GCC_8084_H
#define GPLL0 0
#define GPLL0_VOTE 1
#define GPLL1 2
#define GPLL1_VOTE 3
#define GPLL2 4
#define GPLL2_VOTE 5
#define GPLL3 6
#define GPLL3_VOTE 7
#define GPLL4 8
#define GPLL4_VOTE 9
#define CONFIG_NOC_CLK_SRC 10
#define PERIPH_NOC_CLK_SRC 11
#define SYSTEM_NOC_CLK_SRC 12
#define BLSP_UART_SIM_CLK_SRC 13
#define QDSS_TSCTR_CLK_SRC 14
#define UFS_AXI_CLK_SRC 15
#define RPM_CLK_SRC 16
#define KPSS_AHB_CLK_SRC 17
#define QDSS_AT_CLK_SRC 18
#define BIMC_DDR_CLK_SRC 19
#define USB30_MASTER_CLK_SRC 20
#define USB30_SEC_MASTER_CLK_SRC 21
#define USB_HSIC_AHB_CLK_SRC 22
#define MMSS_BIMC_GFX_CLK_SRC 23
#define QDSS_STM_CLK_SRC 24
#define ACC_CLK_SRC 25
#define SEC_CTRL_CLK_SRC 26
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38
#define BLSP1_UART1_APPS_CLK_SRC 39
#define BLSP1_UART2_APPS_CLK_SRC 40
#define BLSP1_UART3_APPS_CLK_SRC 41
#define BLSP1_UART4_APPS_CLK_SRC 42
#define BLSP1_UART5_APPS_CLK_SRC 43
#define BLSP1_UART6_APPS_CLK_SRC 44
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52
#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53
#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55
#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56
#define BLSP2_UART1_APPS_CLK_SRC 57
#define BLSP2_UART2_APPS_CLK_SRC 58
#define BLSP2_UART3_APPS_CLK_SRC 59
#define BLSP2_UART4_APPS_CLK_SRC 60
#define BLSP2_UART5_APPS_CLK_SRC 61
#define BLSP2_UART6_APPS_CLK_SRC 62
#define CE1_CLK_SRC 63
#define CE2_CLK_SRC 64
#define CE3_CLK_SRC 65
#define GP1_CLK_SRC 66
#define GP2_CLK_SRC 67
#define GP3_CLK_SRC 68
#define PDM2_CLK_SRC 69
#define QDSS_TRACECLKIN_CLK_SRC 70
#define RBCPR_CLK_SRC 71
#define SATA_ASIC0_CLK_SRC 72
#define SATA_PMALIVE_CLK_SRC 73
#define SATA_RX_CLK_SRC 74
#define SATA_RX_OOB_CLK_SRC 75
#define SDCC1_APPS_CLK_SRC 76
#define SDCC2_APPS_CLK_SRC 77
#define SDCC3_APPS_CLK_SRC 78
#define SDCC4_APPS_CLK_SRC 79
#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80
#define SPMI_AHB_CLK_SRC 81
#define SPMI_SER_CLK_SRC 82
#define TSIF_REF_CLK_SRC 83
#define USB30_MOCK_UTMI_CLK_SRC 84
#define USB30_SEC_MOCK_UTMI_CLK_SRC 85
#define USB_HS_SYSTEM_CLK_SRC 86
#define USB_HSIC_CLK_SRC 87
#define USB_HSIC_IO_CAL_CLK_SRC 88
#define USB_HSIC_MOCK_UTMI_CLK_SRC 89
#define USB_HSIC_SYSTEM_CLK_SRC 90
#define GCC_BAM_DMA_AHB_CLK 91
#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92
#define DDR_CLK_SRC 93
#define GCC_BIMC_CFG_AHB_CLK 94
#define GCC_BIMC_CLK 95
#define GCC_BIMC_KPSS_AXI_CLK 96
#define GCC_BIMC_SLEEP_CLK 97
#define GCC_BIMC_SYSNOC_AXI_CLK 98
#define GCC_BIMC_XO_CLK 99
#define GCC_BLSP1_AHB_CLK 100
#define GCC_BLSP1_SLEEP_CLK 101
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113
#define GCC_BLSP1_UART1_APPS_CLK 114
#define GCC_BLSP1_UART1_SIM_CLK 115
#define GCC_BLSP1_UART2_APPS_CLK 116
#define GCC_BLSP1_UART2_SIM_CLK 117
#define GCC_BLSP1_UART3_APPS_CLK 118
#define GCC_BLSP1_UART3_SIM_CLK 119
#define GCC_BLSP1_UART4_APPS_CLK 120
#define GCC_BLSP1_UART4_SIM_CLK 121
#define GCC_BLSP1_UART5_APPS_CLK 122
#define GCC_BLSP1_UART5_SIM_CLK 123
#define GCC_BLSP1_UART6_APPS_CLK 124
#define GCC_BLSP1_UART6_SIM_CLK 125
#define GCC_BLSP2_AHB_CLK 126
#define GCC_BLSP2_SLEEP_CLK 127
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135
#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136
#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137
#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138
#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139
#define GCC_BLSP2_UART1_APPS_CLK 140
#define GCC_BLSP2_UART1_SIM_CLK 141
#define GCC_BLSP2_UART2_APPS_CLK 142
#define GCC_BLSP2_UART2_SIM_CLK 143
#define GCC_BLSP2_UART3_APPS_CLK 144
#define GCC_BLSP2_UART3_SIM_CLK 145
#define GCC_BLSP2_UART4_APPS_CLK 146
#define GCC_BLSP2_UART4_SIM_CLK 147
#define GCC_BLSP2_UART5_APPS_CLK 148
#define GCC_BLSP2_UART5_SIM_CLK 149
#define GCC_BLSP2_UART6_APPS_CLK 150
#define GCC_BLSP2_UART6_SIM_CLK 151
#define GCC_BOOT_ROM_AHB_CLK 152
#define GCC_CE1_AHB_CLK 153
#define GCC_CE1_AXI_CLK 154
#define GCC_CE1_CLK 155
#define GCC_CE2_AHB_CLK 156
#define GCC_CE2_AXI_CLK 157
#define GCC_CE2_CLK 158
#define GCC_CE3_AHB_CLK 159
#define GCC_CE3_AXI_CLK 160
#define GCC_CE3_CLK 161
#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162
#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163
#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164
#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165
#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166
#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167
#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168
#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169
#define GCC_CFG_NOC_AHB_CLK 170
#define GCC_CFG_NOC_DDR_CFG_CLK 171
#define GCC_CFG_NOC_RPM_AHB_CLK 172
#define GCC_COPSS_SMMU_AHB_CLK 173
#define GCC_COPSS_SMMU_AXI_CLK 174
#define GCC_DCD_XO_CLK 175
#define GCC_BIMC_DDR_CH0_CLK 176
#define GCC_BIMC_DDR_CH1_CLK 177
#define GCC_BIMC_DDR_CPLL0_CLK 178
#define GCC_BIMC_DDR_CPLL1_CLK 179
#define GCC_BIMC_GFX_CLK 180
#define GCC_DDR_DIM_CFG_CLK 181
#define GCC_DDR_DIM_SLEEP_CLK 182
#define GCC_DEHR_CLK 183
#define GCC_AHB_CLK 184
#define GCC_IM_SLEEP_CLK 185
#define GCC_XO_CLK 186
#define GCC_XO_DIV4_CLK 187
#define GCC_GP1_CLK 188
#define GCC_GP2_CLK 189
#define GCC_GP3_CLK 190
#define GCC_IMEM_AXI_CLK 191
#define GCC_IMEM_CFG_AHB_CLK 192
#define GCC_KPSS_AHB_CLK 193
#define GCC_KPSS_AXI_CLK 194
#define GCC_LPASS_MPORT_AXI_CLK 195
#define GCC_LPASS_Q6_AXI_CLK 196
#define GCC_LPASS_SWAY_CLK 197
#define GCC_MMSS_BIMC_GFX_CLK 198
#define GCC_MMSS_NOC_AT_CLK 199
#define GCC_MMSS_NOC_CFG_AHB_CLK 200
#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201
#define GCC_OCMEM_NOC_CFG_AHB_CLK 202
#define GCC_OCMEM_SYS_NOC_AXI_CLK 203
#define GCC_MPM_AHB_CLK 204
#define GCC_MSG_RAM_AHB_CLK 205
#define GCC_NOC_CONF_XPU_AHB_CLK 206
#define GCC_PDM2_CLK 207
#define GCC_PDM_AHB_CLK 208
#define GCC_PDM_XO4_CLK 209
#define GCC_PERIPH_NOC_AHB_CLK 210
#define GCC_PERIPH_NOC_AT_CLK 211
#define GCC_PERIPH_NOC_CFG_AHB_CLK 212
#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213
#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214
#define GCC_PERIPH_XPU_AHB_CLK 215
#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216
#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217
#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218
#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219
#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220
#define GCC_PRNG_AHB_CLK 221
#define GCC_QDSS_AT_CLK 222
#define GCC_QDSS_CFG_AHB_CLK 223
#define GCC_QDSS_DAP_AHB_CLK 224
#define GCC_QDSS_DAP_CLK 225
#define GCC_QDSS_ETR_USB_CLK 226
#define GCC_QDSS_STM_CLK 227
#define GCC_QDSS_TRACECLKIN_CLK 228
#define GCC_QDSS_TSCTR_DIV16_CLK 229
#define GCC_QDSS_TSCTR_DIV2_CLK 230
#define GCC_QDSS_TSCTR_DIV3_CLK 231
#define GCC_QDSS_TSCTR_DIV4_CLK 232
#define GCC_QDSS_TSCTR_DIV8_CLK 233
#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234
#define GCC_RBCPR_AHB_CLK 235
#define GCC_RBCPR_CLK 236
#define GCC_RPM_BUS_AHB_CLK 237
#define GCC_RPM_PROC_HCLK 238
#define GCC_RPM_SLEEP_CLK 239
#define GCC_RPM_TIMER_CLK 240
#define GCC_SATA_ASIC0_CLK 241
#define GCC_SATA_AXI_CLK 242
#define GCC_SATA_CFG_AHB_CLK 243
#define GCC_SATA_PMALIVE_CLK 244
#define GCC_SATA_RX_CLK 245
#define GCC_SATA_RX_OOB_CLK 246
#define GCC_SDCC1_AHB_CLK 247
#define GCC_SDCC1_APPS_CLK 248
#define GCC_SDCC1_CDCCAL_FF_CLK 249
#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250
#define GCC_SDCC2_AHB_CLK 251
#define GCC_SDCC2_APPS_CLK 252
#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253
#define GCC_SDCC3_AHB_CLK 254
#define GCC_SDCC3_APPS_CLK 255
#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256
#define GCC_SDCC4_AHB_CLK 257
#define GCC_SDCC4_APPS_CLK 258
#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259
#define GCC_SEC_CTRL_ACC_CLK 260
#define GCC_SEC_CTRL_AHB_CLK 261
#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262
#define GCC_SEC_CTRL_CLK 263
#define GCC_SEC_CTRL_SENSE_CLK 264
#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265
#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266
#define GCC_SPDM_BIMC_CY_CLK 267
#define GCC_SPDM_CFG_AHB_CLK 268
#define GCC_SPDM_DEBUG_CY_CLK 269
#define GCC_SPDM_FF_CLK 270
#define GCC_SPDM_MSTR_AHB_CLK 271
#define GCC_SPDM_PNOC_CY_CLK 272
#define GCC_SPDM_RPM_CY_CLK 273
#define GCC_SPDM_SNOC_CY_CLK 274
#define GCC_SPMI_AHB_CLK 275
#define GCC_SPMI_CNOC_AHB_CLK 276
#define GCC_SPMI_SER_CLK 277
#define GCC_SPSS_AHB_CLK 278
#define GCC_SNOC_CNOC_AHB_CLK 279
#define GCC_SNOC_PNOC_AHB_CLK 280
#define GCC_SYS_NOC_AT_CLK 281
#define GCC_SYS_NOC_AXI_CLK 282
#define GCC_SYS_NOC_KPSS_AHB_CLK 283
#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284
#define GCC_SYS_NOC_UFS_AXI_CLK 285
#define GCC_SYS_NOC_USB3_AXI_CLK 286
#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287
#define GCC_TCSR_AHB_CLK 288
#define GCC_TLMM_AHB_CLK 289
#define GCC_TLMM_CLK 290
#define GCC_TSIF_AHB_CLK 291
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292
#define GCC_TSIF_REF_CLK 293
#define GCC_UFS_AHB_CLK 294
#define GCC_UFS_AXI_CLK 295
#define GCC_UFS_RX_CFG_CLK 296
#define GCC_UFS_RX_SYMBOL_0_CLK 297
#define GCC_UFS_RX_SYMBOL_1_CLK 298
#define GCC_UFS_TX_CFG_CLK 299
#define GCC_UFS_TX_SYMBOL_0_CLK 300
#define GCC_UFS_TX_SYMBOL_1_CLK 301
#define GCC_USB2A_PHY_SLEEP_CLK 302
#define GCC_USB2B_PHY_SLEEP_CLK 303
#define GCC_USB30_MASTER_CLK 304
#define GCC_USB30_MOCK_UTMI_CLK 305
#define GCC_USB30_SLEEP_CLK 306
#define GCC_USB30_SEC_MASTER_CLK 307
#define GCC_USB30_SEC_MOCK_UTMI_CLK 308
#define GCC_USB30_SEC_SLEEP_CLK 309
#define GCC_USB_HS_AHB_CLK 310
#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311
#define GCC_USB_HS_SYSTEM_CLK 312
#define GCC_USB_HSIC_AHB_CLK 313
#define GCC_USB_HSIC_CLK 314
#define GCC_USB_HSIC_IO_CAL_CLK 315
#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316
#define GCC_USB_HSIC_MOCK_UTMI_CLK 317
#define GCC_USB_HSIC_SYSTEM_CLK 318
#define PCIE_0_AUX_CLK_SRC 319
#define PCIE_0_PIPE_CLK_SRC 320
#define PCIE_1_AUX_CLK_SRC 321
#define PCIE_1_PIPE_CLK_SRC 322
#define GCC_PCIE_0_AUX_CLK 323
#define GCC_PCIE_0_CFG_AHB_CLK 324
#define GCC_PCIE_0_MSTR_AXI_CLK 325
#define GCC_PCIE_0_PIPE_CLK 326
#define GCC_PCIE_0_SLV_AXI_CLK 327
#define GCC_PCIE_1_AUX_CLK 328
#define GCC_PCIE_1_CFG_AHB_CLK 329
#define GCC_PCIE_1_MSTR_AXI_CLK 330
#define GCC_PCIE_1_PIPE_CLK 331
#define GCC_PCIE_1_SLV_AXI_CLK 332
#endif

293
include/dt-bindings/clock/qcom,gcc-ipq806x.h Normal file
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@@ -0,0 +1,293 @@
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
#define _DT_BINDINGS_CLK_GCC_IPQ806X_H
#define AFAB_CLK_SRC 0
#define QDSS_STM_CLK 1
#define SCSS_A_CLK 2
#define SCSS_H_CLK 3
#define AFAB_CORE_CLK 4
#define SCSS_XO_SRC_CLK 5
#define AFAB_EBI1_CH0_A_CLK 6
#define AFAB_EBI1_CH1_A_CLK 7
#define AFAB_AXI_S0_FCLK 8
#define AFAB_AXI_S1_FCLK 9
#define AFAB_AXI_S2_FCLK 10
#define AFAB_AXI_S3_FCLK 11
#define AFAB_AXI_S4_FCLK 12
#define SFAB_CORE_CLK 13
#define SFAB_AXI_S0_FCLK 14
#define SFAB_AXI_S1_FCLK 15
#define SFAB_AXI_S2_FCLK 16
#define SFAB_AXI_S3_FCLK 17
#define SFAB_AXI_S4_FCLK 18
#define SFAB_AXI_S5_FCLK 19
#define SFAB_AHB_S0_FCLK 20
#define SFAB_AHB_S1_FCLK 21
#define SFAB_AHB_S2_FCLK 22
#define SFAB_AHB_S3_FCLK 23
#define SFAB_AHB_S4_FCLK 24
#define SFAB_AHB_S5_FCLK 25
#define SFAB_AHB_S6_FCLK 26
#define SFAB_AHB_S7_FCLK 27
#define QDSS_AT_CLK_SRC 28
#define QDSS_AT_CLK 29
#define QDSS_TRACECLKIN_CLK_SRC 30
#define QDSS_TRACECLKIN_CLK 31
#define QDSS_TSCTR_CLK_SRC 32
#define QDSS_TSCTR_CLK 33
#define SFAB_ADM0_M0_A_CLK 34
#define SFAB_ADM0_M1_A_CLK 35
#define SFAB_ADM0_M2_H_CLK 36
#define ADM0_CLK 37
#define ADM0_PBUS_CLK 38
#define IMEM0_A_CLK 39
#define QDSS_H_CLK 40
#define PCIE_A_CLK 41
#define PCIE_AUX_CLK 42
#define PCIE_H_CLK 43
#define PCIE_PHY_CLK 44
#define SFAB_CLK_SRC 45
#define SFAB_LPASS_Q6_A_CLK 46
#define SFAB_AFAB_M_A_CLK 47
#define AFAB_SFAB_M0_A_CLK 48
#define AFAB_SFAB_M1_A_CLK 49
#define SFAB_SATA_S_H_CLK 50
#define DFAB_CLK_SRC 51
#define DFAB_CLK 52
#define SFAB_DFAB_M_A_CLK 53
#define DFAB_SFAB_M_A_CLK 54
#define DFAB_SWAY0_H_CLK 55
#define DFAB_SWAY1_H_CLK 56
#define DFAB_ARB0_H_CLK 57
#define DFAB_ARB1_H_CLK 58
#define PPSS_H_CLK 59
#define PPSS_PROC_CLK 60
#define PPSS_TIMER0_CLK 61
#define PPSS_TIMER1_CLK 62
#define PMEM_A_CLK 63
#define DMA_BAM_H_CLK 64
#define SIC_H_CLK 65
#define SPS_TIC_H_CLK 66
#define CFPB_2X_CLK_SRC 67
#define CFPB_CLK 68
#define CFPB0_H_CLK 69
#define CFPB1_H_CLK 70
#define CFPB2_H_CLK 71
#define SFAB_CFPB_M_H_CLK 72
#define CFPB_MASTER_H_CLK 73
#define SFAB_CFPB_S_H_CLK 74
#define CFPB_SPLITTER_H_CLK 75
#define TSIF_H_CLK 76
#define TSIF_INACTIVITY_TIMERS_CLK 77
#define TSIF_REF_SRC 78
#define TSIF_REF_CLK 79
#define CE1_H_CLK 80
#define CE1_CORE_CLK 81
#define CE1_SLEEP_CLK 82
#define CE2_H_CLK 83
#define CE2_CORE_CLK 84
#define SFPB_H_CLK_SRC 85
#define SFPB_H_CLK 86
#define SFAB_SFPB_M_H_CLK 87
#define SFAB_SFPB_S_H_CLK 88
#define RPM_PROC_CLK 89
#define RPM_BUS_H_CLK 90
#define RPM_SLEEP_CLK 91
#define RPM_TIMER_CLK 92
#define RPM_MSG_RAM_H_CLK 93
#define PMIC_ARB0_H_CLK 94
#define PMIC_ARB1_H_CLK 95
#define PMIC_SSBI2_SRC 96
#define PMIC_SSBI2_CLK 97
#define SDC1_H_CLK 98
#define SDC2_H_CLK 99
#define SDC3_H_CLK 100
#define SDC4_H_CLK 101
#define SDC1_SRC 102
#define SDC1_CLK 103
#define SDC2_SRC 104
#define SDC2_CLK 105
#define SDC3_SRC 106
#define SDC3_CLK 107
#define SDC4_SRC 108
#define SDC4_CLK 109
#define USB_HS1_H_CLK 110
#define USB_HS1_XCVR_SRC 111
#define USB_HS1_XCVR_CLK 112
#define USB_HSIC_H_CLK 113
#define USB_HSIC_XCVR_SRC 114
#define USB_HSIC_XCVR_CLK 115
#define USB_HSIC_SYSTEM_CLK_SRC 116
#define USB_HSIC_SYSTEM_CLK 117
#define CFPB0_C0_H_CLK 118
#define CFPB0_D0_H_CLK 119
#define CFPB0_C1_H_CLK 120
#define CFPB0_D1_H_CLK 121
#define USB_FS1_H_CLK 122
#define USB_FS1_XCVR_SRC 123
#define USB_FS1_XCVR_CLK 124
#define USB_FS1_SYSTEM_CLK 125
#define GSBI_COMMON_SIM_SRC 126
#define GSBI1_H_CLK 127
#define GSBI2_H_CLK 128
#define GSBI3_H_CLK 129
#define GSBI4_H_CLK 130
#define GSBI5_H_CLK 131
#define GSBI6_H_CLK 132
#define GSBI7_H_CLK 133
#define GSBI1_QUP_SRC 134
#define GSBI1_QUP_CLK 135
#define GSBI2_QUP_SRC 136
#define GSBI2_QUP_CLK 137
#define GSBI3_QUP_SRC 138
#define GSBI3_QUP_CLK 139
#define GSBI4_QUP_SRC 140
#define GSBI4_QUP_CLK 141
#define GSBI5_QUP_SRC 142
#define GSBI5_QUP_CLK 143
#define GSBI6_QUP_SRC 144
#define GSBI6_QUP_CLK 145
#define GSBI7_QUP_SRC 146
#define GSBI7_QUP_CLK 147
#define GSBI1_UART_SRC 148
#define GSBI1_UART_CLK 149
#define GSBI2_UART_SRC 150
#define GSBI2_UART_CLK 151
#define GSBI3_UART_SRC 152
#define GSBI3_UART_CLK 153
#define GSBI4_UART_SRC 154
#define GSBI4_UART_CLK 155
#define GSBI5_UART_SRC 156
#define GSBI5_UART_CLK 157
#define GSBI6_UART_SRC 158
#define GSBI6_UART_CLK 159
#define GSBI7_UART_SRC 160
#define GSBI7_UART_CLK 161
#define GSBI1_SIM_CLK 162
#define GSBI2_SIM_CLK 163
#define GSBI3_SIM_CLK 164
#define GSBI4_SIM_CLK 165
#define GSBI5_SIM_CLK 166
#define GSBI6_SIM_CLK 167
#define GSBI7_SIM_CLK 168
#define USB_HSIC_HSIC_CLK_SRC 169
#define USB_HSIC_HSIC_CLK 170
#define USB_HSIC_HSIO_CAL_CLK 171
#define SPDM_CFG_H_CLK 172
#define SPDM_MSTR_H_CLK 173
#define SPDM_FF_CLK_SRC 174
#define SPDM_FF_CLK 175
#define SEC_CTRL_CLK 176
#define SEC_CTRL_ACC_CLK_SRC 177
#define SEC_CTRL_ACC_CLK 178
#define TLMM_H_CLK 179
#define TLMM_CLK 180
#define SATA_H_CLK 181
#define SATA_CLK_SRC 182
#define SATA_RXOOB_CLK 183
#define SATA_PMALIVE_CLK 184
#define SATA_PHY_REF_CLK 185
#define SATA_A_CLK 186
#define SATA_PHY_CFG_CLK 187
#define TSSC_CLK_SRC 188
#define TSSC_CLK 189
#define PDM_SRC 190
#define PDM_CLK 191
#define GP0_SRC 192
#define GP0_CLK 193
#define GP1_SRC 194
#define GP1_CLK 195
#define GP2_SRC 196
#define GP2_CLK 197
#define MPM_CLK 198
#define EBI1_CLK_SRC 199
#define EBI1_CH0_CLK 200
#define EBI1_CH1_CLK 201
#define EBI1_2X_CLK 202
#define EBI1_CH0_DQ_CLK 203
#define EBI1_CH1_DQ_CLK 204
#define EBI1_CH0_CA_CLK 205
#define EBI1_CH1_CA_CLK 206
#define EBI1_XO_CLK 207
#define SFAB_SMPSS_S_H_CLK 208
#define PRNG_SRC 209
#define PRNG_CLK 210
#define PXO_SRC 211
#define SPDM_CY_PORT0_CLK 212
#define SPDM_CY_PORT1_CLK 213
#define SPDM_CY_PORT2_CLK 214
#define SPDM_CY_PORT3_CLK 215
#define SPDM_CY_PORT4_CLK 216
#define SPDM_CY_PORT5_CLK 217
#define SPDM_CY_PORT6_CLK 218
#define SPDM_CY_PORT7_CLK 219
#define PLL0 220
#define PLL0_VOTE 221
#define PLL3 222
#define PLL3_VOTE 223
#define PLL4 224
#define PLL4_VOTE 225
#define PLL8 226
#define PLL8_VOTE 227
#define PLL9 228
#define PLL10 229
#define PLL11 230
#define PLL12 231
#define PLL14 232
#define PLL14_VOTE 233
#define PLL18 234
#define CE5_SRC 235
#define CE5_H_CLK 236
#define CE5_CORE_CLK 237
#define CE3_SLEEP_CLK 238
#define SFAB_AHB_S8_FCLK 239
#define SPDM_CY_PORT8_CLK 246
#define PCIE_ALT_REF_SRC 247
#define PCIE_ALT_REF_CLK 248
#define PCIE_1_A_CLK 249
#define PCIE_1_AUX_CLK 250
#define PCIE_1_H_CLK 251
#define PCIE_1_PHY_CLK 252
#define PCIE_1_ALT_REF_SRC 253
#define PCIE_1_ALT_REF_CLK 254
#define PCIE_2_A_CLK 255
#define PCIE_2_AUX_CLK 256
#define PCIE_2_H_CLK 257
#define PCIE_2_PHY_CLK 258
#define PCIE_2_ALT_REF_SRC 259
#define PCIE_2_ALT_REF_CLK 260
#define EBI2_CLK 261
#define USB30_SLEEP_CLK 262
#define USB30_UTMI_SRC 263
#define USB30_0_UTMI_CLK 264
#define USB30_1_UTMI_CLK 265
#define USB30_MASTER_SRC 266
#define USB30_0_MASTER_CLK 267
#define USB30_1_MASTER_CLK 268
#define GMAC_CORE1_CLK_SRC 269
#define GMAC_CORE2_CLK_SRC 270
#define GMAC_CORE3_CLK_SRC 271
#define GMAC_CORE4_CLK_SRC 272
#define GMAC_CORE1_CLK 273
#define GMAC_CORE2_CLK 274
#define GMAC_CORE3_CLK 275
#define GMAC_CORE4_CLK 276
#define UBI32_CORE1_CLK_SRC 277
#define UBI32_CORE2_CLK_SRC 278
#define UBI32_CORE1_CLK 279
#define UBI32_CORE2_CLK 280
#endif

11
include/dt-bindings/clock/qcom,gcc-msm8960.h
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@@ -308,5 +308,16 @@
#define PLL13 292
#define PLL14 293
#define PLL14_VOTE 294
#define USB_HS3_H_CLK 295
#define USB_HS3_XCVR_SRC 296
#define USB_HS3_XCVR_CLK 297
#define USB_HS4_H_CLK 298
#define USB_HS4_XCVR_SRC 299
#define USB_HS4_XCVR_CLK 300
#define SATA_PHY_CFG_CLK 301
#define SATA_A_CLK 302
#define CE3_SRC 303
#define CE3_CORE_CLK 304
#define CE3_H_CLK 305
#endif

183
include/dt-bindings/clock/qcom,mmcc-apq8084.h Normal file
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/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
#define MMSS_AHB_CLK_SRC 0
#define MMSS_AXI_CLK_SRC 1
#define MMPLL0 2
#define MMPLL0_VOTE 3
#define MMPLL1 4
#define MMPLL1_VOTE 5
#define MMPLL2 6
#define MMPLL3 7
#define MMPLL4 8
#define CSI0_CLK_SRC 9
#define CSI1_CLK_SRC 10
#define CSI2_CLK_SRC 11
#define CSI3_CLK_SRC 12
#define VCODEC0_CLK_SRC 13
#define VFE0_CLK_SRC 14
#define VFE1_CLK_SRC 15
#define MDP_CLK_SRC 16
#define PCLK0_CLK_SRC 17
#define PCLK1_CLK_SRC 18
#define OCMEMNOC_CLK_SRC 19
#define GFX3D_CLK_SRC 20
#define JPEG0_CLK_SRC 21
#define JPEG1_CLK_SRC 22
#define JPEG2_CLK_SRC 23
#define EDPPIXEL_CLK_SRC 24
#define EXTPCLK_CLK_SRC 25
#define VP_CLK_SRC 26
#define CCI_CLK_SRC 27
#define CAMSS_GP0_CLK_SRC 28
#define CAMSS_GP1_CLK_SRC 29
#define MCLK0_CLK_SRC 30
#define MCLK1_CLK_SRC 31
#define MCLK2_CLK_SRC 32
#define MCLK3_CLK_SRC 33
#define CSI0PHYTIMER_CLK_SRC 34
#define CSI1PHYTIMER_CLK_SRC 35
#define CSI2PHYTIMER_CLK_SRC 36
#define CPP_CLK_SRC 37
#define BYTE0_CLK_SRC 38
#define BYTE1_CLK_SRC 39
#define EDPAUX_CLK_SRC 40
#define EDPLINK_CLK_SRC 41
#define ESC0_CLK_SRC 42
#define ESC1_CLK_SRC 43
#define HDMI_CLK_SRC 44
#define VSYNC_CLK_SRC 45
#define RBCPR_CLK_SRC 46
#define RBBMTIMER_CLK_SRC 47
#define MAPLE_CLK_SRC 48
#define VDP_CLK_SRC 49
#define VPU_BUS_CLK_SRC 50
#define MMSS_CXO_CLK 51
#define MMSS_SLEEPCLK_CLK 52
#define AVSYNC_AHB_CLK 53
#define AVSYNC_EDPPIXEL_CLK 54
#define AVSYNC_EXTPCLK_CLK 55
#define AVSYNC_PCLK0_CLK 56
#define AVSYNC_PCLK1_CLK 57
#define AVSYNC_VP_CLK 58
#define CAMSS_AHB_CLK 59
#define CAMSS_CCI_CCI_AHB_CLK 60
#define CAMSS_CCI_CCI_CLK 61
#define CAMSS_CSI0_AHB_CLK 62
#define CAMSS_CSI0_CLK 63
#define CAMSS_CSI0PHY_CLK 64
#define CAMSS_CSI0PIX_CLK 65
#define CAMSS_CSI0RDI_CLK 66
#define CAMSS_CSI1_AHB_CLK 67
#define CAMSS_CSI1_CLK 68
#define CAMSS_CSI1PHY_CLK 69
#define CAMSS_CSI1PIX_CLK 70
#define CAMSS_CSI1RDI_CLK 71
#define CAMSS_CSI2_AHB_CLK 72
#define CAMSS_CSI2_CLK 73
#define CAMSS_CSI2PHY_CLK 74
#define CAMSS_CSI2PIX_CLK 75
#define CAMSS_CSI2RDI_CLK 76
#define CAMSS_CSI3_AHB_CLK 77
#define CAMSS_CSI3_CLK 78
#define CAMSS_CSI3PHY_CLK 79
#define CAMSS_CSI3PIX_CLK 80
#define CAMSS_CSI3RDI_CLK 81
#define CAMSS_CSI_VFE0_CLK 82
#define CAMSS_CSI_VFE1_CLK 83
#define CAMSS_GP0_CLK 84
#define CAMSS_GP1_CLK 85
#define CAMSS_ISPIF_AHB_CLK 86
#define CAMSS_JPEG_JPEG0_CLK 87
#define CAMSS_JPEG_JPEG1_CLK 88
#define CAMSS_JPEG_JPEG2_CLK 89
#define CAMSS_JPEG_JPEG_AHB_CLK 90
#define CAMSS_JPEG_JPEG_AXI_CLK 91
#define CAMSS_MCLK0_CLK 92
#define CAMSS_MCLK1_CLK 93
#define CAMSS_MCLK2_CLK 94
#define CAMSS_MCLK3_CLK 95
#define CAMSS_MICRO_AHB_CLK 96
#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97
#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98
#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99
#define CAMSS_TOP_AHB_CLK 100
#define CAMSS_VFE_CPP_AHB_CLK 101
#define CAMSS_VFE_CPP_CLK 102
#define CAMSS_VFE_VFE0_CLK 103
#define CAMSS_VFE_VFE1_CLK 104
#define CAMSS_VFE_VFE_AHB_CLK 105
#define CAMSS_VFE_VFE_AXI_CLK 106
#define MDSS_AHB_CLK 107
#define MDSS_AXI_CLK 108
#define MDSS_BYTE0_CLK 109
#define MDSS_BYTE1_CLK 110
#define MDSS_EDPAUX_CLK 111
#define MDSS_EDPLINK_CLK 112
#define MDSS_EDPPIXEL_CLK 113
#define MDSS_ESC0_CLK 114
#define MDSS_ESC1_CLK 115
#define MDSS_EXTPCLK_CLK 116
#define MDSS_HDMI_AHB_CLK 117
#define MDSS_HDMI_CLK 118
#define MDSS_MDP_CLK 119
#define MDSS_MDP_LUT_CLK 120
#define MDSS_PCLK0_CLK 121
#define MDSS_PCLK1_CLK 122
#define MDSS_VSYNC_CLK 123
#define MMSS_RBCPR_AHB_CLK 124
#define MMSS_RBCPR_CLK 125
#define MMSS_SPDM_AHB_CLK 126
#define MMSS_SPDM_AXI_CLK 127
#define MMSS_SPDM_CSI0_CLK 128
#define MMSS_SPDM_GFX3D_CLK 129
#define MMSS_SPDM_JPEG0_CLK 130
#define MMSS_SPDM_JPEG1_CLK 131
#define MMSS_SPDM_JPEG2_CLK 132
#define MMSS_SPDM_MDP_CLK 133
#define MMSS_SPDM_PCLK0_CLK 134
#define MMSS_SPDM_PCLK1_CLK 135
#define MMSS_SPDM_VCODEC0_CLK 136
#define MMSS_SPDM_VFE0_CLK 137
#define MMSS_SPDM_VFE1_CLK 138
#define MMSS_SPDM_RM_AXI_CLK 139
#define MMSS_SPDM_RM_OCMEMNOC_CLK 140
#define MMSS_MISC_AHB_CLK 141
#define MMSS_MMSSNOC_AHB_CLK 142
#define MMSS_MMSSNOC_BTO_AHB_CLK 143
#define MMSS_MMSSNOC_AXI_CLK 144
#define MMSS_S0_AXI_CLK 145
#define OCMEMCX_AHB_CLK 146
#define OCMEMCX_OCMEMNOC_CLK 147
#define OXILI_OCMEMGX_CLK 148
#define OXILI_GFX3D_CLK 149
#define OXILI_RBBMTIMER_CLK 150
#define OXILICX_AHB_CLK 151
#define VENUS0_AHB_CLK 152
#define VENUS0_AXI_CLK 153
#define VENUS0_CORE0_VCODEC_CLK 154
#define VENUS0_CORE1_VCODEC_CLK 155
#define VENUS0_OCMEMNOC_CLK 156
#define VENUS0_VCODEC0_CLK 157
#define VPU_AHB_CLK 158
#define VPU_AXI_CLK 159
#define VPU_BUS_CLK 160
#define VPU_CXO_CLK 161
#define VPU_MAPLE_CLK 162
#define VPU_SLEEP_CLK 163
#define VPU_VDP_CLK 164
#endif

8
include/dt-bindings/clock/qcom,mmcc-msm8960.h
View File

@@ -133,5 +133,13 @@
#define CSIPHY0_TIMER_CLK 116
#define PLL1 117
#define PLL2 118
#define RGB_TV_CLK 119
#define NPL_TV_CLK 120
#define VCAP_AHB_CLK 121
#define VCAP_AXI_CLK 122
#define VCAP_SRC 123
#define VCAP_CLK 124
#define VCAP_NPL_CLK 125
#define PLL15 126
#endif

27
include/dt-bindings/clock/r8a7790-clock.h
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@@ -59,6 +59,7 @@
#define R8A7790_CLK_SDHI0 14
#define R8A7790_CLK_MMCIF0 15
#define R8A7790_CLK_IIC0 18
#define R8A7790_CLK_PCIEC 19
#define R8A7790_CLK_IIC1 23
#define R8A7790_CLK_SSUSB 28
#define R8A7790_CLK_CMT1 29
@@ -107,4 +108,30 @@
#define R8A7790_CLK_I2C1 30
#define R8A7790_CLK_I2C0 31
/* MSTP10 */
#define R8A7790_CLK_SSI_ALL 5
#define R8A7790_CLK_SSI9 6
#define R8A7790_CLK_SSI8 7
#define R8A7790_CLK_SSI7 8
#define R8A7790_CLK_SSI6 9
#define R8A7790_CLK_SSI5 10
#define R8A7790_CLK_SSI4 11
#define R8A7790_CLK_SSI3 12
#define R8A7790_CLK_SSI2 13
#define R8A7790_CLK_SSI1 14
#define R8A7790_CLK_SSI0 15
#define R8A7790_CLK_SCU_ALL 17
#define R8A7790_CLK_SCU_DVC1 18
#define R8A7790_CLK_SCU_DVC0 19
#define R8A7790_CLK_SCU_SRC9 22
#define R8A7790_CLK_SCU_SRC8 23
#define R8A7790_CLK_SCU_SRC7 24
#define R8A7790_CLK_SCU_SRC6 25
#define R8A7790_CLK_SCU_SRC5 26
#define R8A7790_CLK_SCU_SRC4 27
#define R8A7790_CLK_SCU_SRC3 28
#define R8A7790_CLK_SCU_SRC2 29
#define R8A7790_CLK_SCU_SRC1 30
#define R8A7790_CLK_SCU_SRC0 31
#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */

27
include/dt-bindings/clock/r8a7791-clock.h
View File

@@ -53,6 +53,7 @@
#define R8A7791_CLK_SDHI0 14
#define R8A7791_CLK_MMCIF0 15
#define R8A7791_CLK_IIC0 18
#define R8A7791_CLK_PCIEC 19
#define R8A7791_CLK_IIC1 23
#define R8A7791_CLK_SSUSB 28
#define R8A7791_CLK_CMT1 29
@@ -107,6 +108,32 @@
#define R8A7791_CLK_I2C1 30
#define R8A7791_CLK_I2C0 31
/* MSTP10 */
#define R8A7791_CLK_SSI_ALL 5
#define R8A7791_CLK_SSI9 6
#define R8A7791_CLK_SSI8 7
#define R8A7791_CLK_SSI7 8
#define R8A7791_CLK_SSI6 9
#define R8A7791_CLK_SSI5 10
#define R8A7791_CLK_SSI4 11
#define R8A7791_CLK_SSI3 12
#define R8A7791_CLK_SSI2 13
#define R8A7791_CLK_SSI1 14
#define R8A7791_CLK_SSI0 15
#define R8A7791_CLK_SCU_ALL 17
#define R8A7791_CLK_SCU_DVC1 18
#define R8A7791_CLK_SCU_DVC0 19
#define R8A7791_CLK_SCU_SRC9 22
#define R8A7791_CLK_SCU_SRC8 23
#define R8A7791_CLK_SCU_SRC7 24
#define R8A7791_CLK_SCU_SRC6 25
#define R8A7791_CLK_SCU_SRC5 26
#define R8A7791_CLK_SCU_SRC4 27
#define R8A7791_CLK_SCU_SRC3 28
#define R8A7791_CLK_SCU_SRC2 29
#define R8A7791_CLK_SCU_SRC1 30
#define R8A7791_CLK_SCU_SRC0 31
/* MSTP11 */
#define R8A7791_CLK_SCIFA3 6
#define R8A7791_CLK_SCIFA4 7

35
include/dt-bindings/clock/rk3066a-cru.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/clock/rk3188-cru-common.h>
/* soft-reset indices */
#define SRST_SRST1 0
#define SRST_SRST2 1
#define SRST_L2MEM 18
#define SRST_I2S0 23
#define SRST_I2S1 24
#define SRST_I2S2 25
#define SRST_TIMER2 29
#define SRST_GPIO4 36
#define SRST_GPIO6 38
#define SRST_TSADC 92
#define SRST_HDMI 96
#define SRST_HDMI_APB 97
#define SRST_CIF1 111

249
include/dt-bindings/clock/rk3188-cru-common.h Normal file
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@@ -0,0 +1,249 @@
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* core clocks from */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_GPLL 4
#define CORE_PERI 5
#define CORE_L2C 6
/* sclk gates (special clocks) */
#define SCLK_UART0 64
#define SCLK_UART1 65
#define SCLK_UART2 66
#define SCLK_UART3 67
#define SCLK_MAC 68
#define SCLK_SPI0 69
#define SCLK_SPI1 70
#define SCLK_SARADC 71
#define SCLK_SDMMC 72
#define SCLK_SDIO 73
#define SCLK_EMMC 74
#define SCLK_I2S0 75
#define SCLK_I2S1 76
#define SCLK_I2S2 77
#define SCLK_SPDIF 78
#define SCLK_CIF0 79
#define SCLK_CIF1 80
#define SCLK_OTGPHY0 81
#define SCLK_OTGPHY1 82
#define SCLK_HSADC 83
#define SCLK_TIMER0 84
#define SCLK_TIMER1 85
#define SCLK_TIMER2 86
#define SCLK_TIMER3 87
#define SCLK_TIMER4 88
#define SCLK_TIMER5 89
#define SCLK_TIMER6 90
#define SCLK_JTAG 91
#define SCLK_SMC 92
#define DCLK_LCDC0 190
#define DCLK_LCDC1 191
/* aclk gates */
#define ACLK_DMA1 192
#define ACLK_DMA2 193
#define ACLK_GPS 194
#define ACLK_LCDC0 195
#define ACLK_LCDC1 196
#define ACLK_GPU 197
#define ACLK_SMC 198
#define ACLK_CIF 199
#define ACLK_IPP 200
#define ACLK_RGA 201
#define ACLK_CIF0 202
/* pclk gates */
#define PCLK_GRF 320
#define PCLK_PMU 321
#define PCLK_TIMER0 322
#define PCLK_TIMER1 323
#define PCLK_TIMER2 324
#define PCLK_TIMER3 325
#define PCLK_PWM01 326
#define PCLK_PWM23 327
#define PCLK_SPI0 328
#define PCLK_SPI1 329
#define PCLK_SARADC 330
#define PCLK_WDT 331
#define PCLK_UART0 332
#define PCLK_UART1 333
#define PCLK_UART2 334
#define PCLK_UART3 335
#define PCLK_I2C0 336
#define PCLK_I2C1 337
#define PCLK_I2C2 338
#define PCLK_I2C3 339
#define PCLK_I2C4 340
#define PCLK_GPIO0 341
#define PCLK_GPIO1 342
#define PCLK_GPIO2 343
#define PCLK_GPIO3 344
#define PCLK_GPIO4 345
#define PCLK_GPIO6 346
#define PCLK_EFUSE 347
#define PCLK_TZPC 348
#define PCLK_TSADC 349
/* hclk gates */
#define HCLK_SDMMC 448
#define HCLK_SDIO 449
#define HCLK_EMMC 450
#define HCLK_OTG0 451
#define HCLK_EMAC 452
#define HCLK_SPDIF 453
#define HCLK_I2S0 454
#define HCLK_I2S1 455
#define HCLK_I2S2 456
#define HCLK_OTG1 457
#define HCLK_HSIC 458
#define HCLK_HSADC 459
#define HCLK_PIDF 460
#define HCLK_LCDC0 461
#define HCLK_LCDC1 462
#define HCLK_ROM 463
#define HCLK_CIF0 464
#define HCLK_IPP 465
#define HCLK_RGA 466
#define HCLK_NANDC0 467
#define CLK_NR_CLKS (HCLK_NANDC0 + 1)
/* soft-reset indices */
#define SRST_MCORE 2
#define SRST_CORE0 3
#define SRST_CORE1 4
#define SRST_MCORE_DBG 7
#define SRST_CORE0_DBG 8
#define SRST_CORE1_DBG 9
#define SRST_CORE0_WDT 12
#define SRST_CORE1_WDT 13
#define SRST_STRC_SYS 14
#define SRST_L2C 15
#define SRST_CPU_AHB 17
#define SRST_AHB2APB 19
#define SRST_DMA1 20
#define SRST_INTMEM 21
#define SRST_ROM 22
#define SRST_SPDIF 26
#define SRST_TIMER0 27
#define SRST_TIMER1 28
#define SRST_EFUSE 30
#define SRST_GPIO0 32
#define SRST_GPIO1 33
#define SRST_GPIO2 34
#define SRST_GPIO3 35
#define SRST_UART0 39
#define SRST_UART1 40
#define SRST_UART2 41
#define SRST_UART3 42
#define SRST_I2C0 43
#define SRST_I2C1 44
#define SRST_I2C2 45
#define SRST_I2C3 46
#define SRST_I2C4 47
#define SRST_PWM0 48
#define SRST_PWM1 49
#define SRST_DAP_PO 50
#define SRST_DAP 51
#define SRST_DAP_SYS 52
#define SRST_TPIU_ATB 53
#define SRST_PMU_APB 54
#define SRST_GRF 55
#define SRST_PMU 56
#define SRST_PERI_AXI 57
#define SRST_PERI_AHB 58
#define SRST_PERI_APB 59
#define SRST_PERI_NIU 60
#define SRST_CPU_PERI 61
#define SRST_EMEM_PERI 62
#define SRST_USB_PERI 63
#define SRST_DMA2 64
#define SRST_SMC 65
#define SRST_MAC 66
#define SRST_NANC0 68
#define SRST_USBOTG0 69
#define SRST_USBPHY0 70
#define SRST_OTGC0 71
#define SRST_USBOTG1 72
#define SRST_USBPHY1 73
#define SRST_OTGC1 74
#define SRST_HSADC 76
#define SRST_PIDFILTER 77
#define SRST_DDR_MSCH 79
#define SRST_TZPC 80
#define SRST_SDMMC 81
#define SRST_SDIO 82
#define SRST_EMMC 83
#define SRST_SPI0 84
#define SRST_SPI1 85
#define SRST_WDT 86
#define SRST_SARADC 87
#define SRST_DDRPHY 88
#define SRST_DDRPHY_APB 89
#define SRST_DDRCTL 90
#define SRST_DDRCTL_APB 91
#define SRST_DDRPUB 93
#define SRST_VIO0_AXI 98
#define SRST_VIO0_AHB 99
#define SRST_LCDC0_AXI 100
#define SRST_LCDC0_AHB 101
#define SRST_LCDC0_DCLK 102
#define SRST_LCDC1_AXI 103
#define SRST_LCDC1_AHB 104
#define SRST_LCDC1_DCLK 105
#define SRST_IPP_AXI 106
#define SRST_IPP_AHB 107
#define SRST_RGA_AXI 108
#define SRST_RGA_AHB 109
#define SRST_CIF0 110
#define SRST_VCODEC_AXI 112
#define SRST_VCODEC_AHB 113
#define SRST_VIO1_AXI 114
#define SRST_VCODEC_CPU 115
#define SRST_VCODEC_NIU 116
#define SRST_GPU 120
#define SRST_GPU_NIU 122
#define SRST_TFUN_ATB 125
#define SRST_TFUN_APB 126
#define SRST_CTI4_APB 127
#define SRST_TPIU_APB 128
#define SRST_TRACE 129
#define SRST_CORE_DBG 130
#define SRST_DBG_APB 131
#define SRST_CTI0 132
#define SRST_CTI0_APB 133
#define SRST_CTI1 134
#define SRST_CTI1_APB 135
#define SRST_PTM_CORE0 136
#define SRST_PTM_CORE1 137
#define SRST_PTM0 138
#define SRST_PTM0_ATB 139
#define SRST_PTM1 140
#define SRST_PTM1_ATB 141
#define SRST_CTM 142
#define SRST_TS 143

51
include/dt-bindings/clock/rk3188-cru.h Normal file
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@@ -0,0 +1,51 @@
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/clock/rk3188-cru-common.h>
/* soft-reset indices */
#define SRST_PTM_CORE2 0
#define SRST_PTM_CORE3 1
#define SRST_CORE2 5
#define SRST_CORE3 6
#define SRST_CORE2_DBG 10
#define SRST_CORE3_DBG 11
#define SRST_TIMER2 16
#define SRST_TIMER4 23
#define SRST_I2S0 24
#define SRST_TIMER5 25
#define SRST_TIMER3 29
#define SRST_TIMER6 31
#define SRST_PTM3 36
#define SRST_PTM3_ATB 37
#define SRST_GPS 67
#define SRST_HSICPHY 75
#define SRST_TIMER 78
#define SRST_PTM2 92
#define SRST_CORE2_WDT 94
#define SRST_CORE3_WDT 95
#define SRST_PTM2_ATB 111
#define SRST_HSIC 117
#define SRST_CTI2 118
#define SRST_CTI2_APB 119
#define SRST_GPU_BRIDGE 121
#define SRST_CTI3 123
#define SRST_CTI3_APB 124

278
include/dt-bindings/clock/rk3288-cru.h Normal file
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@@ -0,0 +1,278 @@
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_GPLL 4
#define PLL_NPLL 5
/* sclk gates (special clocks) */
#define SCLK_GPU 64
#define SCLK_SPI0 65
#define SCLK_SPI1 66
#define SCLK_SPI2 67
#define SCLK_SDMMC 68
#define SCLK_SDIO0 69
#define SCLK_SDIO1 70
#define SCLK_EMMC 71
#define SCLK_TSADC 72
#define SCLK_SARADC 73
#define SCLK_PS2C 74
#define SCLK_NANDC0 75
#define SCLK_NANDC1 76
#define SCLK_UART0 77
#define SCLK_UART1 78
#define SCLK_UART2 79
#define SCLK_UART3 80
#define SCLK_UART4 81
#define SCLK_I2S0 82
#define SCLK_SPDIF 83
#define SCLK_SPDIF8CH 84
#define SCLK_TIMER0 85
#define SCLK_TIMER1 86
#define SCLK_TIMER2 87
#define SCLK_TIMER3 88
#define SCLK_TIMER4 89
#define SCLK_TIMER5 90
#define SCLK_TIMER6 91
#define SCLK_HSADC 92
#define SCLK_OTGPHY0 93
#define SCLK_OTGPHY1 94
#define SCLK_OTGPHY2 95
#define SCLK_OTG_ADP 96
#define SCLK_HSICPHY480M 97
#define SCLK_HSICPHY12M 98
#define SCLK_MACREF 99
#define SCLK_LCDC_PWM0 100
#define SCLK_LCDC_PWM1 101
#define SCLK_MAC_RX 102
#define SCLK_MAC_TX 103
#define DCLK_VOP0 190
#define DCLK_VOP1 191
/* aclk gates */
#define ACLK_GPU 192
#define ACLK_DMAC1 193
#define ACLK_DMAC2 194
#define ACLK_MMU 195
#define ACLK_GMAC 196
#define ACLK_VOP0 197
#define ACLK_VOP1 198
#define ACLK_CRYPTO 199
#define ACLK_RGA 200
/* pclk gates */
#define PCLK_GPIO0 320
#define PCLK_GPIO1 321
#define PCLK_GPIO2 322
#define PCLK_GPIO3 323
#define PCLK_GPIO4 324
#define PCLK_GPIO5 325
#define PCLK_GPIO6 326
#define PCLK_GPIO7 327
#define PCLK_GPIO8 328
#define PCLK_GRF 329
#define PCLK_SGRF 330
#define PCLK_PMU 331
#define PCLK_I2C0 332
#define PCLK_I2C1 333
#define PCLK_I2C2 334
#define PCLK_I2C3 335
#define PCLK_I2C4 336
#define PCLK_I2C5 337
#define PCLK_SPI0 338
#define PCLK_SPI1 339
#define PCLK_SPI2 340
#define PCLK_UART0 341
#define PCLK_UART1 342
#define PCLK_UART2 343
#define PCLK_UART3 344
#define PCLK_UART4 345
#define PCLK_TSADC 346
#define PCLK_SARADC 347
#define PCLK_SIM 348
#define PCLK_GMAC 349
#define PCLK_PWM 350
#define PCLK_RKPWM 351
#define PCLK_PS2C 352
#define PCLK_TIMER 353
#define PCLK_TZPC 354
/* hclk gates */
#define HCLK_GPS 448
#define HCLK_OTG0 449
#define HCLK_USBHOST0 450
#define HCLK_USBHOST1 451
#define HCLK_HSIC 452
#define HCLK_NANDC0 453
#define HCLK_NANDC1 454
#define HCLK_TSP 455
#define HCLK_SDMMC 456
#define HCLK_SDIO0 457
#define HCLK_SDIO1 458
#define HCLK_EMMC 459
#define HCLK_HSADC 460
#define HCLK_CRYPTO 461
#define HCLK_I2S0 462
#define HCLK_SPDIF 463
#define HCLK_SPDIF8CH 464
#define HCLK_VOP0 465
#define HCLK_VOP1 466
#define HCLK_ROM 467
#define HCLK_IEP 468
#define HCLK_ISP 469
#define HCLK_RGA 470
#define CLK_NR_CLKS (HCLK_RGA + 1)
/* soft-reset indices */
#define SRST_CORE0 0
#define SRST_CORE1 1
#define SRST_CORE2 2
#define SRST_CORE3 3
#define SRST_CORE0_PO 4
#define SRST_CORE1_PO 5
#define SRST_CORE2_PO 6
#define SRST_CORE3_PO 7
#define SRST_PDCORE_STRSYS 8
#define SRST_PDBUS_STRSYS 9
#define SRST_L2C 10
#define SRST_TOPDBG 11
#define SRST_CORE0_DBG 12
#define SRST_CORE1_DBG 13
#define SRST_CORE2_DBG 14
#define SRST_CORE3_DBG 15
#define SRST_PDBUG_AHB_ARBITOR 16
#define SRST_EFUSE256 17
#define SRST_DMAC1 18
#define SRST_INTMEM 19
#define SRST_ROM 20
#define SRST_SPDIF8CH 21
#define SRST_TIMER 22
#define SRST_I2S0 23
#define SRST_SPDIF 24
#define SRST_TIMER0 25
#define SRST_TIMER1 26
#define SRST_TIMER2 27
#define SRST_TIMER3 28
#define SRST_TIMER4 29
#define SRST_TIMER5 30
#define SRST_EFUSE 31
#define SRST_GPIO0 32
#define SRST_GPIO1 33
#define SRST_GPIO2 34
#define SRST_GPIO3 35
#define SRST_GPIO4 36
#define SRST_GPIO5 37
#define SRST_GPIO6 38
#define SRST_GPIO7 39
#define SRST_GPIO8 40
#define SRST_I2C0 42
#define SRST_I2C1 43
#define SRST_I2C2 44
#define SRST_I2C3 45
#define SRST_I2C4 46
#define SRST_I2C5 47
#define SRST_DWPWM 48
#define SRST_MMC_PERI 49
#define SRST_PERIPH_MMU 50
#define SRST_DAP 51
#define SRST_DAP_SYS 52
#define SRST_TPIU 53
#define SRST_PMU_APB 54
#define SRST_GRF 55
#define SRST_PMU 56
#define SRST_PERIPH_AXI 57
#define SRST_PERIPH_AHB 58
#define SRST_PERIPH_APB 59
#define SRST_PERIPH_NIU 60
#define SRST_PDPERI_AHB_ARBI 61
#define SRST_EMEM 62
#define SRST_USB_PERI 63
#define SRST_DMAC2 64
#define SRST_MAC 66
#define SRST_GPS 67
#define SRST_RKPWM 69
#define SRST_CCP 71
#define SRST_USBHOST0 72
#define SRST_HSIC 73
#define SRST_HSIC_AUX 74
#define SRST_HSIC_PHY 75
#define SRST_HSADC 76
#define SRST_NANDC0 77
#define SRST_NANDC1 78
#define SRST_TZPC 80
#define SRST_SPI0 83
#define SRST_SPI1 84
#define SRST_SPI2 85
#define SRST_SARADC 87
#define SRST_PDALIVE_NIU 88
#define SRST_PDPMU_INTMEM 89
#define SRST_PDPMU_NIU 90
#define SRST_SGRF 91
#define SRST_VIO_ARBI 96
#define SRST_RGA_NIU 97
#define SRST_VIO0_NIU_AXI 98
#define SRST_VIO_NIU_AHB 99
#define SRST_LCDC0_AXI 100
#define SRST_LCDC0_AHB 101
#define SRST_LCDC0_DCLK 102
#define SRST_VIO1_NIU_AXI 103
#define SRST_VIP 104
#define SRST_RGA_CORE 105
#define SRST_IEP_AXI 106
#define SRST_IEP_AHB 107
#define SRST_RGA_AXI 108
#define SRST_RGA_AHB 109
#define SRST_ISP 110
#define SRST_EDP 111
#define SRST_VCODEC_AXI 112
#define SRST_VCODEC_AHB 113
#define SRST_VIO_H2P 114
#define SRST_MIPIDSI0 115
#define SRST_MIPIDSI1 116
#define SRST_MIPICSI 117
#define SRST_LVDS_PHY 118
#define SRST_LVDS_CON 119
#define SRST_GPU 120
#define SRST_HDMI 121
#define SRST_CORE_PVTM 124
#define SRST_GPU_PVTM 125
#define SRST_MMC0 128
#define SRST_SDIO0 129
#define SRST_SDIO1 130
#define SRST_EMMC 131
#define SRST_USBOTG_AHB 132
#define SRST_USBOTG_PHY 133
#define SRST_USBOTG_CON 134
#define SRST_USBHOST0_AHB 135
#define SRST_USBHOST0_PHY 136
#define SRST_USBHOST0_CON 137
#define SRST_USBHOST1_AHB 138
#define SRST_USBHOST1_PHY 139
#define SRST_USBHOST1_CON 140
#define SRST_USB_ADP 141
#define SRST_ACC_EFUSE 142

34
include/dt-bindings/clock/s5pv210-audss.h Normal file
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@@ -0,0 +1,34 @@
/*
* Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This header provides constants for Samsung audio subsystem
* clock controller.
*
* The constants defined in this header are being used in dts
* and s5pv210 audss driver.
*/
#ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
#define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
#define CLK_MOUT_AUDSS 0
#define CLK_MOUT_I2S_A 1
#define CLK_DOUT_AUD_BUS 2
#define CLK_DOUT_I2S_A 3
#define CLK_I2S 4
#define CLK_HCLK_I2S 5
#define CLK_HCLK_UART 6
#define CLK_HCLK_HWA 7
#define CLK_HCLK_DMA 8
#define CLK_HCLK_BUF 9
#define CLK_HCLK_RP 10
#define AUDSS_MAX_CLKS 11
#endif

239
include/dt-bindings/clock/s5pv210.h Normal file
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@@ -0,0 +1,239 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Samsung S5PV210 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_S5PV210_H
#define _DT_BINDINGS_CLOCK_S5PV210_H
/* Core clocks. */
#define FIN_PLL 1
#define FOUT_APLL 2
#define FOUT_MPLL 3
#define FOUT_EPLL 4
#define FOUT_VPLL 5
/* Muxes. */
#define MOUT_FLASH 6
#define MOUT_PSYS 7
#define MOUT_DSYS 8
#define MOUT_MSYS 9
#define MOUT_VPLL 10
#define MOUT_EPLL 11
#define MOUT_MPLL 12
#define MOUT_APLL 13
#define MOUT_VPLLSRC 14
#define MOUT_CSIS 15
#define MOUT_FIMD 16
#define MOUT_CAM1 17
#define MOUT_CAM0 18
#define MOUT_DAC 19
#define MOUT_MIXER 20
#define MOUT_HDMI 21
#define MOUT_G2D 22
#define MOUT_MFC 23
#define MOUT_G3D 24
#define MOUT_FIMC2 25
#define MOUT_FIMC1 26
#define MOUT_FIMC0 27
#define MOUT_UART3 28
#define MOUT_UART2 29
#define MOUT_UART1 30
#define MOUT_UART0 31
#define MOUT_MMC3 32
#define MOUT_MMC2 33
#define MOUT_MMC1 34
#define MOUT_MMC0 35
#define MOUT_PWM 36
#define MOUT_SPI0 37
#define MOUT_SPI1 38
#define MOUT_DMC0 39
#define MOUT_PWI 40
#define MOUT_HPM 41
#define MOUT_SPDIF 42
#define MOUT_AUDIO2 43
#define MOUT_AUDIO1 44
#define MOUT_AUDIO0 45
/* Dividers. */
#define DOUT_PCLKP 46
#define DOUT_HCLKP 47
#define DOUT_PCLKD 48
#define DOUT_HCLKD 49
#define DOUT_PCLKM 50
#define DOUT_HCLKM 51
#define DOUT_A2M 52
#define DOUT_APLL 53
#define DOUT_CSIS 54
#define DOUT_FIMD 55
#define DOUT_CAM1 56
#define DOUT_CAM0 57
#define DOUT_TBLK 58
#define DOUT_G2D 59
#define DOUT_MFC 60
#define DOUT_G3D 61
#define DOUT_FIMC2 62
#define DOUT_FIMC1 63
#define DOUT_FIMC0 64
#define DOUT_UART3 65
#define DOUT_UART2 66
#define DOUT_UART1 67
#define DOUT_UART0 68
#define DOUT_MMC3 69
#define DOUT_MMC2 70
#define DOUT_MMC1 71
#define DOUT_MMC0 72
#define DOUT_PWM 73
#define DOUT_SPI1 74
#define DOUT_SPI0 75
#define DOUT_DMC0 76
#define DOUT_PWI 77
#define DOUT_HPM 78
#define DOUT_COPY 79
#define DOUT_FLASH 80
#define DOUT_AUDIO2 81
#define DOUT_AUDIO1 82
#define DOUT_AUDIO0 83
#define DOUT_DPM 84
#define DOUT_DVSEM 85
/* Gates */
#define SCLK_FIMC 86
#define CLK_CSIS 87
#define CLK_ROTATOR 88
#define CLK_FIMC2 89
#define CLK_FIMC1 90
#define CLK_FIMC0 91
#define CLK_MFC 92
#define CLK_G2D 93
#define CLK_G3D 94
#define CLK_IMEM 95
#define CLK_PDMA1 96
#define CLK_PDMA0 97
#define CLK_MDMA 98
#define CLK_DMC1 99
#define CLK_DMC0 100
#define CLK_NFCON 101
#define CLK_SROMC 102
#define CLK_CFCON 103
#define CLK_NANDXL 104
#define CLK_USB_HOST 105
#define CLK_USB_OTG 106
#define CLK_HDMI 107
#define CLK_TVENC 108
#define CLK_MIXER 109
#define CLK_VP 110
#define CLK_DSIM 111
#define CLK_FIMD 112
#define CLK_TZIC3 113
#define CLK_TZIC2 114
#define CLK_TZIC1 115
#define CLK_TZIC0 116
#define CLK_VIC3 117
#define CLK_VIC2 118
#define CLK_VIC1 119
#define CLK_VIC0 120
#define CLK_TSI 121
#define CLK_HSMMC3 122
#define CLK_HSMMC2 123
#define CLK_HSMMC1 124
#define CLK_HSMMC0 125
#define CLK_JTAG 126
#define CLK_MODEMIF 127
#define CLK_CORESIGHT 128
#define CLK_SDM 129
#define CLK_SECSS 130
#define CLK_PCM2 131
#define CLK_PCM1 132
#define CLK_PCM0 133
#define CLK_SYSCON 134
#define CLK_GPIO 135
#define CLK_TSADC 136
#define CLK_PWM 137
#define CLK_WDT 138
#define CLK_KEYIF 139
#define CLK_UART3 140
#define CLK_UART2 141
#define CLK_UART1 142
#define CLK_UART0 143
#define CLK_SYSTIMER 144
#define CLK_RTC 145
#define CLK_SPI1 146
#define CLK_SPI0 147
#define CLK_I2C_HDMI_PHY 148
#define CLK_I2C1 149
#define CLK_I2C2 150
#define CLK_I2C0 151
#define CLK_I2S1 152
#define CLK_I2S2 153
#define CLK_I2S0 154
#define CLK_AC97 155
#define CLK_SPDIF 156
#define CLK_TZPC3 157
#define CLK_TZPC2 158
#define CLK_TZPC1 159
#define CLK_TZPC0 160
#define CLK_SECKEY 161
#define CLK_IEM_APC 162
#define CLK_IEM_IEC 163
#define CLK_CHIPID 164
#define CLK_JPEG 163
/* Special clocks*/
#define SCLK_PWI 164
#define SCLK_SPDIF 165
#define SCLK_AUDIO2 166
#define SCLK_AUDIO1 167
#define SCLK_AUDIO0 168
#define SCLK_PWM 169
#define SCLK_SPI1 170
#define SCLK_SPI0 171
#define SCLK_UART3 172
#define SCLK_UART2 173
#define SCLK_UART1 174
#define SCLK_UART0 175
#define SCLK_MMC3 176
#define SCLK_MMC2 177
#define SCLK_MMC1 178
#define SCLK_MMC0 179
#define SCLK_FINVPLL 180
#define SCLK_CSIS 181
#define SCLK_FIMD 182
#define SCLK_CAM1 183
#define SCLK_CAM0 184
#define SCLK_DAC 185
#define SCLK_MIXER 186
#define SCLK_HDMI 187
#define SCLK_FIMC2 188
#define SCLK_FIMC1 189
#define SCLK_FIMC0 190
#define SCLK_HDMI27M 191
#define SCLK_HDMIPHY 192
#define SCLK_USBPHY0 193
#define SCLK_USBPHY1 194
/* S5P6442-specific clocks */
#define MOUT_D0SYNC 195
#define MOUT_D1SYNC 196
#define DOUT_MIXER 197
#define CLK_ETB 198
#define CLK_ETM 199
/* CLKOUT */
#define FOUT_APLL_CLKOUT 200
#define FOUT_MPLL_CLKOUT 201
#define DOUT_APLL_CLKOUT 202
#define MOUT_CLKSEL 203
#define DOUT_CLKOUT 204
#define MOUT_CLKOUT 205
/* Total number of clocks. */
#define NR_CLKS 206
#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */

4
include/dt-bindings/clock/vf610-clock.h
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@@ -164,6 +164,8 @@
#define VF610_CLK_DMAMUX1 151
#define VF610_CLK_DMAMUX2 152
#define VF610_CLK_DMAMUX3 153
#define VF610_CLK_END 154
#define VF610_CLK_FLEXCAN0_EN 154
#define VF610_CLK_FLEXCAN1_EN 155
#define VF610_CLK_END 156
#endif /* __DT_BINDINGS_CLOCK_VF610_H */

20
include/dt-bindings/dma/nbpfaxi.h Normal file
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@@ -0,0 +1,20 @@
/*
* Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
* Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*/
#ifndef DT_BINDINGS_NBPFAXI_H
#define DT_BINDINGS_NBPFAXI_H
/**
* Use "#dma-cells = <2>;" with the second integer defining slave DMA flags:
*/
#define NBPF_SLAVE_RQ_HIGH 1
#define NBPF_SLAVE_RQ_LOW 2
#define NBPF_SLAVE_RQ_LEVEL 4
#endif

2
include/dt-bindings/mfd/as3722.h
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@@ -13,7 +13,7 @@
/* External control pins */
#define AS3722_EXT_CONTROL_PIN_ENABLE1 1
#define AS3722_EXT_CONTROL_PIN_ENABLE2 2
#define AS3722_EXT_CONTROL_PIN_ENABLE2 3
#define AS3722_EXT_CONTROL_PIN_ENABLE3 3
/* Interrupt numbers for AS3722 */
#define AS3722_IRQ_LID 0

18
include/dt-bindings/mfd/palmas.h Normal file
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@@ -0,0 +1,18 @@
/*
* This header provides macros for Palmas device bindings.
*
* Copyright (c) 2013, NVIDIA Corporation.
*
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*
*/
#ifndef __DT_BINDINGS_PALMAS_H__
#define __DT_BINDINGS_PALMAS_H
/* External control pins */
#define PALMAS_EXT_CONTROL_PIN_ENABLE1 1
#define PALMAS_EXT_CONTROL_PIN_ENABLE2 2
#define PALMAS_EXT_CONTROL_PIN_NSLEEP 3
#endif /* __DT_BINDINGS_PALMAS_H */

14
include/dt-bindings/phy/phy-miphy365x.h Normal file
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@@ -0,0 +1,14 @@
/*
* This header provides constants for the phy framework
* based on the STMicroelectronics MiPHY365x.
*
* Author: Lee Jones <lee.jones@linaro.org>
*/
#ifndef _DT_BINDINGS_PHY_MIPHY
#define _DT_BINDINGS_PHY_MIPHY
#define MIPHY_TYPE_SATA 1
#define MIPHY_TYPE_PCIE 2
#define MIPHY_TYPE_USB 3
#endif /* _DT_BINDINGS_PHY_MIPHY */

7
include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h Normal file
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@@ -0,0 +1,7 @@
#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H
#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1
#define TEGRA_XUSB_PADCTL_PCIE 0
#define TEGRA_XUSB_PADCTL_SATA 1
#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */

109
include/dt-bindings/reset/qcom,gcc-apq8084.h Normal file
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@@ -0,0 +1,109 @@
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H
#define _DT_BINDINGS_RESET_APQ_GCC_8084_H
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1
#define GCC_PERIPH_NOC_BCR 2
#define GCC_IMEM_BCR 3
#define GCC_MMSS_BCR 4
#define GCC_QDSS_BCR 5
#define GCC_USB_30_BCR 6
#define GCC_USB3_PHY_BCR 7
#define GCC_USB_HS_HSIC_BCR 8
#define GCC_USB_HS_BCR 9
#define GCC_USB2A_PHY_BCR 10
#define GCC_USB2B_PHY_BCR 11
#define GCC_SDCC1_BCR 12
#define GCC_SDCC2_BCR 13
#define GCC_SDCC3_BCR 14
#define GCC_SDCC4_BCR 15
#define GCC_BLSP1_BCR 16
#define GCC_BLSP1_QUP1_BCR 17
#define GCC_BLSP1_UART1_BCR 18
#define GCC_BLSP1_QUP2_BCR 19
#define GCC_BLSP1_UART2_BCR 20
#define GCC_BLSP1_QUP3_BCR 21
#define GCC_BLSP1_UART3_BCR 22
#define GCC_BLSP1_QUP4_BCR 23
#define GCC_BLSP1_UART4_BCR 24
#define GCC_BLSP1_QUP5_BCR 25
#define GCC_BLSP1_UART5_BCR 26
#define GCC_BLSP1_QUP6_BCR 27
#define GCC_BLSP1_UART6_BCR 28
#define GCC_BLSP2_BCR 29
#define GCC_BLSP2_QUP1_BCR 30
#define GCC_BLSP2_UART1_BCR 31
#define GCC_BLSP2_QUP2_BCR 32
#define GCC_BLSP2_UART2_BCR 33
#define GCC_BLSP2_QUP3_BCR 34
#define GCC_BLSP2_UART3_BCR 35
#define GCC_BLSP2_QUP4_BCR 36
#define GCC_BLSP2_UART4_BCR 37
#define GCC_BLSP2_QUP5_BCR 38
#define GCC_BLSP2_UART5_BCR 39
#define GCC_BLSP2_QUP6_BCR 40
#define GCC_BLSP2_UART6_BCR 41
#define GCC_PDM_BCR 42
#define GCC_PRNG_BCR 43
#define GCC_BAM_DMA_BCR 44
#define GCC_TSIF_BCR 45
#define GCC_TCSR_BCR 46
#define GCC_BOOT_ROM_BCR 47
#define GCC_MSG_RAM_BCR 48
#define GCC_TLMM_BCR 49
#define GCC_MPM_BCR 50
#define GCC_MPM_AHB_RESET 51
#define GCC_MPM_NON_AHB_RESET 52
#define GCC_SEC_CTRL_BCR 53
#define GCC_SPMI_BCR 54
#define GCC_SPDM_BCR 55
#define GCC_CE1_BCR 56
#define GCC_CE2_BCR 57
#define GCC_BIMC_BCR 58
#define GCC_SNOC_BUS_TIMEOUT0_BCR 59
#define GCC_SNOC_BUS_TIMEOUT2_BCR 60
#define GCC_PNOC_BUS_TIMEOUT0_BCR 61
#define GCC_PNOC_BUS_TIMEOUT1_BCR 62
#define GCC_PNOC_BUS_TIMEOUT2_BCR 63
#define GCC_PNOC_BUS_TIMEOUT3_BCR 64
#define GCC_PNOC_BUS_TIMEOUT4_BCR 65
#define GCC_CNOC_BUS_TIMEOUT0_BCR 66
#define GCC_CNOC_BUS_TIMEOUT1_BCR 67
#define GCC_CNOC_BUS_TIMEOUT2_BCR 68
#define GCC_CNOC_BUS_TIMEOUT3_BCR 69
#define GCC_CNOC_BUS_TIMEOUT4_BCR 70
#define GCC_CNOC_BUS_TIMEOUT5_BCR 71
#define GCC_CNOC_BUS_TIMEOUT6_BCR 72
#define GCC_DEHR_BCR 73
#define GCC_RBCPR_BCR 74
#define GCC_MSS_RESTART 75
#define GCC_LPASS_RESTART 76
#define GCC_WCSS_RESTART 77
#define GCC_VENUS_RESTART 78
#define GCC_COPSS_SMMU_BCR 79
#define GCC_SPSS_BCR 80
#define GCC_PCIE_0_BCR 81
#define GCC_PCIE_0_PHY_BCR 82
#define GCC_PCIE_1_BCR 83
#define GCC_PCIE_1_PHY_BCR 84
#define GCC_USB_30_SEC_BCR 85
#define GCC_USB3_SEC_PHY_BCR 86
#define GCC_SATA_BCR 87
#define GCC_CE3_BCR 88
#define GCC_UFS_BCR 89
#define GCC_USB30_PHY_COM_BCR 90
#endif

132
include/dt-bindings/reset/qcom,gcc-ipq806x.h Normal file
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@@ -0,0 +1,132 @@
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_RESET_IPQ_806X_H
#define _DT_BINDINGS_RESET_IPQ_806X_H
#define QDSS_STM_RESET 0
#define AFAB_SMPSS_S_RESET 1
#define AFAB_SMPSS_M1_RESET 2
#define AFAB_SMPSS_M0_RESET 3
#define AFAB_EBI1_CH0_RESET 4
#define AFAB_EBI1_CH1_RESET 5
#define SFAB_ADM0_M0_RESET 6
#define SFAB_ADM0_M1_RESET 7
#define SFAB_ADM0_M2_RESET 8
#define ADM0_C2_RESET 9
#define ADM0_C1_RESET 10
#define ADM0_C0_RESET 11
#define ADM0_PBUS_RESET 12
#define ADM0_RESET 13
#define QDSS_CLKS_SW_RESET 14
#define QDSS_POR_RESET 15
#define QDSS_TSCTR_RESET 16
#define QDSS_HRESET_RESET 17
#define QDSS_AXI_RESET 18
#define QDSS_DBG_RESET 19
#define SFAB_PCIE_M_RESET 20
#define SFAB_PCIE_S_RESET 21
#define PCIE_EXT_RESET 22
#define PCIE_PHY_RESET 23
#define PCIE_PCI_RESET 24
#define PCIE_POR_RESET 25
#define PCIE_HCLK_RESET 26
#define PCIE_ACLK_RESET 27
#define SFAB_LPASS_RESET 28
#define SFAB_AFAB_M_RESET 29
#define AFAB_SFAB_M0_RESET 30
#define AFAB_SFAB_M1_RESET 31
#define SFAB_SATA_S_RESET 32
#define SFAB_DFAB_M_RESET 33
#define DFAB_SFAB_M_RESET 34
#define DFAB_SWAY0_RESET 35
#define DFAB_SWAY1_RESET 36
#define DFAB_ARB0_RESET 37
#define DFAB_ARB1_RESET 38
#define PPSS_PROC_RESET 39
#define PPSS_RESET 40
#define DMA_BAM_RESET 41
#define SPS_TIC_H_RESET 42
#define SFAB_CFPB_M_RESET 43
#define SFAB_CFPB_S_RESET 44
#define TSIF_H_RESET 45
#define CE1_H_RESET 46
#define CE1_CORE_RESET 47
#define CE1_SLEEP_RESET 48
#define CE2_H_RESET 49
#define CE2_CORE_RESET 50
#define SFAB_SFPB_M_RESET 51
#define SFAB_SFPB_S_RESET 52
#define RPM_PROC_RESET 53
#define PMIC_SSBI2_RESET 54
#define SDC1_RESET 55
#define SDC2_RESET 56
#define SDC3_RESET 57
#define SDC4_RESET 58
#define USB_HS1_RESET 59
#define USB_HSIC_RESET 60
#define USB_FS1_XCVR_RESET 61
#define USB_FS1_RESET 62
#define GSBI1_RESET 63
#define GSBI2_RESET 64
#define GSBI3_RESET 65
#define GSBI4_RESET 66
#define GSBI5_RESET 67
#define GSBI6_RESET 68
#define GSBI7_RESET 69
#define SPDM_RESET 70
#define SEC_CTRL_RESET 71
#define TLMM_H_RESET 72
#define SFAB_SATA_M_RESET 73
#define SATA_RESET 74
#define TSSC_RESET 75
#define PDM_RESET 76
#define MPM_H_RESET 77
#define MPM_RESET 78
#define SFAB_SMPSS_S_RESET 79
#define PRNG_RESET 80
#define SFAB_CE3_M_RESET 81
#define SFAB_CE3_S_RESET 82
#define CE3_SLEEP_RESET 83
#define PCIE_1_M_RESET 84
#define PCIE_1_S_RESET 85
#define PCIE_1_EXT_RESET 86
#define PCIE_1_PHY_RESET 87
#define PCIE_1_PCI_RESET 88
#define PCIE_1_POR_RESET 89
#define PCIE_1_HCLK_RESET 90
#define PCIE_1_ACLK_RESET 91
#define PCIE_2_M_RESET 92
#define PCIE_2_S_RESET 93
#define PCIE_2_EXT_RESET 94
#define PCIE_2_PHY_RESET 95
#define PCIE_2_PCI_RESET 96
#define PCIE_2_POR_RESET 97
#define PCIE_2_HCLK_RESET 98
#define PCIE_2_ACLK_RESET 99
#define SFAB_USB30_S_RESET 100
#define SFAB_USB30_M_RESET 101
#define USB30_0_PORT2_HS_PHY_RESET 102
#define USB30_0_MASTER_RESET 103
#define USB30_0_SLEEP_RESET 104
#define USB30_0_UTMI_PHY_RESET 105
#define USB30_0_POWERON_RESET 106
#define USB30_0_PHY_RESET 107
#define USB30_1_MASTER_RESET 108
#define USB30_1_SLEEP_RESET 109
#define USB30_1_UTMI_PHY_RESET 110
#define USB30_1_POWERON_RESET 111
#define USB30_1_PHY_RESET 112
#define NSSFB0_RESET 113
#define NSSFB1_RESET 114
#endif

16
include/dt-bindings/reset/qcom,gcc-msm8960.h
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@@ -114,5 +114,21 @@
#define SFAB_SMPSS_S_RESET 97
#define PRNG_RESET 98
#define RIVA_RESET 99
#define USB_HS3_RESET 100
#define USB_HS4_RESET 101
#define CE3_RESET 102
#define PCIE_EXT_PCI_RESET 103
#define PCIE_PHY_RESET 104
#define PCIE_PCI_RESET 105
#define PCIE_POR_RESET 106
#define PCIE_HCLK_RESET 107
#define PCIE_ACLK_RESET 108
#define CE3_H_RESET 109
#define SFAB_CE3_M_RESET 110
#define SFAB_CE3_S_RESET 111
#define SATA_RESET 112
#define CE3_SLEEP_RESET 113
#define GSS_SLP_RESET 114
#define GSS_RESET 115
#endif

64
include/dt-bindings/reset/qcom,mmcc-apq8084.h Normal file
View File

@@ -0,0 +1,64 @@
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H
#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H
#define MMSS_SPDM_RESET 0
#define MMSS_SPDM_RM_RESET 1
#define VENUS0_RESET 2
#define VPU_RESET 3
#define MDSS_RESET 4
#define AVSYNC_RESET 5
#define CAMSS_PHY0_RESET 6
#define CAMSS_PHY1_RESET 7
#define CAMSS_PHY2_RESET 8
#define CAMSS_CSI0_RESET 9
#define CAMSS_CSI0PHY_RESET 10
#define CAMSS_CSI0RDI_RESET 11
#define CAMSS_CSI0PIX_RESET 12
#define CAMSS_CSI1_RESET 13
#define CAMSS_CSI1PHY_RESET 14
#define CAMSS_CSI1RDI_RESET 15
#define CAMSS_CSI1PIX_RESET 16
#define CAMSS_CSI2_RESET 17
#define CAMSS_CSI2PHY_RESET 18
#define CAMSS_CSI2RDI_RESET 19
#define CAMSS_CSI2PIX_RESET 20
#define CAMSS_CSI3_RESET 21
#define CAMSS_CSI3PHY_RESET 22
#define CAMSS_CSI3RDI_RESET 23
#define CAMSS_CSI3PIX_RESET 24
#define CAMSS_ISPIF_RESET 25
#define CAMSS_CCI_RESET 26
#define CAMSS_MCLK0_RESET 27
#define CAMSS_MCLK1_RESET 28
#define CAMSS_MCLK2_RESET 29
#define CAMSS_MCLK3_RESET 30
#define CAMSS_GP0_RESET 31
#define CAMSS_GP1_RESET 32
#define CAMSS_TOP_RESET 33
#define CAMSS_AHB_RESET 34
#define CAMSS_MICRO_RESET 35
#define CAMSS_JPEG_RESET 36
#define CAMSS_VFE_RESET 37
#define CAMSS_CSI_VFE0_RESET 38
#define CAMSS_CSI_VFE1_RESET 39
#define OXILI_RESET 40
#define OXILICX_RESET 41
#define OCMEMCX_RESET 42
#define MMSS_RBCRP_RESET 43
#define MMSSNOCAHB_RESET 44
#define MMSSNOCAXI_RESET 45
#endif

8
include/dt-bindings/reset/qcom,mmcc-msm8960.h
View File

@@ -89,5 +89,13 @@
#define CSI2_RESET 72
#define CSI_RDI1_RESET 73
#define CSI_RDI2_RESET 74
#define GFX3D_AXI_RESET 75
#define VCAP_AXI_RESET 76
#define SMMU_VCAP_AHB_RESET 77
#define VCAP_AHB_RESET 78
#define CSI_RDI_RESET 79
#define CSI_PIX_RESET 80
#define VCAP_NPL_RESET 81
#define VCAP_RESET 82
#endif

14
include/kvm/arm_arch_timer.h
View File

@@ -67,6 +67,10 @@ void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
u64 kvm_arm_timer_get_reg(struct kvm_vcpu *, u64 regid);
int kvm_arm_timer_set_reg(struct kvm_vcpu *, u64 regid, u64 value);
#else
static inline int kvm_timer_hyp_init(void)
{
@@ -84,6 +88,16 @@ static inline void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) {}
static inline void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) {}
static inline int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value)
{
return 0;
}
static inline u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid)
{
return 0;
}
#endif
#endif

115
include/kvm/arm_vgic.h
View File

@@ -24,7 +24,6 @@
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/irqchip/arm-gic.h>
#define VGIC_NR_IRQS 256
#define VGIC_NR_SGIS 16
@@ -32,7 +31,9 @@
#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
#define VGIC_MAX_CPUS KVM_MAX_VCPUS
#define VGIC_MAX_LRS (1 << 6)
#define VGIC_V2_MAX_LRS (1 << 6)
#define VGIC_V3_MAX_LRS 16
/* Sanity checks... */
#if (VGIC_MAX_CPUS > 8)
@@ -68,9 +69,62 @@ struct vgic_bytemap {
u32 shared[VGIC_NR_SHARED_IRQS / 4];
};
struct kvm_vcpu;
enum vgic_type {
VGIC_V2, /* Good ol' GICv2 */
VGIC_V3, /* New fancy GICv3 */
};
#define LR_STATE_PENDING (1 << 0)
#define LR_STATE_ACTIVE (1 << 1)
#define LR_STATE_MASK (3 << 0)
#define LR_EOI_INT (1 << 2)
struct vgic_lr {
u16 irq;
u8 source;
u8 state;
};
struct vgic_vmcr {
u32 ctlr;
u32 abpr;
u32 bpr;
u32 pmr;
};
struct vgic_ops {
struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
void (*enable_underflow)(struct kvm_vcpu *vcpu);
void (*disable_underflow)(struct kvm_vcpu *vcpu);
void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void (*enable)(struct kvm_vcpu *vcpu);
};
struct vgic_params {
/* vgic type */
enum vgic_type type;
/* Physical address of vgic virtual cpu interface */
phys_addr_t vcpu_base;
/* Number of list registers */
u32 nr_lr;
/* Interrupt number */
unsigned int maint_irq;
/* Virtual control interface base address */
void __iomem *vctrl_base;
};
struct vgic_dist {
#ifdef CONFIG_KVM_ARM_VGIC
spinlock_t lock;
bool in_kernel;
bool ready;
/* Virtual control interface mapping */
@@ -110,6 +164,29 @@ struct vgic_dist {
#endif
};
struct vgic_v2_cpu_if {
u32 vgic_hcr;
u32 vgic_vmcr;
u32 vgic_misr; /* Saved only */
u32 vgic_eisr[2]; /* Saved only */
u32 vgic_elrsr[2]; /* Saved only */
u32 vgic_apr;
u32 vgic_lr[VGIC_V2_MAX_LRS];
};
struct vgic_v3_cpu_if {
#ifdef CONFIG_ARM_GIC_V3
u32 vgic_hcr;
u32 vgic_vmcr;
u32 vgic_misr; /* Saved only */
u32 vgic_eisr; /* Saved only */
u32 vgic_elrsr; /* Saved only */
u32 vgic_ap0r[4];
u32 vgic_ap1r[4];
u64 vgic_lr[VGIC_V3_MAX_LRS];
#endif
};
struct vgic_cpu {
#ifdef CONFIG_KVM_ARM_VGIC
/* per IRQ to LR mapping */
@@ -120,24 +197,24 @@ struct vgic_cpu {
DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
/* Bitmap of used/free list registers */
DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
/* Number of list registers on this CPU */
int nr_lr;
/* CPU vif control registers for world switch */
u32 vgic_hcr;
u32 vgic_vmcr;
u32 vgic_misr; /* Saved only */
u32 vgic_eisr[2]; /* Saved only */
u32 vgic_elrsr[2]; /* Saved only */
u32 vgic_apr;
u32 vgic_lr[VGIC_MAX_LRS];
union {
struct vgic_v2_cpu_if vgic_v2;
struct vgic_v3_cpu_if vgic_v3;
};
#endif
};
#define LR_EMPTY 0xff
#define INT_STATUS_EOI (1 << 0)
#define INT_STATUS_UNDERFLOW (1 << 1)
struct kvm;
struct kvm_vcpu;
struct kvm_run;
@@ -157,9 +234,25 @@ int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
struct kvm_exit_mmio *mmio);
#define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base))
#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k) ((k)->arch.vgic.ready)
int vgic_v2_probe(struct device_node *vgic_node,
const struct vgic_ops **ops,
const struct vgic_params **params);
#ifdef CONFIG_ARM_GIC_V3
int vgic_v3_probe(struct device_node *vgic_node,
const struct vgic_ops **ops,
const struct vgic_params **params);
#else
static inline int vgic_v3_probe(struct device_node *vgic_node,
const struct vgic_ops **ops,
const struct vgic_params **params)
{
return -ENODEV;
}
#endif
#else
static inline int kvm_vgic_hyp_init(void)
{

4
include/linux/acct.h
View File

@@ -24,14 +24,10 @@ struct super_block;
struct pacct_struct;
struct pid_namespace;
extern int acct_parm[]; /* for sysctl */
extern void acct_auto_close_mnt(struct vfsmount *m);
extern void acct_auto_close(struct super_block *sb);
extern void acct_collect(long exitcode, int group_dead);
extern void acct_process(void);
extern void acct_exit_ns(struct pid_namespace *);
#else
#define acct_auto_close_mnt(x) do { } while (0)
#define acct_auto_close(x) do { } while (0)
#define acct_collect(x,y) do { } while (0)
#define acct_process() do { } while (0)
#define acct_exit_ns(ns) do { } while (0)

17
include/linux/acpi.h
View File

@@ -29,17 +29,17 @@
#include <linux/ioport.h> /* for struct resource */
#include <linux/device.h>
#ifdef CONFIG_ACPI
#ifndef _LINUX
#define _LINUX
#endif
#include <acpi/acpi.h>
#ifdef CONFIG_ACPI
#include <linux/list.h>
#include <linux/mod_devicetable.h>
#include <linux/dynamic_debug.h>
#include <acpi/acpi.h>
#include <acpi/acpi_bus.h>
#include <acpi/acpi_drivers.h>
#include <acpi/acpi_numa.h>
@@ -364,6 +364,17 @@ extern bool osc_sb_apei_support_acked;
#define OSC_PCI_EXPRESS_CAPABILITY_CONTROL 0x00000010
#define OSC_PCI_CONTROL_MASKS 0x0000001f
#define ACPI_GSB_ACCESS_ATTRIB_QUICK 0x00000002
#define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV 0x00000004
#define ACPI_GSB_ACCESS_ATTRIB_BYTE 0x00000006
#define ACPI_GSB_ACCESS_ATTRIB_WORD 0x00000008
#define ACPI_GSB_ACCESS_ATTRIB_BLOCK 0x0000000A
#define ACPI_GSB_ACCESS_ATTRIB_MULTIBYTE 0x0000000B
#define ACPI_GSB_ACCESS_ATTRIB_WORD_CALL 0x0000000C
#define ACPI_GSB_ACCESS_ATTRIB_BLOCK_CALL 0x0000000D
#define ACPI_GSB_ACCESS_ATTRIB_RAW_BYTES 0x0000000E
#define ACPI_GSB_ACCESS_ATTRIB_RAW_PROCESS 0x0000000F
extern acpi_status acpi_pci_osc_control_set(acpi_handle handle,
u32 *mask, u32 req);

2
include/linux/aer.h
View File

@@ -11,6 +11,8 @@
#define AER_FATAL 1
#define AER_CORRECTABLE 2
struct pci_dev;
struct aer_header_log_regs {
unsigned int dw0;
unsigned int dw1;

5
include/linux/ahci_platform.h
View File

@@ -43,10 +43,7 @@ struct ahci_host_priv *ahci_platform_get_resources(
struct platform_device *pdev);
int ahci_platform_init_host(struct platform_device *pdev,
struct ahci_host_priv *hpriv,
const struct ata_port_info *pi_template,
unsigned long host_flags,
unsigned int force_port_map,
unsigned int mask_port_map);
const struct ata_port_info *pi_template);
int ahci_platform_suspend_host(struct device *dev);
int ahci_platform_resume_host(struct device *dev);

7
include/linux/amd-iommu.h
View File

@@ -119,6 +119,13 @@ typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
amd_iommu_invalid_ppr_cb cb);
#define PPR_FAULT_EXEC (1 << 1)
#define PPR_FAULT_READ (1 << 2)
#define PPR_FAULT_WRITE (1 << 5)
#define PPR_FAULT_USER (1 << 6)
#define PPR_FAULT_RSVD (1 << 7)
#define PPR_FAULT_GN (1 << 8)
/**
* amd_iommu_device_info() - Get information about IOMMUv2 support of a
* PCI device

10
include/linux/arcdevice.h
View File

@@ -22,10 +22,6 @@
#ifdef __KERNEL__
#include <linux/irqreturn.h>
#ifndef bool
#define bool int
#endif
/*
* RECON_THRESHOLD is the maximum number of RECON messages to receive
* within one minute before printing a "cabling problem" warning. The
@@ -285,9 +281,9 @@ struct arcnet_local {
unsigned long first_recon; /* time of "first" RECON message to count */
unsigned long last_recon; /* time of most recent RECON */
int num_recons; /* number of RECONs between first and last. */
bool network_down; /* do we think the network is down? */
int network_down; /* do we think the network is down? */
bool excnak_pending; /* We just got an excesive nak interrupt */
int excnak_pending; /* We just got an excesive nak interrupt */
struct {
uint16_t sequence; /* sequence number (incs with each packet) */
@@ -305,7 +301,7 @@ struct arcnet_local {
void (*command) (struct net_device * dev, int cmd);
int (*status) (struct net_device * dev);
void (*intmask) (struct net_device * dev, int mask);
bool (*reset) (struct net_device * dev, bool really_reset);
int (*reset) (struct net_device * dev, int really_reset);
void (*open) (struct net_device * dev);
void (*close) (struct net_device * dev);

43
include/linux/atmel-pwm-bl.h
View File

@@ -1,43 +0,0 @@
/*
* Copyright (C) 2007 Atmel Corporation
*
* Driver for the AT32AP700X PS/2 controller (PSIF).
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __INCLUDE_ATMEL_PWM_BL_H
#define __INCLUDE_ATMEL_PWM_BL_H
/**
* struct atmel_pwm_bl_platform_data
* @pwm_channel: which PWM channel in the PWM module to use.
* @pwm_frequency: PWM frequency to generate, the driver will try to be as
* close as the prescaler allows.
* @pwm_compare_max: value to use in the PWM channel compare register.
* @pwm_duty_max: maximum duty cycle value, must be less than or equal to
* pwm_compare_max.
* @pwm_duty_min: minimum duty cycle value, must be less than pwm_duty_max.
* @pwm_active_low: set to one if the low part of the PWM signal increases the
* brightness of the backlight.
* @gpio_on: GPIO line to control the backlight on/off, set to -1 if not used.
* @on_active_low: set to one if the on/off signal is on when GPIO is low.
*
* This struct must be added to the platform device in the board code. It is
* used by the atmel-pwm-bl driver to setup the GPIO to control on/off and the
* PWM device.
*/
struct atmel_pwm_bl_platform_data {
unsigned int pwm_channel;
unsigned int pwm_frequency;
unsigned int pwm_compare_max;
unsigned int pwm_duty_max;
unsigned int pwm_duty_min;
unsigned int pwm_active_low;
int gpio_on;
unsigned int on_active_low;
};
#endif /* __INCLUDE_ATMEL_PWM_BL_H */

13
include/linux/atmel-ssc.h
View File

@@ -7,6 +7,7 @@
struct atmel_ssc_platform_data {
int use_dma;
int has_fslen_ext;
};
struct ssc_device {
@@ -71,6 +72,12 @@ void ssc_free(struct ssc_device *ssc);
#define SSC_RFMR_DATNB_OFFSET 8
#define SSC_RFMR_FSEDGE_SIZE 1
#define SSC_RFMR_FSEDGE_OFFSET 24
/*
* The FSLEN_EXT exist on at91sam9rl, at91sam9g10,
* at91sam9g20, and at91sam9g45 and newer SoCs
*/
#define SSC_RFMR_FSLEN_EXT_SIZE 4
#define SSC_RFMR_FSLEN_EXT_OFFSET 28
#define SSC_RFMR_FSLEN_SIZE 4
#define SSC_RFMR_FSLEN_OFFSET 16
#define SSC_RFMR_FSOS_SIZE 4
@@ -109,6 +116,12 @@ void ssc_free(struct ssc_device *ssc);
#define SSC_TFMR_FSDEN_OFFSET 23
#define SSC_TFMR_FSEDGE_SIZE 1
#define SSC_TFMR_FSEDGE_OFFSET 24
/*
* The FSLEN_EXT exist on at91sam9rl, at91sam9g10,
* at91sam9g20, and at91sam9g45 and newer SoCs
*/
#define SSC_TFMR_FSLEN_EXT_SIZE 4
#define SSC_TFMR_FSLEN_EXT_OFFSET 28
#define SSC_TFMR_FSLEN_SIZE 4
#define SSC_TFMR_FSLEN_OFFSET 16
#define SSC_TFMR_FSOS_SIZE 3

70
include/linux/atmel_pwm.h
View File

@@ -1,70 +0,0 @@
#ifndef __LINUX_ATMEL_PWM_H
#define __LINUX_ATMEL_PWM_H
/**
* struct pwm_channel - driver handle to a PWM channel
* @regs: base of this channel's registers
* @index: number of this channel (0..31)
* @mck: base clock rate, which can be prescaled and maybe subdivided
*
* Drivers initialize a pwm_channel structure using pwm_channel_alloc().
* Then they configure its clock rate (derived from MCK), alignment,
* polarity, and duty cycle by writing directly to the channel registers,
* before enabling the channel by calling pwm_channel_enable().
*
* After emitting a PWM signal for the desired length of time, drivers
* may then pwm_channel_disable() or pwm_channel_free(). Both of these
* disable the channel, but when it's freed the IRQ is deconfigured and
* the channel must later be re-allocated and reconfigured.
*
* Note that if the period or duty cycle need to be changed while the
* PWM channel is operating, drivers must use the PWM_CUPD double buffer
* mechanism, either polling until they change or getting implicitly
* notified through a once-per-period interrupt handler.
*/
struct pwm_channel {
void __iomem *regs;
unsigned index;
unsigned long mck;
};
extern int pwm_channel_alloc(int index, struct pwm_channel *ch);
extern int pwm_channel_free(struct pwm_channel *ch);
extern int pwm_clk_alloc(unsigned prescale, unsigned div);
extern void pwm_clk_free(unsigned clk);
extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled);
#define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1)
#define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0)
/* periodic interrupts, mostly for CUPD changes to period or cycle */
extern int pwm_channel_handler(struct pwm_channel *ch,
void (*handler)(struct pwm_channel *ch));
/* per-channel registers (banked at pwm_channel->regs) */
#define PWM_CMR 0x00 /* mode register */
#define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */
#define PWM_CPR_CPOL (1 << 9) /* set: idle high */
#define PWM_CPR_CALG (1 << 8) /* set: center align */
#define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */
#define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */
#define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */
#define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */
#define PWM_CPRD 0x08 /* period (count up from zero) */
#define PWM_CCNT 0x0c /* counter (20 bits?) */
#define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */
static inline void
pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val)
{
__raw_writel(val, pwmc->regs + offset);
}
static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset)
{
return __raw_readl(pwmc->regs + offset);
}
#endif /* __LINUX_ATMEL_PWM_H */

27
include/linux/bcma/bcma.h
View File

@@ -6,6 +6,7 @@
#include <linux/bcma/bcma_driver_chipcommon.h>
#include <linux/bcma/bcma_driver_pci.h>
#include <linux/bcma/bcma_driver_pcie2.h>
#include <linux/bcma/bcma_driver_mips.h>
#include <linux/bcma/bcma_driver_gmac_cmn.h>
#include <linux/ssb/ssb.h> /* SPROM sharing */
@@ -72,17 +73,17 @@ struct bcma_host_ops {
/* Core-ID values. */
#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
#define BCMA_CORE_4706_CHIPCOMMON 0x500
#define BCMA_CORE_PCIEG2 0x501
#define BCMA_CORE_DMA 0x502
#define BCMA_CORE_SDIO3 0x503
#define BCMA_CORE_USB20 0x504
#define BCMA_CORE_USB30 0x505
#define BCMA_CORE_A9JTAG 0x506
#define BCMA_CORE_DDR23 0x507
#define BCMA_CORE_ROM 0x508
#define BCMA_CORE_NAND 0x509
#define BCMA_CORE_QSPI 0x50A
#define BCMA_CORE_CHIPCOMMON_B 0x50B
#define BCMA_CORE_NS_PCIEG2 0x501
#define BCMA_CORE_NS_DMA 0x502
#define BCMA_CORE_NS_SDIO3 0x503
#define BCMA_CORE_NS_USB20 0x504
#define BCMA_CORE_NS_USB30 0x505
#define BCMA_CORE_NS_A9JTAG 0x506
#define BCMA_CORE_NS_DDR23 0x507
#define BCMA_CORE_NS_ROM 0x508
#define BCMA_CORE_NS_NAND 0x509
#define BCMA_CORE_NS_QSPI 0x50A
#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
#define BCMA_CORE_4706_SOC_RAM 0x50E
#define BCMA_CORE_ARMCA9 0x510
#define BCMA_CORE_4706_MAC_GBIT 0x52D
@@ -157,6 +158,9 @@ struct bcma_host_ops {
/* Chip IDs of PCIe devices */
#define BCMA_CHIP_ID_BCM4313 0x4313
#define BCMA_CHIP_ID_BCM43142 43142
#define BCMA_CHIP_ID_BCM43131 43131
#define BCMA_CHIP_ID_BCM43217 43217
#define BCMA_CHIP_ID_BCM43222 43222
#define BCMA_CHIP_ID_BCM43224 43224
#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
@@ -333,6 +337,7 @@ struct bcma_bus {
struct bcma_drv_cc drv_cc;
struct bcma_drv_pci drv_pci[2];
struct bcma_drv_pcie2 drv_pcie2;
struct bcma_drv_mips drv_mips;
struct bcma_drv_gmac_cmn drv_gmac_cmn;

158
include/linux/bcma/bcma_driver_pcie2.h Normal file
View File

@@ -0,0 +1,158 @@
#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
#define LINUX_BCMA_DRIVER_PCIE2_H_
#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
#define BCMA_CORE_PCIE2_DATAINTF 0x0180
#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
#define PCIE2_LTR_ACTIVE 2
#define PCIE2_LTR_ACTIVE_IDLE 1
#define PCIE2_LTR_SLEEP 0
#define PCIE2_LTR_FINAL_MASK 0x300
#define PCIE2_LTR_FINAL_SHIFT 8
#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
#define BCMA_CORE_PCIE2_OARR0 0x0D20
#define BCMA_CORE_PCIE2_OARR1 0x0D28
#define BCMA_CORE_PCIE2_OARR2 0x0D30
#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
/* PCIE gen2 config regs */
#define PCIE2_INTSTATUS 0x090
#define PCIE2_INTMASK 0x094
#define PCIE2_SBMBX 0x098
#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
struct bcma_drv_pcie2 {
struct bcma_device *core;
};
#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */

1
include/linux/bio.h
View File

@@ -308,6 +308,7 @@ struct bio_integrity_payload {
unsigned short bip_slab; /* slab the bip came from */
unsigned short bip_vcnt; /* # of integrity bio_vecs */
unsigned short bip_max_vcnt; /* integrity bio_vec slots */
unsigned bip_owns_buf:1; /* should free bip_buf */
struct work_struct bip_work; /* I/O completion */

62
include/linux/bitmap.h
View File

@@ -88,32 +88,32 @@
* lib/bitmap.c provides these functions:
*/
extern int __bitmap_empty(const unsigned long *bitmap, int bits);
extern int __bitmap_full(const unsigned long *bitmap, int bits);
extern int __bitmap_empty(const unsigned long *bitmap, unsigned int nbits);
extern int __bitmap_full(const unsigned long *bitmap, unsigned int nbits);
extern int __bitmap_equal(const unsigned long *bitmap1,
const unsigned long *bitmap2, int bits);
const unsigned long *bitmap2, unsigned int nbits);
extern void __bitmap_complement(unsigned long *dst, const unsigned long *src,
int bits);
unsigned int nbits);
extern void __bitmap_shift_right(unsigned long *dst,
const unsigned long *src, int shift, int bits);
extern void __bitmap_shift_left(unsigned long *dst,
const unsigned long *src, int shift, int bits);
extern int __bitmap_and(unsigned long *dst, const unsigned long *bitmap1,
const unsigned long *bitmap2, int bits);
const unsigned long *bitmap2, unsigned int nbits);
extern void __bitmap_or(unsigned long *dst, const unsigned long *bitmap1,
const unsigned long *bitmap2, int bits);
const unsigned long *bitmap2, unsigned int nbits);
extern void __bitmap_xor(unsigned long *dst, const unsigned long *bitmap1,
const unsigned long *bitmap2, int bits);
const unsigned long *bitmap2, unsigned int nbits);
extern int __bitmap_andnot(unsigned long *dst, const unsigned long *bitmap1,
const unsigned long *bitmap2, int bits);
const unsigned long *bitmap2, unsigned int nbits);
extern int __bitmap_intersects(const unsigned long *bitmap1,
const unsigned long *bitmap2, int bits);
const unsigned long *bitmap2, unsigned int nbits);
extern int __bitmap_subset(const unsigned long *bitmap1,
const unsigned long *bitmap2, int bits);
extern int __bitmap_weight(const unsigned long *bitmap, int bits);
const unsigned long *bitmap2, unsigned int nbits);
extern int __bitmap_weight(const unsigned long *bitmap, unsigned int nbits);
extern void bitmap_set(unsigned long *map, int i, int len);
extern void bitmap_clear(unsigned long *map, int start, int nr);
extern void bitmap_set(unsigned long *map, unsigned int start, int len);
extern void bitmap_clear(unsigned long *map, unsigned int start, int len);
extern unsigned long bitmap_find_next_zero_area(unsigned long *map,
unsigned long size,
unsigned long start,
@@ -140,9 +140,9 @@ extern void bitmap_onto(unsigned long *dst, const unsigned long *orig,
const unsigned long *relmap, int bits);
extern void bitmap_fold(unsigned long *dst, const unsigned long *orig,
int sz, int bits);
extern int bitmap_find_free_region(unsigned long *bitmap, int bits, int order);
extern void bitmap_release_region(unsigned long *bitmap, int pos, int order);
extern int bitmap_allocate_region(unsigned long *bitmap, int pos, int order);
extern int bitmap_find_free_region(unsigned long *bitmap, unsigned int bits, int order);
extern void bitmap_release_region(unsigned long *bitmap, unsigned int pos, int order);
extern int bitmap_allocate_region(unsigned long *bitmap, unsigned int pos, int order);
extern void bitmap_copy_le(void *dst, const unsigned long *src, int nbits);
extern int bitmap_ord_to_pos(const unsigned long *bitmap, int n, int bits);
@@ -188,15 +188,15 @@ static inline void bitmap_copy(unsigned long *dst, const unsigned long *src,
}
static inline int bitmap_and(unsigned long *dst, const unsigned long *src1,
const unsigned long *src2, int nbits)
const unsigned long *src2, unsigned int nbits)
{
if (small_const_nbits(nbits))
return (*dst = *src1 & *src2) != 0;
return (*dst = *src1 & *src2 & BITMAP_LAST_WORD_MASK(nbits)) != 0;
return __bitmap_and(dst, src1, src2, nbits);
}
static inline void bitmap_or(unsigned long *dst, const unsigned long *src1,
const unsigned long *src2, int nbits)
const unsigned long *src2, unsigned int nbits)
{
if (small_const_nbits(nbits))
*dst = *src1 | *src2;
@@ -205,7 +205,7 @@ static inline void bitmap_or(unsigned long *dst, const unsigned long *src1,
}
static inline void bitmap_xor(unsigned long *dst, const unsigned long *src1,
const unsigned long *src2, int nbits)
const unsigned long *src2, unsigned int nbits)
{
if (small_const_nbits(nbits))
*dst = *src1 ^ *src2;
@@ -214,24 +214,24 @@ static inline void bitmap_xor(unsigned long *dst, const unsigned long *src1,
}
static inline int bitmap_andnot(unsigned long *dst, const unsigned long *src1,
const unsigned long *src2, int nbits)
const unsigned long *src2, unsigned int nbits)
{
if (small_const_nbits(nbits))
return (*dst = *src1 & ~(*src2)) != 0;
return (*dst = *src1 & ~(*src2) & BITMAP_LAST_WORD_MASK(nbits)) != 0;
return __bitmap_andnot(dst, src1, src2, nbits);
}
static inline void bitmap_complement(unsigned long *dst, const unsigned long *src,
int nbits)
unsigned int nbits)
{
if (small_const_nbits(nbits))
*dst = ~(*src) & BITMAP_LAST_WORD_MASK(nbits);
*dst = ~(*src);
else
__bitmap_complement(dst, src, nbits);
}
static inline int bitmap_equal(const unsigned long *src1,
const unsigned long *src2, int nbits)
const unsigned long *src2, unsigned int nbits)
{
if (small_const_nbits(nbits))
return ! ((*src1 ^ *src2) & BITMAP_LAST_WORD_MASK(nbits));
@@ -240,7 +240,7 @@ static inline int bitmap_equal(const unsigned long *src1,
}
static inline int bitmap_intersects(const unsigned long *src1,
const unsigned long *src2, int nbits)
const unsigned long *src2, unsigned int nbits)
{
if (small_const_nbits(nbits))
return ((*src1 & *src2) & BITMAP_LAST_WORD_MASK(nbits)) != 0;
@@ -249,7 +249,7 @@ static inline int bitmap_intersects(const unsigned long *src1,
}
static inline int bitmap_subset(const unsigned long *src1,
const unsigned long *src2, int nbits)
const unsigned long *src2, unsigned int nbits)
{
if (small_const_nbits(nbits))
return ! ((*src1 & ~(*src2)) & BITMAP_LAST_WORD_MASK(nbits));
@@ -257,7 +257,7 @@ static inline int bitmap_subset(const unsigned long *src1,
return __bitmap_subset(src1, src2, nbits);
}
static inline int bitmap_empty(const unsigned long *src, int nbits)
static inline int bitmap_empty(const unsigned long *src, unsigned nbits)
{
if (small_const_nbits(nbits))
return ! (*src & BITMAP_LAST_WORD_MASK(nbits));
@@ -265,7 +265,7 @@ static inline int bitmap_empty(const unsigned long *src, int nbits)
return __bitmap_empty(src, nbits);
}
static inline int bitmap_full(const unsigned long *src, int nbits)
static inline int bitmap_full(const unsigned long *src, unsigned int nbits)
{
if (small_const_nbits(nbits))
return ! (~(*src) & BITMAP_LAST_WORD_MASK(nbits));
@@ -273,7 +273,7 @@ static inline int bitmap_full(const unsigned long *src, int nbits)
return __bitmap_full(src, nbits);
}
static inline int bitmap_weight(const unsigned long *src, int nbits)
static inline int bitmap_weight(const unsigned long *src, unsigned int nbits)
{
if (small_const_nbits(nbits))
return hweight_long(*src & BITMAP_LAST_WORD_MASK(nbits));
@@ -284,7 +284,7 @@ static inline void bitmap_shift_right(unsigned long *dst,
const unsigned long *src, int n, int nbits)
{
if (small_const_nbits(nbits))
*dst = *src >> n;
*dst = (*src & BITMAP_LAST_WORD_MASK(nbits)) >> n;
else
__bitmap_shift_right(dst, src, n, nbits);
}

7
include/linux/blk-mq.h
View File

@@ -127,10 +127,9 @@ enum {
BLK_MQ_RQ_QUEUE_ERROR = 2, /* end IO with error */
BLK_MQ_F_SHOULD_MERGE = 1 << 0,
BLK_MQ_F_SHOULD_SORT = 1 << 1,
BLK_MQ_F_TAG_SHARED = 1 << 2,
BLK_MQ_F_SG_MERGE = 1 << 3,
BLK_MQ_F_SYSFS_UP = 1 << 4,
BLK_MQ_F_TAG_SHARED = 1 << 1,
BLK_MQ_F_SG_MERGE = 1 << 2,
BLK_MQ_F_SYSFS_UP = 1 << 3,
BLK_MQ_S_STOPPED = 0,
BLK_MQ_S_TAG_ACTIVE = 1,

4
include/linux/blkdev.h
View File

@@ -21,6 +21,7 @@
#include <linux/bsg.h>
#include <linux/smp.h>
#include <linux/rcupdate.h>
#include <linux/percpu-refcount.h>
#include <asm/scatterlist.h>
@@ -470,6 +471,7 @@ struct request_queue {
struct mutex sysfs_lock;
int bypass_depth;
int mq_freeze_depth;
#if defined(CONFIG_BLK_DEV_BSG)
bsg_job_fn *bsg_job_fn;
@@ -483,7 +485,7 @@ struct request_queue {
#endif
struct rcu_head rcu_head;
wait_queue_head_t mq_freeze_wq;
struct percpu_counter mq_usage_counter;
struct percpu_ref mq_usage_counter;
struct list_head all_q_node;
struct blk_mq_tag_set *tag_set;

1
include/linux/brcmphy.h
View File

@@ -16,7 +16,6 @@
#define PHY_ID_BCM7366 0x600d8490
#define PHY_ID_BCM7439 0x600d8480
#define PHY_ID_BCM7445 0x600d8510
#define PHY_ID_BCM7XXX_28 0x600d8400
#define PHY_BCM_OUI_MASK 0xfffffc00
#define PHY_BCM_OUI_1 0x00206000

2
include/linux/byteorder/generic.h
View File

@@ -2,7 +2,7 @@
#define _LINUX_BYTEORDER_GENERIC_H
/*
* linux/byteorder_generic.h
* linux/byteorder/generic.h
* Generic Byte-reordering support
*
* The "... p" macros, like le64_to_cpup, can be used with pointers

12
include/linux/ccp.h
View File

@@ -26,6 +26,13 @@ struct ccp_cmd;
#if defined(CONFIG_CRYPTO_DEV_CCP_DD) || \
defined(CONFIG_CRYPTO_DEV_CCP_DD_MODULE)
/**
* ccp_present - check if a CCP device is present
*
* Returns zero if a CCP device is present, -ENODEV otherwise.
*/
int ccp_present(void);
/**
* ccp_enqueue_cmd - queue an operation for processing by the CCP
*
@@ -53,6 +60,11 @@ int ccp_enqueue_cmd(struct ccp_cmd *cmd);
#else /* CONFIG_CRYPTO_DEV_CCP_DD is not enabled */
static inline int ccp_present(void)
{
return -ENODEV;
}
static inline int ccp_enqueue_cmd(struct ccp_cmd *cmd)
{
return -ENODEV;

14
include/linux/ceph/messenger.h
View File

@@ -285,19 +285,9 @@ extern void ceph_msg_data_add_bio(struct ceph_msg *msg, struct bio *bio,
extern struct ceph_msg *ceph_msg_new(int type, int front_len, gfp_t flags,
bool can_fail);
extern void ceph_msg_kfree(struct ceph_msg *m);
static inline struct ceph_msg *ceph_msg_get(struct ceph_msg *msg)
{
kref_get(&msg->kref);
return msg;
}
extern void ceph_msg_last_put(struct kref *kref);
static inline void ceph_msg_put(struct ceph_msg *msg)
{
kref_put(&msg->kref, ceph_msg_last_put);
}
extern struct ceph_msg *ceph_msg_get(struct ceph_msg *msg);
extern void ceph_msg_put(struct ceph_msg *msg);
extern void ceph_msg_dump(struct ceph_msg *msg);

16
include/linux/ceph/osd_client.h
View File

@@ -117,7 +117,7 @@ struct ceph_osd_request {
struct list_head r_req_lru_item;
struct list_head r_osd_item;
struct list_head r_linger_item;
struct list_head r_linger_osd;
struct list_head r_linger_osd_item;
struct ceph_osd *r_osd;
struct ceph_pg r_pgid;
int r_pg_osds[CEPH_PG_MAX_SIZE];
@@ -325,22 +325,14 @@ extern struct ceph_osd_request *ceph_osdc_new_request(struct ceph_osd_client *,
extern void ceph_osdc_set_request_linger(struct ceph_osd_client *osdc,
struct ceph_osd_request *req);
extern void ceph_osdc_unregister_linger_request(struct ceph_osd_client *osdc,
struct ceph_osd_request *req);
static inline void ceph_osdc_get_request(struct ceph_osd_request *req)
{
kref_get(&req->r_kref);
}
extern void ceph_osdc_release_request(struct kref *kref);
static inline void ceph_osdc_put_request(struct ceph_osd_request *req)
{
kref_put(&req->r_kref, ceph_osdc_release_request);
}
extern void ceph_osdc_get_request(struct ceph_osd_request *req);
extern void ceph_osdc_put_request(struct ceph_osd_request *req);
extern int ceph_osdc_start_request(struct ceph_osd_client *osdc,
struct ceph_osd_request *req,
bool nofail);
extern void ceph_osdc_cancel_request(struct ceph_osd_request *req);
extern int ceph_osdc_wait_request(struct ceph_osd_client *osdc,
struct ceph_osd_request *req);
extern void ceph_osdc_sync(struct ceph_osd_client *osdc);

165
include/linux/cgroup.h
View File

@@ -203,7 +203,15 @@ struct cgroup {
struct kernfs_node *kn; /* cgroup kernfs entry */
struct kernfs_node *populated_kn; /* kn for "cgroup.subtree_populated" */
/* the bitmask of subsystems enabled on the child cgroups */
/*
* The bitmask of subsystems enabled on the child cgroups.
* ->subtree_control is the one configured through
* "cgroup.subtree_control" while ->child_subsys_mask is the
* effective one which may have more subsystems enabled.
* Controller knobs are made available iff it's enabled in
* ->subtree_control.
*/
unsigned int subtree_control;
unsigned int child_subsys_mask;
/* Private pointers for each registered subsystem */
@@ -248,73 +256,9 @@ struct cgroup {
/* cgroup_root->flags */
enum {
/*
* Unfortunately, cgroup core and various controllers are riddled
* with idiosyncrasies and pointless options. The following flag,
* when set, will force sane behavior - some options are forced on,
* others are disallowed, and some controllers will change their
* hierarchical or other behaviors.
*
* The set of behaviors affected by this flag are still being
* determined and developed and the mount option for this flag is
* prefixed with __DEVEL__. The prefix will be dropped once we
* reach the point where all behaviors are compatible with the
* planned unified hierarchy, which will automatically turn on this
* flag.
*
* The followings are the behaviors currently affected this flag.
*
* - Mount options "noprefix", "xattr", "clone_children",
* "release_agent" and "name" are disallowed.
*
* - When mounting an existing superblock, mount options should
* match.
*
* - Remount is disallowed.
*
* - rename(2) is disallowed.
*
* - "tasks" is removed. Everything should be at process
* granularity. Use "cgroup.procs" instead.
*
* - "cgroup.procs" is not sorted. pids will be unique unless they
* got recycled inbetween reads.
*
* - "release_agent" and "notify_on_release" are removed.
* Replacement notification mechanism will be implemented.
*
* - "cgroup.clone_children" is removed.
*
* - "cgroup.subtree_populated" is available. Its value is 0 if
* the cgroup and its descendants contain no task; otherwise, 1.
* The file also generates kernfs notification which can be
* monitored through poll and [di]notify when the value of the
* file changes.
*
* - If mount is requested with sane_behavior but without any
* subsystem, the default unified hierarchy is mounted.
*
* - cpuset: tasks will be kept in empty cpusets when hotplug happens
* and take masks of ancestors with non-empty cpus/mems, instead of
* being moved to an ancestor.
*
* - cpuset: a task can be moved into an empty cpuset, and again it
* takes masks of ancestors.
*
* - memcg: use_hierarchy is on by default and the cgroup file for
* the flag is not created.
*
* - blkcg: blk-throttle becomes properly hierarchical.
*
* - debug: disallowed on the default hierarchy.
*/
CGRP_ROOT_SANE_BEHAVIOR = (1 << 0),
CGRP_ROOT_SANE_BEHAVIOR = (1 << 0), /* __DEVEL__sane_behavior specified */
CGRP_ROOT_NOPREFIX = (1 << 1), /* mounted subsystems have no named prefix */
CGRP_ROOT_XATTR = (1 << 2), /* supports extended attributes */
/* mount options live below bit 16 */
CGRP_ROOT_OPTION_MASK = (1 << 16) - 1,
};
/*
@@ -440,9 +384,11 @@ struct css_set {
enum {
CFTYPE_ONLY_ON_ROOT = (1 << 0), /* only create on root cgrp */
CFTYPE_NOT_ON_ROOT = (1 << 1), /* don't create on root cgrp */
CFTYPE_INSANE = (1 << 2), /* don't create if sane_behavior */
CFTYPE_NO_PREFIX = (1 << 3), /* (DON'T USE FOR NEW FILES) no subsys prefix */
CFTYPE_ONLY_ON_DFL = (1 << 4), /* only on default hierarchy */
/* internal flags, do not use outside cgroup core proper */
__CFTYPE_ONLY_ON_DFL = (1 << 16), /* only on default hierarchy */
__CFTYPE_NOT_ON_DFL = (1 << 17), /* not on default hierarchy */
};
#define MAX_CFTYPE_NAME 64
@@ -526,20 +472,64 @@ struct cftype {
extern struct cgroup_root cgrp_dfl_root;
extern struct css_set init_css_set;
/**
* cgroup_on_dfl - test whether a cgroup is on the default hierarchy
* @cgrp: the cgroup of interest
*
* The default hierarchy is the v2 interface of cgroup and this function
* can be used to test whether a cgroup is on the default hierarchy for
* cases where a subsystem should behave differnetly depending on the
* interface version.
*
* The set of behaviors which change on the default hierarchy are still
* being determined and the mount option is prefixed with __DEVEL__.
*
* List of changed behaviors:
*
* - Mount options "noprefix", "xattr", "clone_children", "release_agent"
* and "name" are disallowed.
*
* - When mounting an existing superblock, mount options should match.
*
* - Remount is disallowed.
*
* - rename(2) is disallowed.
*
* - "tasks" is removed. Everything should be at process granularity. Use
* "cgroup.procs" instead.
*
* - "cgroup.procs" is not sorted. pids will be unique unless they got
* recycled inbetween reads.
*
* - "release_agent" and "notify_on_release" are removed. Replacement
* notification mechanism will be implemented.
*
* - "cgroup.clone_children" is removed.
*
* - "cgroup.subtree_populated" is available. Its value is 0 if the cgroup
* and its descendants contain no task; otherwise, 1. The file also
* generates kernfs notification which can be monitored through poll and
* [di]notify when the value of the file changes.
*
* - cpuset: tasks will be kept in empty cpusets when hotplug happens and
* take masks of ancestors with non-empty cpus/mems, instead of being
* moved to an ancestor.
*
* - cpuset: a task can be moved into an empty cpuset, and again it takes
* masks of ancestors.
*
* - memcg: use_hierarchy is on by default and the cgroup file for the flag
* is not created.
*
* - blkcg: blk-throttle becomes properly hierarchical.
*
* - debug: disallowed on the default hierarchy.
*/
static inline bool cgroup_on_dfl(const struct cgroup *cgrp)
{
return cgrp->root == &cgrp_dfl_root;
}
/*
* See the comment above CGRP_ROOT_SANE_BEHAVIOR for details. This
* function can be called as long as @cgrp is accessible.
*/
static inline bool cgroup_sane_behavior(const struct cgroup *cgrp)
{
return cgrp->root->flags & CGRP_ROOT_SANE_BEHAVIOR;
}
/* no synchronization, the result can only be used as a hint */
static inline bool cgroup_has_tasks(struct cgroup *cgrp)
{
@@ -602,7 +592,8 @@ static inline void pr_cont_cgroup_path(struct cgroup *cgrp)
char *task_cgroup_path(struct task_struct *task, char *buf, size_t buflen);
int cgroup_add_cftypes(struct cgroup_subsys *ss, struct cftype *cfts);
int cgroup_add_dfl_cftypes(struct cgroup_subsys *ss, struct cftype *cfts);
int cgroup_add_legacy_cftypes(struct cgroup_subsys *ss, struct cftype *cfts);
int cgroup_rm_cftypes(struct cftype *cfts);
bool cgroup_is_descendant(struct cgroup *cgrp, struct cgroup *ancestor);
@@ -634,6 +625,7 @@ struct cgroup_subsys {
int (*css_online)(struct cgroup_subsys_state *css);
void (*css_offline)(struct cgroup_subsys_state *css);
void (*css_free)(struct cgroup_subsys_state *css);
void (*css_reset)(struct cgroup_subsys_state *css);
int (*can_attach)(struct cgroup_subsys_state *css,
struct cgroup_taskset *tset);
@@ -682,8 +674,21 @@ struct cgroup_subsys {
*/
struct list_head cfts;
/* base cftypes, automatically registered with subsys itself */
struct cftype *base_cftypes;
/*
* Base cftypes which are automatically registered. The two can
* point to the same array.
*/
struct cftype *dfl_cftypes; /* for the default hierarchy */
struct cftype *legacy_cftypes; /* for the legacy hierarchies */
/*
* A subsystem may depend on other subsystems. When such subsystem
* is enabled on a cgroup, the depended-upon subsystems are enabled
* together if available. Subsystems enabled due to dependency are
* not visible to userland until explicitly enabled. The following
* specifies the mask of subsystems that this one depends on.
*/
unsigned int depends_on;
};
#define SUBSYS(_x) extern struct cgroup_subsys _x ## _cgrp_subsys;

5
include/linux/clk-provider.h
View File

@@ -619,5 +619,10 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
#endif /* platform dependent I/O accessors */
#ifdef CONFIG_DEBUG_FS
struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
void *data, const struct file_operations *fops);
#endif
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */

20
include/linux/clk/clk-conf.h Normal file
View File

@@ -0,0 +1,20 @@
/*
* Copyright (C) 2014 Samsung Electronics Co., Ltd.
* Sylwester Nawrocki <s.nawrocki@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
struct device_node;
#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
int of_clk_set_defaults(struct device_node *node, bool clk_supplier);
#else
static inline int of_clk_set_defaults(struct device_node *node,
bool clk_supplier)
{
return 0;
}
#endif

2
include/linux/clocksource.h
View File

@@ -162,7 +162,6 @@ extern u64 timecounter_cyc2time(struct timecounter *tc,
* @archdata: arch-specific data
* @suspend: suspend function for the clocksource, if necessary
* @resume: resume function for the clocksource, if necessary
* @cycle_last: most recent cycle counter value seen by ::read()
* @owner: module reference, must be set by clocksource in modules
*/
struct clocksource {
@@ -171,7 +170,6 @@ struct clocksource {
* clocksource itself is cacheline aligned.
*/
cycle_t (*read)(struct clocksource *cs);
cycle_t cycle_last;
cycle_t mask;
u32 mult;
u32 shift;

27
include/linux/cma.h Normal file
View File

@@ -0,0 +1,27 @@
#ifndef __CMA_H__
#define __CMA_H__
/*
* There is always at least global CMA area and a few optional
* areas configured in kernel .config.
*/
#ifdef CONFIG_CMA_AREAS
#define MAX_CMA_AREAS (1 + CONFIG_CMA_AREAS)
#else
#define MAX_CMA_AREAS (0)
#endif
struct cma;
extern phys_addr_t cma_get_base(struct cma *cma);
extern unsigned long cma_get_size(struct cma *cma);
extern int __init cma_declare_contiguous(phys_addr_t size,
phys_addr_t base, phys_addr_t limit,
phys_addr_t alignment, unsigned int order_per_bit,
bool fixed, struct cma **res_cma);
extern struct page *cma_alloc(struct cma *cma, int count, unsigned int align);
extern bool cma_release(struct cma *cma, struct page *pages, int count);
#endif

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