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Merge branch 'android12-5.10' into android12-5.10-lts

Browse Source 
Catch this branch up to what is in `android12-5.10`

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Ic6606f5a9ad3b3c6915e57d358b704f97abf9cab
This commit is contained in:
Greg Kroah-Hartman
2021-04-16 16:02:58 +02:00
parent e9fa24e154 ab8b108b0a
commit b0c3c31639
862 changed files with 86944 additions and 70443 deletions
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25
Documentation/ABI/testing/sysfs-kernel-mm-cma Normal file
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@@ -0,0 +1,25 @@
What: /sys/kernel/mm/cma/
Date: Feb 2021
Contact: Minchan Kim <minchan@kernel.org>
Description:
/sys/kernel/mm/cma/ contains a subdirectory for each CMA
heap name (also sometimes called CMA areas).
Each CMA heap subdirectory (that is, each
/sys/kernel/mm/cma/<cma-heap-name> directory) contains the
following items:
alloc_pages_success
alloc_pages_fail
What: /sys/kernel/mm/cma/<cma-heap-name>/alloc_pages_success
Date: Feb 2021
Contact: Minchan Kim <minchan@kernel.org>
Description:
the number of pages CMA API succeeded to allocate
What: /sys/kernel/mm/cma/<cma-heap-name>/alloc_pages_fail
Date: Feb 2021
Contact: Minchan Kim <minchan@kernel.org>
Description:
the number of pages CMA API failed to allocate

99
Documentation/admin-guide/mm/userfaultfd.rst
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@@ -63,36 +63,36 @@ the generic ioctl available.
The ``uffdio_api.features`` bitmask returned by the ``UFFDIO_API`` ioctl
defines what memory types are supported by the ``userfaultfd`` and what
events, except page fault notifications, may be generated.
events, except page fault notifications, may be generated:
If the kernel supports registering ``userfaultfd`` ranges on hugetlbfs
virtual memory areas, ``UFFD_FEATURE_MISSING_HUGETLBFS`` will be set in
``uffdio_api.features``. Similarly, ``UFFD_FEATURE_MISSING_SHMEM`` will be
set if the kernel supports registering ``userfaultfd`` ranges on shared
memory (covering all shmem APIs, i.e. tmpfs, ``IPCSHM``, ``/dev/zero``,
``MAP_SHARED``, ``memfd_create``, etc).
- The ``UFFD_FEATURE_EVENT_*`` flags indicate that various other events
other than page faults are supported. These events are described in more
detail below in the `Non-cooperative userfaultfd`_ section.
The userland application that wants to use ``userfaultfd`` with hugetlbfs
or shared memory need to set the corresponding flag in
``uffdio_api.features`` to enable those features.
- ``UFFD_FEATURE_MISSING_HUGETLBFS`` and ``UFFD_FEATURE_MISSING_SHMEM``
indicate that the kernel supports ``UFFDIO_REGISTER_MODE_MISSING``
registrations for hugetlbfs and shared memory (covering all shmem APIs,
i.e. tmpfs, ``IPCSHM``, ``/dev/zero``, ``MAP_SHARED``, ``memfd_create``,
etc) virtual memory areas, respectively.
If the userland desires to receive notifications for events other than
page faults, it has to verify that ``uffdio_api.features`` has appropriate
``UFFD_FEATURE_EVENT_*`` bits set. These events are described in more
detail below in `Non-cooperative userfaultfd`_ section.
- ``UFFD_FEATURE_MINOR_HUGETLBFS`` indicates that the kernel supports
``UFFDIO_REGISTER_MODE_MINOR`` registration for hugetlbfs virtual memory
areas.
Once the ``userfaultfd`` has been enabled the ``UFFDIO_REGISTER`` ioctl should
be invoked (if present in the returned ``uffdio_api.ioctls`` bitmask) to
register a memory range in the ``userfaultfd`` by setting the
The userland application should set the feature flags it intends to use
when invoking the ``UFFDIO_API`` ioctl, to request that those features be
enabled if supported.
Once the ``userfaultfd`` API has been enabled the ``UFFDIO_REGISTER``
ioctl should be invoked (if present in the returned ``uffdio_api.ioctls``
bitmask) to register a memory range in the ``userfaultfd`` by setting the
uffdio_register structure accordingly. The ``uffdio_register.mode``
bitmask will specify to the kernel which kind of faults to track for
the range (``UFFDIO_REGISTER_MODE_MISSING`` would track missing
pages). The ``UFFDIO_REGISTER`` ioctl will return the
the range. The ``UFFDIO_REGISTER`` ioctl will return the
``uffdio_register.ioctls`` bitmask of ioctls that are suitable to resolve
userfaults on the range registered. Not all ioctls will necessarily be
supported for all memory types depending on the underlying virtual
memory backend (anonymous memory vs tmpfs vs real filebacked
mappings).
supported for all memory types (e.g. anonymous memory vs. shmem vs.
hugetlbfs), or all types of intercepted faults.
Userland can use the ``uffdio_register.ioctls`` to manage the virtual
address space in the background (to add or potentially also remove
@@ -100,21 +100,46 @@ memory from the ``userfaultfd`` registered range). This means a userfault
could be triggering just before userland maps in the background the
user-faulted page.
The primary ioctl to resolve userfaults is ``UFFDIO_COPY``. That
atomically copies a page into the userfault registered range and wakes
up the blocked userfaults
(unless ``uffdio_copy.mode & UFFDIO_COPY_MODE_DONTWAKE`` is set).
Other ioctl works similarly to ``UFFDIO_COPY``. They're atomic as in
guaranteeing that nothing can see an half copied page since it'll
keep userfaulting until the copy has finished.
Resolving Userfaults
--------------------
There are three basic ways to resolve userfaults:
- ``UFFDIO_COPY`` atomically copies some existing page contents from
userspace.
- ``UFFDIO_ZEROPAGE`` atomically zeros the new page.
- ``UFFDIO_CONTINUE`` maps an existing, previously-populated page.
These operations are atomic in the sense that they guarantee nothing can
see a half-populated page, since readers will keep userfaulting until the
operation has finished.
By default, these wake up userfaults blocked on the range in question.
They support a ``UFFDIO_*_MODE_DONTWAKE`` ``mode`` flag, which indicates
that waking will be done separately at some later time.
Which ioctl to choose depends on the kind of page fault, and what we'd
like to do to resolve it:
- For ``UFFDIO_REGISTER_MODE_MISSING`` faults, the fault needs to be
resolved by either providing a new page (``UFFDIO_COPY``), or mapping
the zero page (``UFFDIO_ZEROPAGE``). By default, the kernel would map
the zero page for a missing fault. With userfaultfd, userspace can
decide what content to provide before the faulting thread continues.
- For ``UFFDIO_REGISTER_MODE_MINOR`` faults, there is an existing page (in
the page cache). Userspace has the option of modifying the page's
contents before resolving the fault. Once the contents are correct
(modified or not), userspace asks the kernel to map the page and let the
faulting thread continue with ``UFFDIO_CONTINUE``.
Notes:
- If you requested ``UFFDIO_REGISTER_MODE_MISSING`` when registering then
you must provide some kind of page in your thread after reading from
the uffd. You must provide either ``UFFDIO_COPY`` or ``UFFDIO_ZEROPAGE``.
The normal behavior of the OS automatically providing a zero page on
an annonymous mmaping is not in place.
- You can tell which kind of fault occurred by examining
``pagefault.flags`` within the ``uffd_msg``, checking for the
``UFFD_PAGEFAULT_FLAG_*`` flags.
- None of the page-delivering ioctls default to the range that you
registered with. You must fill in all fields for the appropriate
@@ -122,9 +147,9 @@ Notes:
- You get the address of the access that triggered the missing page
event out of a struct uffd_msg that you read in the thread from the
uffd. You can supply as many pages as you want with ``UFFDIO_COPY`` or
``UFFDIO_ZEROPAGE``. Keep in mind that unless you used DONTWAKE then
the first of any of those IOCTLs wakes up the faulting thread.
uffd. You can supply as many pages as you want with these IOCTLs.
Keep in mind that unless you used DONTWAKE then the first of any of
those IOCTLs wakes up the faulting thread.
- Be sure to test for all errors including
(``pollfd[0].revents & POLLERR``). This can happen, e.g. when ranges

4
Documentation/admin-guide/ramoops.rst
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@@ -3,7 +3,7 @@ Ramoops oops/panic logger
Sergiu Iordache <sergiu@chromium.org>
Updated: 17 November 2011
Updated: 10 Feb 2021
Introduction
------------
@@ -30,6 +30,8 @@ mapping to pgprot_writecombine. Setting ``mem_type=1`` attempts to use
depends on atomic operations. At least on ARM, pgprot_noncached causes the
memory to be mapped strongly ordered, and atomic operations on strongly ordered
memory are implementation defined, and won't work on many ARMs such as omaps.
Setting ``mem_type=2`` attempts to treat the memory region as normal memory,
which enables full cache on it. This can improve the performance.
The memory area is divided into ``record_size`` chunks (also rounded down to
power of two) and each kmesg dump writes a ``record_size`` chunk of

105
Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
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@@ -1,105 +0,0 @@
* Mediatek IOMMU Architecture Implementation
Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and
this M4U have two generations of HW architecture. Generation one uses flat
pagetable, and only supports 4K size page mapping. Generation two uses the
ARM Short-Descriptor translation table format for address translation.
About the M4U Hardware Block Diagram, please check below:
EMI (External Memory Interface)
|
m4u (Multimedia Memory Management Unit)
|
+--------+
| |
gals0-rx gals1-rx (Global Async Local Sync rx)
| |
| |
gals0-tx gals1-tx (Global Async Local Sync tx)
| | Some SoCs may have GALS.
+--------+
|
SMI Common(Smart Multimedia Interface Common)
|
+----------------+-------
| |
| gals-rx There may be GALS in some larbs.
| |
| |
| gals-tx
| |
SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
(display) (vdec)
| |
| |
+-----+-----+ +----+----+
| | | | | |
| | |... | | | ... There are different ports in each larb.
| | | | | |
OVL0 RDMA0 WDMA0 MC PP VLD
As above, The Multimedia HW will go through SMI and M4U while it
access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
smi local arbiter and smi common. It will control whether the Multimedia
HW should go though the m4u for translation or bypass it and talk
directly with EMI. And also SMI help control the power domain and clocks for
each local arbiter.
Normally we specify a local arbiter(larb) for each multimedia HW
like display, video decode, and camera. And there are different ports
in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.
In some SoCs, there may be a GALS(Global Async Local Sync) module between
smi-common and m4u, and additional GALS module between smi-larb and
smi-common. GALS can been seen as a "asynchronous fifo" which could help
synchronize for the modules in different clock frequency.
Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
"mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.
"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
generation one m4u HW.
"mediatek,mt8167-m4u" for mt8167 which uses generation two m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
"mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
- clocks : must contain one entry for each clock-names.
- clock-names : Only 1 optional clock:
- "bclk": the block clock of m4u.
Here is the list which require this "bclk":
- mt2701, mt2712, mt7623 and mt8173.
Note that m4u use the EMI clock which always has been enabled before kernel
if there is no this "bclk".
- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
dt-binding/memory/mt2712-larb-port.h for mt2712,
dt-binding/memory/mt6779-larb-port.h for mt6779,
dt-binding/memory/mt8167-larb-port.h for mt8167,
dt-binding/memory/mt8173-larb-port.h for mt8173, and
dt-binding/memory/mt8183-larb-port.h for mt8183.
Example:
iommu: iommu@10205000 {
compatible = "mediatek,mt8173-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>;
#iommu-cells = <1>;
};
Example for a client device:
display {
compatible = "mediatek,mt8173-disp";
iommus = <&iommu M4U_PORT_DISP_OVL0>,
<&iommu M4U_PORT_DISP_RDMA0>;
...
};

183
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml Normal file
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@@ -0,0 +1,183 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek IOMMU Architecture Implementation
maintainers:
- Yong Wu <yong.wu@mediatek.com>
description: |+
Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
this M4U have two generations of HW architecture. Generation one uses flat
pagetable, and only supports 4K size page mapping. Generation two uses the
ARM Short-Descriptor translation table format for address translation.
About the M4U Hardware Block Diagram, please check below:
EMI (External Memory Interface)
|
m4u (Multimedia Memory Management Unit)
|
+--------+
| |
gals0-rx gals1-rx (Global Async Local Sync rx)
| |
| |
gals0-tx gals1-tx (Global Async Local Sync tx)
| | Some SoCs may have GALS.
+--------+
|
SMI Common(Smart Multimedia Interface Common)
|
+----------------+-------
| |
| gals-rx There may be GALS in some larbs.
| |
| |
| gals-tx
| |
SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
(display) (vdec)
| |
| |
+-----+-----+ +----+----+
| | | | | |
| | |... | | | ... There are different ports in each larb.
| | | | | |
OVL0 RDMA0 WDMA0 MC PP VLD
As above, The Multimedia HW will go through SMI and M4U while it
access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
smi local arbiter and smi common. It will control whether the Multimedia
HW should go though the m4u for translation or bypass it and talk
directly with EMI. And also SMI help control the power domain and clocks for
each local arbiter.
Normally we specify a local arbiter(larb) for each multimedia HW
like display, video decode, and camera. And there are different ports
in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.
In some SoCs, there may be a GALS(Global Async Local Sync) module between
smi-common and m4u, and additional GALS module between smi-larb and
smi-common. GALS can been seen as a "asynchronous fifo" which could help
synchronize for the modules in different clock frequency.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt2701-m4u # generation one
- mediatek,mt2712-m4u # generation two
- mediatek,mt6779-m4u # generation two
- mediatek,mt8167-m4u # generation two
- mediatek,mt8173-m4u # generation two
- mediatek,mt8183-m4u # generation two
- mediatek,mt8192-m4u # generation two
- description: mt7623 generation one
items:
- const: mediatek,mt7623-m4u
- const: mediatek,mt2701-m4u
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: bclk is the block clock.
clock-names:
items:
- const: bclk
mediatek,larbs:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 32
description: |
List of phandle to the local arbiters in the current Socs.
Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
according to the local arbiter index, like larb0, larb1, larb2...
'#iommu-cells':
const: 1
description: |
This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
defined in
dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
dt-binding/memory/mt2712-larb-port.h for mt2712,
dt-binding/memory/mt6779-larb-port.h for mt6779,
dt-binding/memory/mt8167-larb-port.h for mt8167,
dt-binding/memory/mt8173-larb-port.h for mt8173,
dt-binding/memory/mt8183-larb-port.h for mt8183,
dt-binding/memory/mt8192-larb-port.h for mt8192.
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- mediatek,larbs
- '#iommu-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-m4u
- mediatek,mt2712-m4u
- mediatek,mt8173-m4u
- mediatek,mt8192-m4u
then:
required:
- clocks
- if:
properties:
compatible:
enum:
- mediatek,mt8192-m4u
then:
required:
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
iommu: iommu@10205000 {
compatible = "mediatek,mt8173-m4u";
reg = <0x10205000 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,larbs = <&larb0 &larb1 &larb2
&larb3 &larb4 &larb5>;
#iommu-cells = <1>;
};
- |
#include <dt-bindings/memory/mt8173-larb-port.h>
/* Example for a client device */
display {
compatible = "mediatek,mt8173-disp";
iommus = <&iommu M4U_PORT_DISP_OVL0>,
<&iommu M4U_PORT_DISP_RDMA0>;
};

50
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
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@@ -1,50 +0,0 @@
SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
Mediatek SMI have two generations of HW architecture, here is the list
which generation the SoCs use:
generation 1: mt2701 and mt7623.
generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
for generation 1, the register is at smi ao base(smi always on register
base). Besides that, the smi async clock should be prepared and enabled for
SMI generation 1 to transform the smi clock into emi clock domain, but that is
not needed for SMI generation 2.
Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-common"
"mediatek,mt2712-smi-common"
"mediatek,mt6779-smi-common"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8167-smi-common"
"mediatek,mt8173-smi-common"
"mediatek,mt8183-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
for generation 2 smi HW as follows:
- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
the register.
- "smi" : It's the clock for transfer data and command.
They may be the same if both source clocks are the same.
- "async" : asynchronous clock, it help transform the smi clock into the emi
clock domain, this clock is only needed by generation 1 smi HW.
and these 2 option clocks for generation 2 smi HW:
- "gals0": the path0 clock of GALS(Global Async Local Sync).
- "gals1": the path1 clock of GALS(Global Async Local Sync).
Here is the list which has this GALS: mt6779 and mt8183.
Example:
smi_common: smi@14022000 {
compatible = "mediatek,mt8173-smi-common";
reg = <0 0x14022000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>;
clock-names = "apb", "smi";
};

140
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml Normal file
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@@ -0,0 +1,140 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SMI (Smart Multimedia Interface) Common
maintainers:
- Yong Wu <yong.wu@mediatek.com>
description: |
The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
MediaTek SMI have two generations of HW architecture, here is the list
which generation the SoCs use:
generation 1: mt2701 and mt7623.
generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
for generation 1, the register is at smi ao base(smi always on register
base). Besides that, the smi async clock should be prepared and enabled for
SMI generation 1 to transform the smi clock into emi clock domain, but that is
not needed for SMI generation 2.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt2701-smi-common
- mediatek,mt2712-smi-common
- mediatek,mt6779-smi-common
- mediatek,mt8167-smi-common
- mediatek,mt8173-smi-common
- mediatek,mt8183-smi-common
- description: for mt7623
items:
- const: mediatek,mt7623-smi-common
- const: mediatek,mt2701-smi-common
reg:
maxItems: 1
power-domains:
maxItems: 1
clocks:
description: |
apb and smi are mandatory. the async is only for generation 1 smi HW.
gals(global async local sync) also is optional, see below.
minItems: 2
maxItems: 4
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
- description: smi is the clock for transfer data and command.
- description: async is asynchronous clock, it help transform the smi
clock into the emi clock domain.
- description: gals0 is the path0 clock of gals.
- description: gals1 is the path1 clock of gals.
clock-names:
minItems: 2
maxItems: 4
required:
- compatible
- reg
- power-domains
- clocks
- clock-names
allOf:
- if: # only for gen1 HW
properties:
compatible:
contains:
enum:
- mediatek,mt2701-smi-common
then:
properties:
clock:
items:
minItems: 3
maxItems: 3
clock-names:
items:
- const: apb
- const: smi
- const: async
- if: # for gen2 HW that have gals
properties:
compatible:
enum:
- mediatek,mt6779-smi-common
- mediatek,mt8183-smi-common
then:
properties:
clock:
items:
minItems: 4
maxItems: 4
clock-names:
items:
- const: apb
- const: smi
- const: gals0
- const: gals1
else: # for gen2 HW that don't have gals
properties:
clock:
items:
minItems: 2
maxItems: 2
clock-names:
items:
- const: apb
- const: smi
additionalProperties: false
examples:
- |+
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
smi_common: smi@14022000 {
compatible = "mediatek,mt8173-smi-common";
reg = <0x14022000 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>;
clock-names = "apb", "smi";
};

50
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
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@@ -1,50 +0,0 @@
SMI (Smart Multimedia Interface) Local Arbiter
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-larb"
"mediatek,mt2712-smi-larb"
"mediatek,mt6779-smi-larb"
"mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
"mediatek,mt8167-smi-larb"
"mediatek,mt8173-smi-larb"
"mediatek,mt8183-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
- clock-names: must contain 2 entries, as follows:
- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
the register.
- "smi" : It's the clock for transfer data and command.
and this optional clock name:
- "gals": the clock for GALS(Global Async Local Sync).
Here is the list which has this GALS: mt8183.
Required property for mt2701, mt2712, mt6779, mt7623 and mt8167:
- mediatek,larb-id :the hardware id of this larb.
Example:
larb1: larb@16010000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
clocks = <&vdecsys CLK_VDEC_CKEN>,
<&vdecsys CLK_VDEC_LARB_CKEN>;
clock-names = "apb", "smi";
};
Example for mt2701:
larb0: larb@14010000 {
compatible = "mediatek,mt2701-smi-larb";
reg = <0 0x14010000 0 0x1000>;
mediatek,smi = <&smi_common>;
mediatek,larb-id = <0>;
clocks = <&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB0>;
clock-names = "apb", "smi";
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};

130
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml Normal file
View File

@@ -0,0 +1,130 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SMI (Smart Multimedia Interface) Local Arbiter
maintainers:
- Yong Wu <yong.wu@mediatek.com>
description: |
The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
properties:
compatible:
oneOf:
- enum:
- mediatek,mt2701-smi-larb
- mediatek,mt2712-smi-larb
- mediatek,mt6779-smi-larb
- mediatek,mt8167-smi-larb
- mediatek,mt8173-smi-larb
- mediatek,mt8183-smi-larb
- description: for mt7623
items:
- const: mediatek,mt7623-smi-larb
- const: mediatek,mt2701-smi-larb
reg:
maxItems: 1
clocks:
description: |
apb and smi are mandatory. gals(global async local sync) is optional.
minItems: 2
maxItems: 3
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
- description: smi is the clock for transfer data and command.
- description: the clock for gals.
clock-names:
minItems: 2
maxItems: 3
power-domains:
maxItems: 1
mediatek,smi:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: a phandle to the smi_common node.
mediatek,larb-id:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 31
description: the hardware id of this larb. It's only required when this
hardward id is not consecutive from its M4U point of view.
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
allOf:
- if: # HW has gals
properties:
compatible:
enum:
- mediatek,mt8183-smi-larb
then:
properties:
clock:
items:
minItems: 3
maxItems: 3
clock-names:
items:
- const: apb
- const: smi
- const: gals
else:
properties:
clock:
items:
minItems: 2
maxItems: 2
clock-names:
items:
- const: apb
- const: smi
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-smi-larb
- mediatek,mt2712-smi-larb
- mediatek,mt6779-smi-larb
- mediatek,mt8167-smi-larb
then:
required:
- mediatek,larb-id
additionalProperties: false
examples:
- |+
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
larb1: larb@16010000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0x16010000 0x1000>;
mediatek,smi = <&smi_common>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
clocks = <&vdecsys CLK_VDEC_CKEN>,
<&vdecsys CLK_VDEC_LARB_CKEN>;
clock-names = "apb", "smi";
};

2
Documentation/devicetree/bindings/net/ethernet-controller.yaml
View File

@@ -49,7 +49,7 @@ properties:
description:
Reference to an nvmem node for the MAC address
nvmem-cells-names:
nvmem-cell-names:
const: mac-address
phy-connection-type:

10
Documentation/devicetree/bindings/reserved-memory/ramoops.txt
View File

@@ -42,8 +42,14 @@ Optional properties:
- pmsg-size: size in bytes of log buffer reserved for userspace messages
(defaults to 0: disabled)
- unbuffered: if present, use unbuffered mappings to map the reserved region
(defaults to buffered mappings)
- mem-type: if present, sets the type of mapping is to be used to map the
reserved region. mem-type: 0 = write-combined (default), 1 = unbuffered,
2 = cached.
- unbuffered: deprecated, use mem_type instead. if present, and mem_type is
not specified, it is equivalent to mem_type = 1 and uses unbuffered mappings
to map the reserved region (defaults to buffered mappings mem_type = 0). If
both are specified -- "mem_type" overrides "unbuffered".
- max-reason: if present, sets maximum type of kmsg dump reasons to store
(defaults to 2: log Oopses and Panics). This can be set to INT_MAX to

2
Documentation/filesystems/OWNERS Normal file
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@@ -0,0 +1,2 @@
# include OWNERS from the authoritative android-mainline branch
include kernel/common:android-mainline:/Documentation/filesystems/OWNERS

3
Documentation/trace/ftrace.rst
View File

@@ -76,6 +76,9 @@ it::
All files located in the tracefs file system will be located in that
debugfs file system directory as well.
In order to not automount tracefs in the debugfs filesystem, enable the
defconfig option CONFIG_TRACEFS_DISABLE_AUTOMOUNT.
.. attention::
Any selected ftrace option will also create the tracefs file system.

1
Documentation/userspace-api/media/v4l/common.rst
View File

@@ -50,6 +50,7 @@ applicable to all devices.
ext-ctrls-fm-tx
ext-ctrls-fm-rx
ext-ctrls-detect
ext-ctrls-colorimetry
fourcc
format
planar-apis

81
Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
View File

@@ -674,11 +674,64 @@ enum v4l2_mpeg_video_frame_skip_mode -
is currently displayed (decoded). This value is reset to 0 whenever
the decoder is started.
``V4L2_CID_MPEG_VIDEO_DEC_CONCEAL_COLOR (integer64)``
This control sets the conceal color in YUV color space. It describes
the client preference of the error conceal color in case of an error
where the reference frame is missing. The decoder should fill the
reference buffer with the preferred color and use it for future
decoding. The control is using 16 bits per channel.
Applicable to decoders.
.. flat-table::
:header-rows: 0
:stub-columns: 0
* -
- 8bit format
- 10bit format
- 12bit format
* - Y luminance
- Bit 0:7
- Bit 0:9
- Bit 0:11
* - Cb chrominance
- Bit 16:23
- Bit 16:25
- Bit 16:27
* - Cr chrominance
- Bit 32:39
- Bit 32:41
- Bit 32:43
* - Must be zero
- Bit 48:63
- Bit 48:63
- Bit 48:63
``V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (boolean)``
If enabled the decoder expects to receive a single slice per buffer,
otherwise the decoder expects a single frame in per buffer.
Applicable to the decoder, all codecs.
``V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE (boolean)``
If the display delay is enabled then the decoder is forced to return
a CAPTURE buffer (decoded frame) after processing a certain number
of OUTPUT buffers. The delay can be set through
``V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY``. This
feature can be used for example for generating thumbnails of videos.
Applicable to the decoder.
``V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY (integer)``
Display delay value for decoder. The decoder is forced to
return a decoded frame after the set 'display delay' number of
frames. If this number is low it may result in frames returned out
of display order, in addition the hardware may still be using the
returned buffer as a reference picture for subsequent frames.
``V4L2_CID_MPEG_VIDEO_AU_DELIMITER (boolean)``
If enabled then, AUD (Access Unit Delimiter) NALUs will be generated.
That could be useful to find the start of a frame without having to
fully parse each NALU. Applicable to the H264 and HEVC encoders.
``V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (boolean)``
Enable writing sample aspect ratio in the Video Usability
Information. Applicable to the H264 encoder.
@@ -2788,6 +2841,11 @@ MFC 5.1 Control IDs
feature can be used for example for generating thumbnails of videos.
Applicable to the H264 decoder.
.. note::
This control is deprecated. Use the standard
``V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE`` control instead.
``V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (integer)``
Display delay value for H264 decoder. The decoder is forced to
return a decoded frame after the set 'display delay' number of
@@ -2795,6 +2853,11 @@ MFC 5.1 Control IDs
of display order, in addition the hardware may still be using the
returned buffer as a reference picture for subsequent frames.
.. note::
This control is deprecated. Use the standard
``V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY`` control instead.
``V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (integer)``
The number of reference pictures used for encoding a P picture.
Applicable to the H264 encoder.
@@ -4459,3 +4522,21 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
so this has to come from client.
This is applicable to H264 and valid Range is from 0 to 63.
Source Rec. ITU-T H.264 (06/2019); G.7.4.1.1, G.8.8.1.
``V4L2_CID_MPEG_VIDEO_LTR_COUNT (integer)``
Specifies the maximum number of Long Term Reference (LTR) frames at any
given time that the encoder can keep.
This is applicable to the H264 and HEVC encoders.
``V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX (integer)``
After setting this control the frame that will be queued next
will be marked as a Long Term Reference (LTR) frame
and given this LTR index which ranges from 0 to LTR_COUNT-1.
This is applicable to the H264 and HEVC encoders.
Source Rec. ITU-T H.264 (06/2019); Table 7.9
``V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES (bitmask)``
Specifies the Long Term Reference (LTR) frame(s) to be used for
encoding the next frame queued after setting this control.
This provides a bitmask which consists of bits [0, LTR_COUNT-1].
This is applicable to the H264 and HEVC encoders.

22
Documentation/userspace-api/media/v4l/ext-ctrls-colorimetry.rst Normal file
View File

@@ -0,0 +1,22 @@
.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
.. _colorimetry-controls:
*****************************
Colorimetry Control Reference
*****************************
The Colorimetry class includes controls for High Dynamic Range
imaging for representing colors in digital images and video. The
controls should be used for video and image encoding and decoding
as well as in HDMI receivers and transmitters.
Colorimetry Control IDs
-----------------------
.. _colorimetry-control-id:
``V4L2_CID_COLORIMETRY_CLASS (class)``
The Colorimetry class descriptor. Calling
:ref:`VIDIOC_QUERYCTRL` for this control will
return a description of this control class.

4
Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst
View File

@@ -358,6 +358,10 @@ still cause this situation.
- 0xa20000
- The class containing RF tuner controls. These controls are
described in :ref:`rf-tuner-controls`.
* - ``V4L2_CTRL_CLASS_COLORIMETRY``
- 0xa50000
- The class containing colorimetry controls. These controls are
described in :ref:`colorimetry-controls`.
Return Value
============

6
Documentation/virt/kvm/api.rst
View File

@@ -4815,8 +4815,10 @@ If an MSR access is not permitted through the filtering, it generates a
allows user space to deflect and potentially handle various MSR accesses
into user space.
If a vCPU is in running state while this ioctl is invoked, the vCPU may
experience inconsistent filtering behavior on MSR accesses.
Note, invoking this ioctl with a vCPU is running is inherently racy. However,
KVM does guarantee that vCPUs will see either the previous filter or the new
filter, e.g. MSRs with identical settings in both the old and new filter will
have deterministic behavior.
5. The kvm_run structure

2
Documentation/vm/page_owner.rst
View File

@@ -47,7 +47,7 @@ size change due to this facility.
text data bss dec hex filename
48800 2445 644 51889 cab1 mm/page_alloc.o
6574 108 29 6711 1a37 mm/page_owner.o
6662 108 29 6799 1a8f mm/page_owner.o
1025 8 8 1041 411 mm/page_ext.o
Although, roughly, 8 KB code is added in total, page_alloc.o increase by

50
Makefile
View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 5
PATCHLEVEL = 10
SUBLEVEL = 26
SUBLEVEL = 31
EXTRAVERSION =
NAME = Dare mighty things
@@ -225,6 +225,20 @@ export KBUILD_CHECKSRC KBUILD_EXTMOD
extmod-prefix = $(if $(KBUILD_EXTMOD),$(KBUILD_EXTMOD)/)
# ANDROID: set up mixed-build support. mixed-build allows device kernel modules
# to be compiled against a GKI kernel. This approach still uses the headers and
# Kbuild from device kernel, so care must be taken to ensure that those headers match.
ifdef KBUILD_MIXED_TREE
# Need vmlinux.symvers for modpost and System.map for depmod, check whether they exist in KBUILD_MIXED_TREE
required_mixed_files=vmlinux.symvers System.map
$(if $(filter-out $(words $(required_mixed_files)), \
$(words $(wildcard $(add-prefix $(KBUILD_MIXED_TREE)/,$(required_mixed_files))))),,\
$(error KBUILD_MIXED_TREE=$(KBUILD_MIXED_TREE) doesn't contain $(required_mixed_files)))
endif
mixed-build-prefix = $(if $(KBUILD_MIXED_TREE),$(KBUILD_MIXED_TREE)/)
export KBUILD_MIXED_TREE
ifeq ($(abs_srctree),$(abs_objtree))
# building in the source tree
srctree := .
@@ -265,7 +279,8 @@ no-dot-config-targets := $(clean-targets) \
$(version_h) headers headers_% archheaders archscripts \
%asm-generic kernelversion %src-pkg dt_binding_check \
outputmakefile
no-sync-config-targets := $(no-dot-config-targets) %install kernelrelease
no-sync-config-targets := $(no-dot-config-targets) %install kernelrelease \
image_name
single-targets := %.a %.i %.ko %.lds %.ll %.lst %.mod %.o %.s %.symtypes %/
config-build :=
@@ -654,11 +669,13 @@ drivers-y += net/ virt/
libs-y := lib/
endif # KBUILD_EXTMOD
ifndef KBUILD_MIXED_TREE
# The all: target is the default when no target is given on the
# command line.
# This allow a user to issue only 'make' to build a kernel including modules
# Defaults to vmlinux, but the arch makefile usually adds further targets
all: vmlinux
endif
CFLAGS_GCOV := -fprofile-arcs -ftest-coverage \
$(call cc-option,-fno-tree-loop-im) \
@@ -1022,7 +1039,7 @@ LDFLAGS_vmlinux += $(call ld-option, -X,)
endif
ifeq ($(CONFIG_RELR),y)
LDFLAGS_vmlinux += --pack-dyn-relocs=relr
LDFLAGS_vmlinux += --pack-dyn-relocs=relr --use-android-relr-tags
endif
# We never want expected sections to be placed heuristically by the
@@ -1128,6 +1145,17 @@ ifdef CONFIG_STACK_VALIDATION
endif
endif
PHONY += resolve_btfids_clean
resolve_btfids_O = $(abspath $(objtree))/tools/bpf/resolve_btfids
# tools/bpf/resolve_btfids directory might not exist
# in output directory, skip its clean in that case
resolve_btfids_clean:
ifneq ($(wildcard $(resolve_btfids_O)),)
$(Q)$(MAKE) -sC $(srctree)/tools/bpf/resolve_btfids O=$(resolve_btfids_O) clean
endif
ifdef CONFIG_BPF
ifdef CONFIG_DEBUG_INFO_BTF
ifeq ($(has_libelf),1)
@@ -1243,8 +1271,10 @@ cmd_link-vmlinux = \
$(CONFIG_SHELL) $< "$(LD)" "$(KBUILD_LDFLAGS)" "$(LDFLAGS_vmlinux)"; \
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
ifndef KBUILD_MIXED_TREE
vmlinux: scripts/link-vmlinux.sh autoksyms_recursive $(vmlinux-deps) FORCE
+$(call if_changed,link-vmlinux)
endif
targets := vmlinux
@@ -1460,7 +1490,9 @@ endif
# using awk while concatenating to the final file.
PHONY += modules
modules: $(if $(KBUILD_BUILTIN),vmlinux) modules_check modules_prepare
# if KBUILD_BUILTIN && !KBUILD_MIXED_TREE, depend on vmlinux
modules: $(if $(KBUILD_BUILTIN), $(if $(KBUILD_MIXED_TREE),,vmlinux))
modules: modules_check modules_prepare
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
PHONY += modules_check
@@ -1494,8 +1526,8 @@ _modinst_:
ln -s $(CURDIR) $(MODLIB)/build ; \
fi
@sed 's:^:kernel/:' modules.order > $(MODLIB)/modules.order
@cp -f modules.builtin $(MODLIB)/
@cp -f $(objtree)/modules.builtin.modinfo $(MODLIB)/
@cp -f $(mixed-build-prefix)modules.builtin $(MODLIB)/
@cp -f $(or $(mixed-build-prefix),$(objtree)/)modules.builtin.modinfo $(MODLIB)/
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modinst
# This depmod is only for convenience to give the initial
@@ -1563,7 +1595,7 @@ vmlinuxclean:
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/link-vmlinux.sh clean
$(Q)$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) clean)
clean: archclean vmlinuxclean
clean: archclean vmlinuxclean resolve_btfids_clean
# mrproper - Delete all generated files, including .config
#
@@ -1874,7 +1906,7 @@ descend: $(build-dirs)
$(build-dirs): prepare
$(Q)$(MAKE) $(build)=$@ \
single-build=$(if $(filter-out $@/, $(filter $@/%, $(KBUILD_SINGLE_TARGETS))),1) \
need-builtin=1 need-modorder=1
$(if $(KBUILD_MIXED_TREE),,need-builtin=1) need-modorder=1
clean-dirs := $(addprefix _clean_, $(clean-dirs))
PHONY += $(clean-dirs) clean
@@ -2008,7 +2040,7 @@ quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files))
# Run depmod only if we have System.map and depmod is executable
quiet_cmd_depmod = DEPMOD $(KERNELRELEASE)
cmd_depmod = $(CONFIG_SHELL) $(srctree)/scripts/depmod.sh $(DEPMOD) \
$(KERNELRELEASE)
$(KERNELRELEASE) $(mixed-build-prefix)
# read saved command lines for existing targets
existing-targets := $(wildcard $(sort $(targets)))

2
OWNERS Normal file
View File

@@ -0,0 +1,2 @@
# include OWNERS from the authoritative android-mainline branch
include kernel/common:android-mainline:/OWNERS

12
android/OWNERS Normal file
View File

@@ -0,0 +1,12 @@
# If we ever add another OWNERS above this directory, it's likely to be
# more permissive, so don't inherit from it
set noparent
adelva@google.com
maennich@google.com
saravanak@google.com
sspatil@google.com
tkjos@google.com
willmcvicker@google.com
# Downstream boards maintained directly in this manifest branch
per-file abi_gki_aarch64_cuttlefish = adelva@google.com, rammuthiah@google.com
per-file abi_gki_aarch64_goldfish = rkir@google.com

138074
android/abi_gki_aarch64.xml
View File

File diff suppressed because it is too large Load Diff

9
android/abi_gki_aarch64_core Normal file
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@@ -0,0 +1,9 @@
[abi_symbol_list]
# commonly used symbols
ieee802154_alloc_hw
ieee802154_free_hw
ieee802154_register_hw
ieee802154_rx_irqsafe
ieee802154_unregister_hw
ieee802154_wake_queue
ieee802154_xmit_complete

2052
android/abi_gki_aarch64_generic Normal file
View File

File diff suppressed because it is too large Load Diff

51
android/abi_gki_aarch64_qcom
View File

@@ -28,6 +28,9 @@
amba_bustype
amba_driver_register
amba_driver_unregister
android_debug_per_cpu_symbol
android_debug_symbol
android_rvh_probe_register
anon_inode_getfile
__arch_clear_user
__arch_copy_from_user
@@ -231,6 +234,7 @@
consume_skb
contig_page_data
_copy_from_iter_full
copy_from_kernel_nofault
__cpu_active_mask
cpu_bit_bitmap
cpufreq_cpu_get
@@ -340,6 +344,7 @@
debugfs_remove
dec_zone_page_state
default_llseek
deferred_free
delayed_work_timer_fn
del_gendisk
del_timer
@@ -362,6 +367,7 @@
devfreq_suspend_device
dev_fwnode
__dev_get_by_index
dev_get_by_index
dev_get_by_name
dev_get_regmap
device_add
@@ -506,6 +512,7 @@
dev_pm_opp_unregister_notifier
dev_pm_qos_add_notifier
dev_pm_qos_add_request
dev_pm_qos_read_value
dev_pm_qos_remove_notifier
dev_pm_qos_remove_request
dev_pm_qos_update_request
@@ -1044,8 +1051,11 @@
iio_channel_get_all
iio_read_channel_processed
import_iovec
in4_pton
in6_pton
inc_zone_page_state
in_egroup_p
inet_proto_csum_replace4
init_dummy_netdev
init_iova_domain
init_net
@@ -1079,6 +1089,10 @@
input_unregister_handle
input_unregister_handler
int_sqrt
interval_tree_insert
interval_tree_iter_first
interval_tree_iter_next
interval_tree_remove
invalidate_mapping_pages
iomem_resource
iommu_alloc_resv_region
@@ -1120,9 +1134,11 @@
iounmap
__iowrite32_copy
ip_compute_csum
ipi_desc_get
iput
__ipv6_addr_type
ipv6_ext_hdr
ipv6_find_hdr
ipv6_skip_exthdr
irq_chip_ack_parent
irq_chip_disable_parent
@@ -1228,6 +1244,9 @@
kset_create_and_add
ksize
ksoftirqd
kstat
kstat_irqs_cpu
kstat_irqs_usr
kstrdup
kstrdup_const
kstrndup
@@ -1274,6 +1293,7 @@
ktime_get_seconds
ktime_get_with_offset
kvfree
kvfree_call_rcu
kvmalloc_node
led_classdev_flash_register_ext
led_classdev_flash_unregister
@@ -1289,6 +1309,8 @@
__local_bh_enable_ip
__lock_page
lock_sock_nested
log_buf_addr_get
log_buf_len_get
__log_post_read_mmio
__log_read_mmio
__log_write_mmio
@@ -1408,6 +1430,8 @@
nonseekable_open
noop_llseek
nr_cpu_ids
nr_ipi_get
nr_irqs
ns_capable
nsecs_to_jiffies
ns_to_timespec64
@@ -1555,6 +1579,7 @@
pci_bus_type
pci_clear_master
pci_d3cold_disable
pci_dev_present
pci_device_group
pci_disable_device
pci_disable_msi
@@ -1594,6 +1619,7 @@
percpu_down_write
__percpu_init_rwsem
__per_cpu_offset
per_cpu_ptr_to_phys
percpu_up_write
perf_aux_output_begin
perf_aux_output_end
@@ -1806,7 +1832,6 @@
refcount_dec_and_lock
refcount_dec_not_one
refcount_warn_saturate
__refrigerator
regcache_cache_only
regcache_mark_dirty
regcache_sync
@@ -1815,12 +1840,14 @@
__register_chrdev
register_chrdev_region
register_console
register_die_notifier
register_ftrace_export
register_inet6addr_notifier
register_inetaddr_notifier
register_kprobe
register_kretprobe
register_memory_notifier
register_module_notifier
register_netdev
register_netdevice
register_netdevice_notifier
@@ -1947,12 +1974,14 @@
rtnl_lock
rtnl_register_module
rtnl_trylock
rtnl_unicast
rtnl_unlock
rtnl_unregister
runqueues
sched_clock
sched_feat_keys
sched_feat_names
sched_setattr
sched_set_fifo
sched_set_fifo_low
sched_set_normal
@@ -1997,6 +2026,7 @@
sdhci_set_bus_width
sdhci_set_power_noreg
sdhci_setup_host
seq_buf_printf
seq_hex_dump
seq_lseek
seq_open
@@ -2055,6 +2085,7 @@
skb_copy_expand
skb_dequeue
skb_dequeue_tail
skb_ensure_writable
skb_free_datagram
__skb_get_hash
__skb_gso_segment
@@ -2150,6 +2181,7 @@
sock_queue_rcv_skb
sock_register
sock_release
sock_setsockopt
sock_unregister
softnet_data
sort
@@ -2240,6 +2272,7 @@
sysfs_create_group
sysfs_create_groups
sysfs_create_link
sysfs_emit
__sysfs_match_string
sysfs_notify
sysfs_remove_bin_file
@@ -2275,7 +2308,9 @@
thermal_cooling_device_unregister
thermal_of_cooling_device_register
thermal_pressure
thermal_zone_device_enable
thermal_zone_device_register
thermal_zone_device_unregister
thermal_zone_device_update
thermal_zone_get_slope
thermal_zone_get_temp
@@ -2298,11 +2333,13 @@
trace_event_reg
trace_handle_return
__traceiter_cpu_frequency
__traceiter_gpu_mem_total
__tracepoint_android_rvh_account_irq
__tracepoint_android_rvh_build_perf_domains
__tracepoint_android_rvh_can_migrate_task
__tracepoint_android_rvh_check_preempt_wakeup
__tracepoint_android_rvh_cpu_cgroup_attach
__tracepoint_android_rvh_cpu_cgroup_online
__tracepoint_android_rvh_cpufreq_transition
__tracepoint_android_rvh_dequeue_task
__tracepoint_android_rvh_enqueue_task
@@ -2317,6 +2354,7 @@
__tracepoint_android_rvh_place_entity
__tracepoint_android_rvh_preempt_disable
__tracepoint_android_rvh_preempt_enable
__tracepoint_android_rvh_replace_next_task_fair
__tracepoint_android_rvh_resume_cpus
__tracepoint_android_rvh_sched_balance_rt
__tracepoint_android_rvh_sched_cpu_dying
@@ -2343,11 +2381,19 @@
__tracepoint_android_rvh_update_misfit_status
__tracepoint_android_rvh_wake_up_new_task
__tracepoint_android_vh_allow_domain_state
__tracepoint_android_vh_binder_restore_priority
__tracepoint_android_vh_binder_set_priority
__tracepoint_android_vh_binder_transaction_init
__tracepoint_android_vh_binder_wakeup_ilocked
__tracepoint_android_vh_cpu_idle_enter
__tracepoint_android_vh_cpu_idle_exit
__tracepoint_android_vh_dump_throttled_rt_tasks
__tracepoint_android_vh_freq_table_limits
__tracepoint_android_vh_ftrace_dump_buffer
__tracepoint_android_vh_ftrace_format_check
__tracepoint_android_vh_ftrace_oops_enter
__tracepoint_android_vh_ftrace_oops_exit
__tracepoint_android_vh_ftrace_size_check
__tracepoint_android_vh_iommu_setup_dma_ops
__tracepoint_android_vh_ipi_stop
__tracepoint_android_vh_jiffies_update
@@ -2361,6 +2407,7 @@
__tracepoint_cpu_frequency
__tracepoint_cpu_frequency_limits
__tracepoint_cpu_idle
__tracepoint_gpu_mem_total
__tracepoint_ipi_entry
__tracepoint_ipi_raise
__tracepoint_irq_handler_entry
@@ -2453,11 +2500,13 @@
__unregister_chrdev
unregister_chrdev_region
unregister_console
unregister_die_notifier
unregister_ftrace_export
unregister_inet6addr_notifier
unregister_inetaddr_notifier
unregister_kprobe
unregister_kretprobe
unregister_module_notifier
unregister_netdev
unregister_netdevice_many
unregister_netdevice_notifier

59
android/abi_gki_aarch64_virtual_device
View File

@@ -1,5 +1,6 @@
[abi_symbol_list]
# commonly used symbols
alloc_anon_inode
__alloc_disk_node
alloc_etherdev_mqs
__alloc_pages_nodemask
@@ -39,6 +40,7 @@
__check_object_size
__class_create
class_destroy
__ClearPageMovable
clk_disable
clk_enable
clk_get_rate
@@ -116,7 +118,6 @@
free_netdev
__free_pages
free_pages
freezing_slow_path
fs_bio_set
get_device
__get_free_pages
@@ -130,6 +131,7 @@
idr_alloc
idr_destroy
idr_remove
init_pseudo
__init_rwsem
__init_swait_queue_head
init_timer_key
@@ -145,11 +147,15 @@
input_unregister_device
__ioremap
iounmap
iput
jiffies
jiffies_to_msecs
kasan_flag_enabled
kern_mount
kern_unmount
kfree
kfree_skb
kill_anon_super
kimage_voffset
__kmalloc
kmalloc_caches
@@ -170,7 +176,6 @@
kstrtoint
kstrtouint
kstrtoull
kthread_create_on_node
ktime_get
ktime_get_mono_fast_ns
ktime_get_raw_ts64
@@ -204,6 +209,7 @@
__mutex_init
mutex_lock
mutex_lock_interruptible
mutex_trylock
mutex_unlock
netdev_err
netdev_info
@@ -286,7 +292,6 @@
__rcu_read_lock
__rcu_read_unlock
refcount_warn_saturate
__refrigerator
register_blkdev
register_netdev
register_netdevice
@@ -321,6 +326,7 @@
__serio_register_port
serio_unregister_driver
set_disk_ro
__SetPageMovable
sg_alloc_table
sg_free_table
sg_init_one
@@ -378,7 +384,6 @@
__sysfs_match_string
sysfs_remove_group
sysfs_remove_link
system_freezing_cnt
system_wq
trace_event_buffer_commit
trace_event_buffer_reserve
@@ -398,6 +403,7 @@
unregister_netdev
unregister_netdevice_notifier
unregister_netdevice_queue
unregister_shrinker
unregister_virtio_device
unregister_virtio_driver
up_read
@@ -429,7 +435,6 @@
vring_transport_features
wait_for_completion
__wake_up
wake_up_process
__warn_printk
# required by ambakmi.ko
@@ -482,9 +487,6 @@
of_clk_hw_simple_get
of_property_read_string
# required by deferred-free-helper.ko
sched_set_normal
# required by dummy-cpufreq.ko
cpufreq_generic_attr
cpufreq_register_driver
@@ -675,6 +677,7 @@
kobject_del
kobject_get
kstrtoll
kthread_create_on_node
kthread_parkme
kthread_should_park
kthread_should_stop
@@ -687,7 +690,6 @@
mempool_init
mempool_kfree
mempool_kmalloc
mutex_trylock
part_end_io_acct
part_start_io_acct
percpu_ref_exit
@@ -710,6 +712,7 @@
unregister_reboot_notifier
unregister_sysctl_table
vfs_fsync
wake_up_process
# required by nd_virtio.ko
bio_chain
@@ -732,9 +735,6 @@
netdev_pick_tx
pci_bus_type
# required by page_pool.ko
mod_node_page_state
# required by psmouse.ko
bus_register_notifier
bus_unregister_notifier
@@ -876,6 +876,11 @@
snd_pcm_hw_constraint_msbits
# required by system_heap.ko
deferred_free
dmabuf_page_pool_alloc
dmabuf_page_pool_create
dmabuf_page_pool_destroy
dmabuf_page_pool_free
dma_heap_add
dma_heap_get_dev
dma_heap_get_name
@@ -1084,6 +1089,24 @@
# required by virtio-rng.ko
wait_for_completion_killable
# required by virtio_balloon.ko
adjust_managed_page_count
all_vm_events
balloon_aops
balloon_page_alloc
balloon_page_dequeue
balloon_page_enqueue
init_on_free
page_reporting_register
page_reporting_unregister
register_oom_notifier
si_mem_available
si_meminfo
system_freezable_wq
unregister_oom_notifier
vm_event_states
vm_node_stat
# required by virtio_blk.ko
blk_execute_rq
blk_get_request
@@ -1116,6 +1139,7 @@
cdev_del
device_destroy
fasync_helper
freezing_slow_path
hvc_alloc
hvc_instantiate
hvc_kick
@@ -1125,10 +1149,12 @@
kill_fasync
pipe_lock
pipe_unlock
__refrigerator
__register_chrdev
single_open
single_release
__splice_from_pipe
system_freezing_cnt
__unregister_chrdev
# required by virtio_mmio.ko
@@ -1282,20 +1308,11 @@
vzalloc
# required by zsmalloc.ko
alloc_anon_inode
__ClearPageMovable
dec_zone_page_state
inc_zone_page_state
init_pseudo
iput
kern_mount
kern_unmount
kill_anon_super
__lock_page
page_mapping
_raw_read_lock
_raw_read_unlock
_raw_write_lock
_raw_write_unlock
__SetPageMovable
unregister_shrinker

2
arch/arm/OWNERS Normal file
View File

@@ -0,0 +1,2 @@
# include OWNERS from the authoritative android-mainline branch
include kernel/common:android-mainline:/arch/arm/OWNERS

3
arch/arm/boot/dts/am33xx.dtsi
View File

@@ -40,6 +40,9 @@
ethernet1 = &cpsw_emac1;
spi0 = &spi0;
spi1 = &spi1;
mmc0 = &mmc1;
mmc1 = &mmc2;
mmc2 = &mmc3;
};
cpus {

1
arch/arm/boot/dts/armada-385-turris-omnia.dts
View File

@@ -236,6 +236,7 @@
status = "okay";
compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
reg = <1>;
marvell,reg-init = <3 18 0 0x4985>;
/* irq is connected to &pcawan pin 7 */
};

8
arch/arm/boot/dts/at91-sam9x60ek.dts
View File

@@ -334,14 +334,6 @@
};
&pinctrl {
atmel,mux-mask = <
/* A B C */
0xFFFFFE7F 0xC0E0397F 0xEF00019D /* pioA */
0x03FFFFFF 0x02FC7E68 0x00780000 /* pioB */
0xffffffff 0xF83FFFFF 0xB800F3FC /* pioC */
0x003FFFFF 0x003F8000 0x00000000 /* pioD */
>;
adc {
pinctrl_adc_default: adc_default {
atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;

4
arch/arm/boot/dts/at91-sama5d27_som1.dtsi
View File

@@ -84,8 +84,8 @@
pinctrl-0 = <&pinctrl_macb0_default>;
phy-mode = "rmii";
ethernet-phy@0 {
reg = <0x0>;
ethernet-phy@7 {
reg = <0x7>;
interrupt-parent = <&pioA>;
interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";

2
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View File

@@ -432,6 +432,7 @@
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vdd_sd1_reg>;
status = "disabled";
};
@@ -441,5 +442,6 @@
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vdd_sd0_reg>;
status = "disabled";
};

1
arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts
View File

@@ -14,5 +14,6 @@
};
&gpmi {
fsl,use-minimum-ecc;
status = "okay";
};

9
arch/arm/boot/dts/sam9x60.dtsi
View File

@@ -606,6 +606,15 @@
compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
atmel,mux-mask = <
/* A B C */
0xffffffff 0xffe03fff 0xef00019d /* pioA */
0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
0xffffffff 0xffffffff 0xf83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
pioA: gpio@fffff400 {
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;

39
arch/arm/mach-omap2/omap-secure.c
View File

@@ -9,6 +9,7 @@
*/
#include <linux/arm-smccc.h>
#include <linux/cpu_pm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
@@ -20,6 +21,7 @@
#include "common.h"
#include "omap-secure.h"
#include "soc.h"
static phys_addr_t omap_secure_memblock_base;
@@ -213,3 +215,40 @@ void __init omap_secure_init(void)
{
omap_optee_init_check();
}
/*
* Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return
* address after MMU has been re-enabled after CPU1 has been woken up again.
* Otherwise the ROM code will attempt to use the earlier physical return
* address that got set with MMU off when waking up CPU1. Only used on secure
* devices.
*/
static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
{
switch (cmd) {
case CPU_CLUSTER_PM_EXIT:
omap_secure_dispatcher(OMAP4_PPA_SERVICE_0,
FLAG_START_CRITICAL,
0, 0, 0, 0, 0);
break;
default:
break;
}
return NOTIFY_OK;
}
static struct notifier_block secure_notifier_block = {
.notifier_call = cpu_notifier,
};
static int __init secure_pm_init(void)
{
if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx())
return 0;
cpu_pm_register_notifier(&secure_notifier_block);
return 0;
}
omap_arch_initcall(secure_pm_init);

1
arch/arm/mach-omap2/omap-secure.h
View File

@@ -50,6 +50,7 @@
#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
/* Secure PPA(Primary Protected Application) APIs */
#define OMAP4_PPA_SERVICE_0 0x21
#define OMAP4_PPA_L2_POR_INDEX 0x23
#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25

4
arch/arm/mach-omap2/pmic-cpcap.c
View File

@@ -246,10 +246,10 @@ int __init omap4_cpcap_init(void)
omap_voltage_register_pmic(voltdm, &omap443x_max8952_mpu);
if (of_machine_is_compatible("motorola,droid-bionic")) {
voltdm = voltdm_lookup("mpu");
voltdm = voltdm_lookup("core");
omap_voltage_register_pmic(voltdm, &omap_cpcap_core);
voltdm = voltdm_lookup("mpu");
voltdm = voltdm_lookup("iva");
omap_voltage_register_pmic(voltdm, &omap_cpcap_iva);
} else {
voltdm = voltdm_lookup("core");

75
arch/arm/mach-omap2/sr_device.c
View File

@@ -88,34 +88,26 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
extern struct omap_sr_data omap_sr_pdata[];
static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
static int __init sr_init_by_name(const char *name, const char *voltdm)
{
struct omap_sr_data *sr_data = NULL;
struct omap_volt_data *volt_data;
struct omap_smartreflex_dev_attr *sr_dev_attr;
static int i;
if (!strncmp(oh->name, "smartreflex_mpu_iva", 20) ||
!strncmp(oh->name, "smartreflex_mpu", 16))
if (!strncmp(name, "smartreflex_mpu_iva", 20) ||
!strncmp(name, "smartreflex_mpu", 16))
sr_data = &omap_sr_pdata[OMAP_SR_MPU];
else if (!strncmp(oh->name, "smartreflex_core", 17))
else if (!strncmp(name, "smartreflex_core", 17))
sr_data = &omap_sr_pdata[OMAP_SR_CORE];
else if (!strncmp(oh->name, "smartreflex_iva", 16))
else if (!strncmp(name, "smartreflex_iva", 16))
sr_data = &omap_sr_pdata[OMAP_SR_IVA];
if (!sr_data) {
pr_err("%s: Unknown instance %s\n", __func__, oh->name);
pr_err("%s: Unknown instance %s\n", __func__, name);
return -EINVAL;
}
sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
__func__, oh->name);
goto exit;
}
sr_data->name = oh->name;
sr_data->name = name;
if (cpu_is_omap343x())
sr_data->ip_type = 1;
else
@@ -136,10 +128,10 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
}
}
sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
sr_data->voltdm = voltdm_lookup(voltdm);
if (!sr_data->voltdm) {
pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
__func__, sr_dev_attr->sensor_voltdm_name);
__func__, voltdm);
goto exit;
}
@@ -160,6 +152,20 @@ exit:
return 0;
}
static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
{
struct omap_smartreflex_dev_attr *sr_dev_attr;
sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
__func__, oh->name);
return 0;
}
return sr_init_by_name(oh->name, sr_dev_attr->sensor_voltdm_name);
}
/*
* API to be called from board files to enable smartreflex
* autocompensation at init.
@@ -169,7 +175,42 @@ void __init omap_enable_smartreflex_on_init(void)
sr_enable_on_init = true;
}
static const char * const omap4_sr_instances[] = {
"mpu",
"iva",
"core",
};
static const char * const dra7_sr_instances[] = {
"mpu",
"core",
};
int __init omap_devinit_smartreflex(void)
{
const char * const *sr_inst;
int i, nr_sr = 0;
if (soc_is_omap44xx()) {
sr_inst = omap4_sr_instances;
nr_sr = ARRAY_SIZE(omap4_sr_instances);
} else if (soc_is_dra7xx()) {
sr_inst = dra7_sr_instances;
nr_sr = ARRAY_SIZE(dra7_sr_instances);
}
if (nr_sr) {
const char *name, *voltdm;
for (i = 0; i < nr_sr; i++) {
name = kasprintf(GFP_KERNEL, "smartreflex_%s", sr_inst[i]);
voltdm = sr_inst[i];
sr_init_by_name(name, voltdm);
}
return 0;
}
return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
}

294
arch/arm/probes/kprobes/test-arm.c
View File

@@ -55,25 +55,25 @@ void kprobe_arm_test_cases(void)
TEST_GROUP("Data-processing (register), (register-shifted register), (immediate)")
#define _DATA_PROCESSING_DNM(op,s,val) \
TEST_RR( op "eq" s " r0, r",1, VAL1,", r",2, val, "") \
TEST_RR( op "ne" s " r1, r",1, VAL1,", r",2, val, ", lsl #3") \
TEST_RR( op "cs" s " r2, r",3, VAL1,", r",2, val, ", lsr #4") \
TEST_RR( op "cc" s " r3, r",3, VAL1,", r",2, val, ", asr #5") \
TEST_RR( op "mi" s " r4, r",5, VAL1,", r",2, N(val),", asr #6") \
TEST_RR( op "pl" s " r5, r",5, VAL1,", r",2, val, ", ror #7") \
TEST_RR( op "vs" s " r6, r",7, VAL1,", r",2, val, ", rrx") \
TEST_R( op "vc" s " r6, r",7, VAL1,", pc, lsl #3") \
TEST_R( op "vc" s " r6, r",7, VAL1,", sp, lsr #4") \
TEST_R( op "vc" s " r6, pc, r",7, VAL1,", asr #5") \
TEST_R( op "vc" s " r6, sp, r",7, VAL1,", ror #6") \
TEST_RRR( op "hi" s " r8, r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")\
TEST_RRR( op "ls" s " r9, r",9, VAL1,", r",14,val, ", lsr r",7, 4,"")\
TEST_RRR( op "ge" s " r10, r",11,VAL1,", r",14,val, ", asr r",7, 5,"")\
TEST_RRR( op "lt" s " r11, r",11,VAL1,", r",14,N(val),", asr r",7, 6,"")\
TEST_RR( op "gt" s " r12, r13" ", r",14,val, ", ror r",14,7,"")\
TEST_RR( op "le" s " r14, r",0, val, ", r13" ", lsl r",14,8,"")\
TEST_R( op "eq" s " r0, r",11,VAL1,", #0xf5") \
TEST_R( op "ne" s " r11, r",0, VAL1,", #0xf5000000") \
TEST_RR( op s "eq r0, r",1, VAL1,", r",2, val, "") \
TEST_RR( op s "ne r1, r",1, VAL1,", r",2, val, ", lsl #3") \
TEST_RR( op s "cs r2, r",3, VAL1,", r",2, val, ", lsr #4") \
TEST_RR( op s "cc r3, r",3, VAL1,", r",2, val, ", asr #5") \
TEST_RR( op s "mi r4, r",5, VAL1,", r",2, N(val),", asr #6") \
TEST_RR( op s "pl r5, r",5, VAL1,", r",2, val, ", ror #7") \
TEST_RR( op s "vs r6, r",7, VAL1,", r",2, val, ", rrx") \
TEST_R( op s "vc r6, r",7, VAL1,", pc, lsl #3") \
TEST_R( op s "vc r6, r",7, VAL1,", sp, lsr #4") \
TEST_R( op s "vc r6, pc, r",7, VAL1,", asr #5") \
TEST_R( op s "vc r6, sp, r",7, VAL1,", ror #6") \
TEST_RRR( op s "hi r8, r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")\
TEST_RRR( op s "ls r9, r",9, VAL1,", r",14,val, ", lsr r",7, 4,"")\
TEST_RRR( op s "ge r10, r",11,VAL1,", r",14,val, ", asr r",7, 5,"")\
TEST_RRR( op s "lt r11, r",11,VAL1,", r",14,N(val),", asr r",7, 6,"")\
TEST_RR( op s "gt r12, r13" ", r",14,val, ", ror r",14,7,"")\
TEST_RR( op s "le r14, r",0, val, ", r13" ", lsl r",14,8,"")\
TEST_R( op s "eq r0, r",11,VAL1,", #0xf5") \
TEST_R( op s "ne r11, r",0, VAL1,", #0xf5000000") \
TEST_R( op s " r7, r",8, VAL2,", #0x000af000") \
TEST( op s " r4, pc" ", #0x00005a00")
@@ -104,23 +104,23 @@ void kprobe_arm_test_cases(void)
TEST_R( op " r",8, VAL2,", #0x000af000")
#define _DATA_PROCESSING_DM(op,s,val) \
TEST_R( op "eq" s " r0, r",1, val, "") \
TEST_R( op "ne" s " r1, r",1, val, ", lsl #3") \
TEST_R( op "cs" s " r2, r",3, val, ", lsr #4") \
TEST_R( op "cc" s " r3, r",3, val, ", asr #5") \
TEST_R( op "mi" s " r4, r",5, N(val),", asr #6") \
TEST_R( op "pl" s " r5, r",5, val, ", ror #7") \
TEST_R( op "vs" s " r6, r",10,val, ", rrx") \
TEST( op "vs" s " r7, pc, lsl #3") \
TEST( op "vs" s " r7, sp, lsr #4") \
TEST_RR( op "vc" s " r8, r",7, val, ", lsl r",0, 3,"") \
TEST_RR( op "hi" s " r9, r",9, val, ", lsr r",7, 4,"") \
TEST_RR( op "ls" s " r10, r",9, val, ", asr r",7, 5,"") \
TEST_RR( op "ge" s " r11, r",11,N(val),", asr r",7, 6,"") \
TEST_RR( op "lt" s " r12, r",11,val, ", ror r",14,7,"") \
TEST_R( op "gt" s " r14, r13" ", lsl r",14,8,"") \
TEST( op "eq" s " r0, #0xf5") \
TEST( op "ne" s " r11, #0xf5000000") \
TEST_R( op s "eq r0, r",1, val, "") \
TEST_R( op s "ne r1, r",1, val, ", lsl #3") \
TEST_R( op s "cs r2, r",3, val, ", lsr #4") \
TEST_R( op s "cc r3, r",3, val, ", asr #5") \
TEST_R( op s "mi r4, r",5, N(val),", asr #6") \
TEST_R( op s "pl r5, r",5, val, ", ror #7") \
TEST_R( op s "vs r6, r",10,val, ", rrx") \
TEST( op s "vs r7, pc, lsl #3") \
TEST( op s "vs r7, sp, lsr #4") \
TEST_RR( op s "vc r8, r",7, val, ", lsl r",0, 3,"") \
TEST_RR( op s "hi r9, r",9, val, ", lsr r",7, 4,"") \
TEST_RR( op s "ls r10, r",9, val, ", asr r",7, 5,"") \
TEST_RR( op s "ge r11, r",11,N(val),", asr r",7, 6,"") \
TEST_RR( op s "lt r12, r",11,val, ", ror r",14,7,"") \
TEST_R( op s "gt r14, r13" ", lsl r",14,8,"") \
TEST( op s "eq r0, #0xf5") \
TEST( op s "ne r11, #0xf5000000") \
TEST( op s " r7, #0x000af000") \
TEST( op s " r4, #0x00005a00")
@@ -166,10 +166,10 @@ void kprobe_arm_test_cases(void)
/* Data-processing with PC as a target and status registers updated */
TEST_UNSUPPORTED("movs pc, r1")
TEST_UNSUPPORTED("movs pc, r1, lsl r2")
TEST_UNSUPPORTED(__inst_arm(0xe1b0f211) " @movs pc, r1, lsl r2")
TEST_UNSUPPORTED("movs pc, #0x10000")
TEST_UNSUPPORTED("adds pc, lr, r1")
TEST_UNSUPPORTED("adds pc, lr, r1, lsl r2")
TEST_UNSUPPORTED(__inst_arm(0xe09ef211) " @adds pc, lr, r1, lsl r2")
TEST_UNSUPPORTED("adds pc, lr, #4")
/* Data-processing with SP as target */
@@ -352,7 +352,7 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe000029f) " @ mul r0, pc, r2")
TEST_UNSUPPORTED(__inst_arm(0xe0000f91) " @ mul r0, r1, pc")
TEST_RR( "muls r0, r",1, VAL1,", r",2, VAL2,"")
TEST_RR( "mullss r7, r",8, VAL2,", r",9, VAL2,"")
TEST_RR( "mulsls r7, r",8, VAL2,", r",9, VAL2,"")
TEST_R( "muls lr, r",4, VAL3,", r13")
TEST_UNSUPPORTED(__inst_arm(0xe01f0291) " @ muls pc, r1, r2")
@@ -361,7 +361,7 @@ void kprobe_arm_test_cases(void)
TEST_RR( "mla lr, r",1, VAL2,", r",2, VAL3,", r13")
TEST_UNSUPPORTED(__inst_arm(0xe02f3291) " @ mla pc, r1, r2, r3")
TEST_RRR( "mlas r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
TEST_RRR( "mlahis r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
TEST_RRR( "mlashi r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
TEST_RR( "mlas lr, r",1, VAL2,", r",2, VAL3,", r13")
TEST_UNSUPPORTED(__inst_arm(0xe03f3291) " @ mlas pc, r1, r2, r3")
@@ -394,7 +394,7 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe081f392) " @ umull pc, r1, r2, r3")
TEST_UNSUPPORTED(__inst_arm(0xe08f1392) " @ umull r1, pc, r2, r3")
TEST_RR( "umulls r0, r1, r",2, VAL1,", r",3, VAL2,"")
TEST_RR( "umulllss r7, r8, r",9, VAL2,", r",10, VAL1,"")
TEST_RR( "umullsls r7, r8, r",9, VAL2,", r",10, VAL1,"")
TEST_R( "umulls lr, r12, r",11,VAL3,", r13")
TEST_UNSUPPORTED(__inst_arm(0xe091f392) " @ umulls pc, r1, r2, r3")
TEST_UNSUPPORTED(__inst_arm(0xe09f1392) " @ umulls r1, pc, r2, r3")
@@ -405,7 +405,7 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe0af1392) " @ umlal pc, r1, r2, r3")
TEST_UNSUPPORTED(__inst_arm(0xe0a1f392) " @ umlal r1, pc, r2, r3")
TEST_RRRR( "umlals r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
TEST_RRRR( "umlalles r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
TEST_RRRR( "umlalsle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
TEST_RRR( "umlals r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
TEST_UNSUPPORTED(__inst_arm(0xe0bf1392) " @ umlals pc, r1, r2, r3")
TEST_UNSUPPORTED(__inst_arm(0xe0b1f392) " @ umlals r1, pc, r2, r3")
@@ -416,7 +416,7 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe0c1f392) " @ smull pc, r1, r2, r3")
TEST_UNSUPPORTED(__inst_arm(0xe0cf1392) " @ smull r1, pc, r2, r3")
TEST_RR( "smulls r0, r1, r",2, VAL1,", r",3, VAL2,"")
TEST_RR( "smulllss r7, r8, r",9, VAL2,", r",10, VAL1,"")
TEST_RR( "smullsls r7, r8, r",9, VAL2,", r",10, VAL1,"")
TEST_R( "smulls lr, r12, r",11,VAL3,", r13")
TEST_UNSUPPORTED(__inst_arm(0xe0d1f392) " @ smulls pc, r1, r2, r3")
TEST_UNSUPPORTED(__inst_arm(0xe0df1392) " @ smulls r1, pc, r2, r3")
@@ -427,7 +427,7 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe0ef1392) " @ smlal pc, r1, r2, r3")
TEST_UNSUPPORTED(__inst_arm(0xe0e1f392) " @ smlal r1, pc, r2, r3")
TEST_RRRR( "smlals r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
TEST_RRRR( "smlalles r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
TEST_RRRR( "smlalsle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
TEST_RRR( "smlals r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
TEST_UNSUPPORTED(__inst_arm(0xe0ff1392) " @ smlals pc, r1, r2, r3")
TEST_UNSUPPORTED(__inst_arm(0xe0f0f392) " @ smlals r0, pc, r2, r3")
@@ -450,7 +450,7 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe10f0091) " @ swp r0, r1, [pc]")
#if __LINUX_ARM_ARCH__ < 6
TEST_RP("swpb lr, r",7,VAL2,", [r",8,0,"]")
TEST_R( "swpvsb r0, r",1,VAL1,", [sp]")
TEST_R( "swpbvs r0, r",1,VAL1,", [sp]")
#else
TEST_UNSUPPORTED(__inst_arm(0xe148e097) " @ swpb lr, r7, [r8]")
TEST_UNSUPPORTED(__inst_arm(0x614d0091) " @ swpvsb r0, r1, [sp]")
@@ -477,11 +477,11 @@ void kprobe_arm_test_cases(void)
TEST_GROUP("Extra load/store instructions")
TEST_RPR( "strh r",0, VAL1,", [r",1, 48,", -r",2, 24,"]")
TEST_RPR( "streqh r",14,VAL2,", [r",11,0, ", r",12, 48,"]")
TEST_UNSUPPORTED( "streqh r14, [r13, r12]")
TEST_UNSUPPORTED( "streqh r14, [r12, r13]")
TEST_RPR( "strheq r",14,VAL2,", [r",11,0, ", r",12, 48,"]")
TEST_UNSUPPORTED( "strheq r14, [r13, r12]")
TEST_UNSUPPORTED( "strheq r14, [r12, r13]")
TEST_RPR( "strh r",1, VAL1,", [r",2, 24,", r",3, 48,"]!")
TEST_RPR( "strneh r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
TEST_RPR( "strhne r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
TEST_RPR( "strh r",2, VAL1,", [r",3, 24,"], r",4, 48,"")
TEST_RPR( "strh r",10,VAL2,", [r",9, 48,"], -r",11,24,"")
TEST_UNSUPPORTED(__inst_arm(0xe1afc0ba) " @ strh r12, [pc, r10]!")
@@ -489,9 +489,9 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe089a0bf) " @ strh r10, [r9], pc")
TEST_PR( "ldrh r0, [r",0, 48,", -r",2, 24,"]")
TEST_PR( "ldrcsh r14, [r",13,0, ", r",12, 48,"]")
TEST_PR( "ldrhcs r14, [r",13,0, ", r",12, 48,"]")
TEST_PR( "ldrh r1, [r",2, 24,", r",3, 48,"]!")
TEST_PR( "ldrcch r12, [r",11,48,", -r",10,24,"]!")
TEST_PR( "ldrhcc r12, [r",11,48,", -r",10,24,"]!")
TEST_PR( "ldrh r2, [r",3, 24,"], r",4, 48,"")
TEST_PR( "ldrh r10, [r",9, 48,"], -r",11,24,"")
TEST_UNSUPPORTED(__inst_arm(0xe1bfc0ba) " @ ldrh r12, [pc, r10]!")
@@ -499,9 +499,9 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe099a0bf) " @ ldrh r10, [r9], pc")
TEST_RP( "strh r",0, VAL1,", [r",1, 24,", #-2]")
TEST_RP( "strmih r",14,VAL2,", [r",13,0, ", #2]")
TEST_RP( "strhmi r",14,VAL2,", [r",13,0, ", #2]")
TEST_RP( "strh r",1, VAL1,", [r",2, 24,", #4]!")
TEST_RP( "strplh r",12,VAL2,", [r",11,24,", #-4]!")
TEST_RP( "strhpl r",12,VAL2,", [r",11,24,", #-4]!")
TEST_RP( "strh r",2, VAL1,", [r",3, 24,"], #48")
TEST_RP( "strh r",10,VAL2,", [r",9, 64,"], #-48")
TEST_RP( "strh r",3, VAL1,", [r",13,TEST_MEMORY_SIZE,", #-"__stringify(MAX_STACK_SIZE)"]!")
@@ -511,9 +511,9 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe0c9f3b0) " @ strh pc, [r9], #48")
TEST_P( "ldrh r0, [r",0, 24,", #-2]")
TEST_P( "ldrvsh r14, [r",13,0, ", #2]")
TEST_P( "ldrhvs r14, [r",13,0, ", #2]")
TEST_P( "ldrh r1, [r",2, 24,", #4]!")
TEST_P( "ldrvch r12, [r",11,24,", #-4]!")
TEST_P( "ldrhvc r12, [r",11,24,", #-4]!")
TEST_P( "ldrh r2, [r",3, 24,"], #48")
TEST_P( "ldrh r10, [r",9, 64,"], #-48")
TEST( "ldrh r0, [pc, #0]")
@@ -521,18 +521,18 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe0d9f3b0) " @ ldrh pc, [r9], #48")
TEST_PR( "ldrsb r0, [r",0, 48,", -r",2, 24,"]")
TEST_PR( "ldrhisb r14, [r",13,0,", r",12, 48,"]")
TEST_PR( "ldrsbhi r14, [r",13,0,", r",12, 48,"]")
TEST_PR( "ldrsb r1, [r",2, 24,", r",3, 48,"]!")
TEST_PR( "ldrlssb r12, [r",11,48,", -r",10,24,"]!")
TEST_PR( "ldrsbls r12, [r",11,48,", -r",10,24,"]!")
TEST_PR( "ldrsb r2, [r",3, 24,"], r",4, 48,"")
TEST_PR( "ldrsb r10, [r",9, 48,"], -r",11,24,"")
TEST_UNSUPPORTED(__inst_arm(0xe1bfc0da) " @ ldrsb r12, [pc, r10]!")
TEST_UNSUPPORTED(__inst_arm(0xe099f0db) " @ ldrsb pc, [r9], r11")
TEST_P( "ldrsb r0, [r",0, 24,", #-1]")
TEST_P( "ldrgesb r14, [r",13,0, ", #1]")
TEST_P( "ldrsbge r14, [r",13,0, ", #1]")
TEST_P( "ldrsb r1, [r",2, 24,", #4]!")
TEST_P( "ldrltsb r12, [r",11,24,", #-4]!")
TEST_P( "ldrsblt r12, [r",11,24,", #-4]!")
TEST_P( "ldrsb r2, [r",3, 24,"], #48")
TEST_P( "ldrsb r10, [r",9, 64,"], #-48")
TEST( "ldrsb r0, [pc, #0]")
@@ -540,18 +540,18 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe0d9f3d0) " @ ldrsb pc, [r9], #48")
TEST_PR( "ldrsh r0, [r",0, 48,", -r",2, 24,"]")
TEST_PR( "ldrgtsh r14, [r",13,0, ", r",12, 48,"]")
TEST_PR( "ldrshgt r14, [r",13,0, ", r",12, 48,"]")
TEST_PR( "ldrsh r1, [r",2, 24,", r",3, 48,"]!")
TEST_PR( "ldrlesh r12, [r",11,48,", -r",10,24,"]!")
TEST_PR( "ldrshle r12, [r",11,48,", -r",10,24,"]!")
TEST_PR( "ldrsh r2, [r",3, 24,"], r",4, 48,"")
TEST_PR( "ldrsh r10, [r",9, 48,"], -r",11,24,"")
TEST_UNSUPPORTED(__inst_arm(0xe1bfc0fa) " @ ldrsh r12, [pc, r10]!")
TEST_UNSUPPORTED(__inst_arm(0xe099f0fb) " @ ldrsh pc, [r9], r11")
TEST_P( "ldrsh r0, [r",0, 24,", #-1]")
TEST_P( "ldreqsh r14, [r",13,0 ,", #1]")
TEST_P( "ldrsheq r14, [r",13,0 ,", #1]")
TEST_P( "ldrsh r1, [r",2, 24,", #4]!")
TEST_P( "ldrnesh r12, [r",11,24,", #-4]!")
TEST_P( "ldrshne r12, [r",11,24,", #-4]!")
TEST_P( "ldrsh r2, [r",3, 24,"], #48")
TEST_P( "ldrsh r10, [r",9, 64,"], #-48")
TEST( "ldrsh r0, [pc, #0]")
@@ -571,30 +571,30 @@ void kprobe_arm_test_cases(void)
#if __LINUX_ARM_ARCH__ >= 5
TEST_RPR( "strd r",0, VAL1,", [r",1, 48,", -r",2,24,"]")
TEST_RPR( "strccd r",8, VAL2,", [r",11,0, ", r",12,48,"]")
TEST_UNSUPPORTED( "strccd r8, [r13, r12]")
TEST_UNSUPPORTED( "strccd r8, [r12, r13]")
TEST_RPR( "strdcc r",8, VAL2,", [r",11,0, ", r",12,48,"]")
TEST_UNSUPPORTED( "strdcc r8, [r13, r12]")
TEST_UNSUPPORTED( "strdcc r8, [r12, r13]")
TEST_RPR( "strd r",4, VAL1,", [r",2, 24,", r",3, 48,"]!")
TEST_RPR( "strcsd r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
TEST_RPR( "strd r",2, VAL1,", [r",5, 24,"], r",4,48,"")
TEST_RPR( "strd r",10,VAL2,", [r",9, 48,"], -r",7,24,"")
TEST_RPR( "strdcs r",12,VAL2,", r13, [r",11,48,", -r",10,24,"]!")
TEST_RPR( "strd r",2, VAL1,", r3, [r",5, 24,"], r",4,48,"")
TEST_RPR( "strd r",10,VAL2,", r11, [r",9, 48,"], -r",7,24,"")
TEST_UNSUPPORTED(__inst_arm(0xe1afc0fa) " @ strd r12, [pc, r10]!")
TEST_PR( "ldrd r0, [r",0, 48,", -r",2,24,"]")
TEST_PR( "ldrmid r8, [r",13,0, ", r",12,48,"]")
TEST_PR( "ldrdmi r8, [r",13,0, ", r",12,48,"]")
TEST_PR( "ldrd r4, [r",2, 24,", r",3, 48,"]!")
TEST_PR( "ldrpld r6, [r",11,48,", -r",10,24,"]!")
TEST_PR( "ldrd r2, [r",5, 24,"], r",4,48,"")
TEST_PR( "ldrd r10, [r",9,48,"], -r",7,24,"")
TEST_PR( "ldrdpl r6, [r",11,48,", -r",10,24,"]!")
TEST_PR( "ldrd r2, r3, [r",5, 24,"], r",4,48,"")
TEST_PR( "ldrd r10, r11, [r",9,48,"], -r",7,24,"")
TEST_UNSUPPORTED(__inst_arm(0xe1afc0da) " @ ldrd r12, [pc, r10]!")
TEST_UNSUPPORTED(__inst_arm(0xe089f0db) " @ ldrd pc, [r9], r11")
TEST_UNSUPPORTED(__inst_arm(0xe089e0db) " @ ldrd lr, [r9], r11")
TEST_UNSUPPORTED(__inst_arm(0xe089c0df) " @ ldrd r12, [r9], pc")
TEST_RP( "strd r",0, VAL1,", [r",1, 24,", #-8]")
TEST_RP( "strvsd r",8, VAL2,", [r",13,0, ", #8]")
TEST_RP( "strdvs r",8, VAL2,", [r",13,0, ", #8]")
TEST_RP( "strd r",4, VAL1,", [r",2, 24,", #16]!")
TEST_RP( "strvcd r",12,VAL2,", [r",11,24,", #-16]!")
TEST_RP( "strdvc r",12,VAL2,", r13, [r",11,24,", #-16]!")
TEST_RP( "strd r",2, VAL1,", [r",4, 24,"], #48")
TEST_RP( "strd r",10,VAL2,", [r",9, 64,"], #-48")
TEST_RP( "strd r",6, VAL1,", [r",13,TEST_MEMORY_SIZE,", #-"__stringify(MAX_STACK_SIZE)"]!")
@@ -603,9 +603,9 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(__inst_arm(0xe1efc3f0) " @ strd r12, [pc, #48]!")
TEST_P( "ldrd r0, [r",0, 24,", #-8]")
TEST_P( "ldrhid r8, [r",13,0, ", #8]")
TEST_P( "ldrdhi r8, [r",13,0, ", #8]")
TEST_P( "ldrd r4, [r",2, 24,", #16]!")
TEST_P( "ldrlsd r6, [r",11,24,", #-16]!")
TEST_P( "ldrdls r6, [r",11,24,", #-16]!")
TEST_P( "ldrd r2, [r",5, 24,"], #48")
TEST_P( "ldrd r10, [r",9,6,"], #-48")
TEST_UNSUPPORTED(__inst_arm(0xe1efc3d0) " @ ldrd r12, [pc, #48]!")
@@ -1084,63 +1084,63 @@ void kprobe_arm_test_cases(void)
TEST_GROUP("Branch, branch with link, and block data transfer")
TEST_P( "stmda r",0, 16*4,", {r0}")
TEST_P( "stmeqda r",4, 16*4,", {r0-r15}")
TEST_P( "stmneda r",8, 16*4,"!, {r8-r15}")
TEST_P( "stmdaeq r",4, 16*4,", {r0-r15}")
TEST_P( "stmdane r",8, 16*4,"!, {r8-r15}")
TEST_P( "stmda r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
TEST_P( "stmda r",13,0, "!, {pc}")
TEST_P( "ldmda r",0, 16*4,", {r0}")
TEST_BF_P("ldmcsda r",4, 15*4,", {r0-r15}")
TEST_BF_P("ldmccda r",7, 15*4,"!, {r8-r15}")
TEST_BF_P("ldmdacs r",4, 15*4,", {r0-r15}")
TEST_BF_P("ldmdacc r",7, 15*4,"!, {r8-r15}")
TEST_P( "ldmda r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
TEST_BF_P("ldmda r",14,15*4,"!, {pc}")
TEST_P( "stmia r",0, 16*4,", {r0}")
TEST_P( "stmmiia r",4, 16*4,", {r0-r15}")
TEST_P( "stmplia r",8, 16*4,"!, {r8-r15}")
TEST_P( "stmiami r",4, 16*4,", {r0-r15}")
TEST_P( "stmiapl r",8, 16*4,"!, {r8-r15}")
TEST_P( "stmia r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
TEST_P( "stmia r",14,0, "!, {pc}")
TEST_P( "ldmia r",0, 16*4,", {r0}")
TEST_BF_P("ldmvsia r",4, 0, ", {r0-r15}")
TEST_BF_P("ldmvcia r",7, 8*4, "!, {r8-r15}")
TEST_BF_P("ldmiavs r",4, 0, ", {r0-r15}")
TEST_BF_P("ldmiavc r",7, 8*4, "!, {r8-r15}")
TEST_P( "ldmia r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
TEST_BF_P("ldmia r",14,15*4,"!, {pc}")
TEST_P( "stmdb r",0, 16*4,", {r0}")
TEST_P( "stmhidb r",4, 16*4,", {r0-r15}")
TEST_P( "stmlsdb r",8, 16*4,"!, {r8-r15}")
TEST_P( "stmdbhi r",4, 16*4,", {r0-r15}")
TEST_P( "stmdbls r",8, 16*4,"!, {r8-r15}")
TEST_P( "stmdb r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
TEST_P( "stmdb r",13,4, "!, {pc}")
TEST_P( "ldmdb r",0, 16*4,", {r0}")
TEST_BF_P("ldmgedb r",4, 16*4,", {r0-r15}")
TEST_BF_P("ldmltdb r",7, 16*4,"!, {r8-r15}")
TEST_BF_P("ldmdbge r",4, 16*4,", {r0-r15}")
TEST_BF_P("ldmdblt r",7, 16*4,"!, {r8-r15}")
TEST_P( "ldmdb r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
TEST_BF_P("ldmdb r",14,16*4,"!, {pc}")
TEST_P( "stmib r",0, 16*4,", {r0}")
TEST_P( "stmgtib r",4, 16*4,", {r0-r15}")
TEST_P( "stmleib r",8, 16*4,"!, {r8-r15}")
TEST_P( "stmibgt r",4, 16*4,", {r0-r15}")
TEST_P( "stmible r",8, 16*4,"!, {r8-r15}")
TEST_P( "stmib r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
TEST_P( "stmib r",13,-4, "!, {pc}")
TEST_P( "ldmib r",0, 16*4,", {r0}")
TEST_BF_P("ldmeqib r",4, -4,", {r0-r15}")
TEST_BF_P("ldmneib r",7, 7*4,"!, {r8-r15}")
TEST_BF_P("ldmibeq r",4, -4,", {r0-r15}")
TEST_BF_P("ldmibne r",7, 7*4,"!, {r8-r15}")
TEST_P( "ldmib r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
TEST_BF_P("ldmib r",14,14*4,"!, {pc}")
TEST_P( "stmdb r",13,16*4,"!, {r3-r12,lr}")
TEST_P( "stmeqdb r",13,16*4,"!, {r3-r12}")
TEST_P( "stmnedb r",2, 16*4,", {r3-r12,lr}")
TEST_P( "stmdbeq r",13,16*4,"!, {r3-r12}")
TEST_P( "stmdbne r",2, 16*4,", {r3-r12,lr}")
TEST_P( "stmdb r",13,16*4,"!, {r2-r12,lr}")
TEST_P( "stmdb r",0, 16*4,", {r0-r12}")
TEST_P( "stmdb r",0, 16*4,", {r0-r12,lr}")
TEST_BF_P("ldmia r",13,5*4, "!, {r3-r12,pc}")
TEST_P( "ldmccia r",13,5*4, "!, {r3-r12}")
TEST_BF_P("ldmcsia r",2, 5*4, "!, {r3-r12,pc}")
TEST_P( "ldmiacc r",13,5*4, "!, {r3-r12}")
TEST_BF_P("ldmiacs r",2, 5*4, "!, {r3-r12,pc}")
TEST_BF_P("ldmia r",13,4*4, "!, {r2-r12,pc}")
TEST_P( "ldmia r",0, 16*4,", {r0-r12}")
TEST_P( "ldmia r",0, 16*4,", {r0-r12,lr}")
@@ -1174,80 +1174,80 @@ void kprobe_arm_test_cases(void)
#define TEST_COPROCESSOR(code) TEST_UNSUPPORTED(code)
#define COPROCESSOR_INSTRUCTIONS_ST_LD(two,cc) \
TEST_COPROCESSOR("stc"two" 0, cr0, [r13, #4]") \
TEST_COPROCESSOR("stc"two" 0, cr0, [r13, #-4]") \
TEST_COPROCESSOR("stc"two" 0, cr0, [r13, #4]!") \
TEST_COPROCESSOR("stc"two" 0, cr0, [r13, #-4]!") \
TEST_COPROCESSOR("stc"two" 0, cr0, [r13], #4") \
TEST_COPROCESSOR("stc"two" 0, cr0, [r13], #-4") \
TEST_COPROCESSOR("stc"two" 0, cr0, [r13], {1}") \
TEST_COPROCESSOR("stc"two"l 0, cr0, [r13, #4]") \
TEST_COPROCESSOR("stc"two"l 0, cr0, [r13, #-4]") \
TEST_COPROCESSOR("stc"two"l 0, cr0, [r13, #4]!") \
TEST_COPROCESSOR("stc"two"l 0, cr0, [r13, #-4]!") \
TEST_COPROCESSOR("stc"two"l 0, cr0, [r13], #4") \
TEST_COPROCESSOR("stc"two"l 0, cr0, [r13], #-4") \
TEST_COPROCESSOR("stc"two"l 0, cr0, [r13], {1}") \
TEST_COPROCESSOR("ldc"two" 0, cr0, [r13, #4]") \
TEST_COPROCESSOR("ldc"two" 0, cr0, [r13, #-4]") \
TEST_COPROCESSOR("ldc"two" 0, cr0, [r13, #4]!") \
TEST_COPROCESSOR("ldc"two" 0, cr0, [r13, #-4]!") \
TEST_COPROCESSOR("ldc"two" 0, cr0, [r13], #4") \
TEST_COPROCESSOR("ldc"two" 0, cr0, [r13], #-4") \
TEST_COPROCESSOR("ldc"two" 0, cr0, [r13], {1}") \
TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13, #4]") \
TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13, #-4]") \
TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13, #4]!") \
TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13, #-4]!") \
TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13], #4") \
TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13], #-4") \
TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13], {1}") \
TEST_COPROCESSOR("stc"two" p0, cr0, [r13, #4]") \
TEST_COPROCESSOR("stc"two" p0, cr0, [r13, #-4]") \
TEST_COPROCESSOR("stc"two" p0, cr0, [r13, #4]!") \
TEST_COPROCESSOR("stc"two" p0, cr0, [r13, #-4]!") \
TEST_COPROCESSOR("stc"two" p0, cr0, [r13], #4") \
TEST_COPROCESSOR("stc"two" p0, cr0, [r13], #-4") \
TEST_COPROCESSOR("stc"two" p0, cr0, [r13], {1}") \
TEST_COPROCESSOR("stc"two"l p0, cr0, [r13, #4]") \
TEST_COPROCESSOR("stc"two"l p0, cr0, [r13, #-4]") \
TEST_COPROCESSOR("stc"two"l p0, cr0, [r13, #4]!") \
TEST_COPROCESSOR("stc"two"l p0, cr0, [r13, #-4]!") \
TEST_COPROCESSOR("stc"two"l p0, cr0, [r13], #4") \
TEST_COPROCESSOR("stc"two"l p0, cr0, [r13], #-4") \
TEST_COPROCESSOR("stc"two"l p0, cr0, [r13], {1}") \
TEST_COPROCESSOR("ldc"two" p0, cr0, [r13, #4]") \
TEST_COPROCESSOR("ldc"two" p0, cr0, [r13, #-4]") \
TEST_COPROCESSOR("ldc"two" p0, cr0, [r13, #4]!") \
TEST_COPROCESSOR("ldc"two" p0, cr0, [r13, #-4]!") \
TEST_COPROCESSOR("ldc"two" p0, cr0, [r13], #4") \
TEST_COPROCESSOR("ldc"two" p0, cr0, [r13], #-4") \
TEST_COPROCESSOR("ldc"two" p0, cr0, [r13], {1}") \
TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13, #4]") \
TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13, #-4]") \
TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13, #4]!") \
TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13, #-4]!") \
TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13], #4") \
TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13], #-4") \
TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13], {1}") \
\
TEST_COPROCESSOR( "stc"two" 0, cr0, [r15, #4]") \
TEST_COPROCESSOR( "stc"two" 0, cr0, [r15, #-4]") \
TEST_COPROCESSOR( "stc"two" p0, cr0, [r15, #4]") \
TEST_COPROCESSOR( "stc"two" p0, cr0, [r15, #-4]") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##daf0001) " @ stc"two" 0, cr0, [r15, #4]!") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##d2f0001) " @ stc"two" 0, cr0, [r15, #-4]!") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##caf0001) " @ stc"two" 0, cr0, [r15], #4") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##c2f0001) " @ stc"two" 0, cr0, [r15], #-4") \
TEST_COPROCESSOR( "stc"two" 0, cr0, [r15], {1}") \
TEST_COPROCESSOR( "stc"two"l 0, cr0, [r15, #4]") \
TEST_COPROCESSOR( "stc"two"l 0, cr0, [r15, #-4]") \
TEST_COPROCESSOR( "stc"two" p0, cr0, [r15], {1}") \
TEST_COPROCESSOR( "stc"two"l p0, cr0, [r15, #4]") \
TEST_COPROCESSOR( "stc"two"l p0, cr0, [r15, #-4]") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##def0001) " @ stc"two"l 0, cr0, [r15, #4]!") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##d6f0001) " @ stc"two"l 0, cr0, [r15, #-4]!") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##cef0001) " @ stc"two"l 0, cr0, [r15], #4") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##c6f0001) " @ stc"two"l 0, cr0, [r15], #-4") \
TEST_COPROCESSOR( "stc"two"l 0, cr0, [r15], {1}") \
TEST_COPROCESSOR( "ldc"two" 0, cr0, [r15, #4]") \
TEST_COPROCESSOR( "ldc"two" 0, cr0, [r15, #-4]") \
TEST_COPROCESSOR( "stc"two"l p0, cr0, [r15], {1}") \
TEST_COPROCESSOR( "ldc"two" p0, cr0, [r15, #4]") \
TEST_COPROCESSOR( "ldc"two" p0, cr0, [r15, #-4]") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##dbf0001) " @ ldc"two" 0, cr0, [r15, #4]!") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##d3f0001) " @ ldc"two" 0, cr0, [r15, #-4]!") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##cbf0001) " @ ldc"two" 0, cr0, [r15], #4") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##c3f0001) " @ ldc"two" 0, cr0, [r15], #-4") \
TEST_COPROCESSOR( "ldc"two" 0, cr0, [r15], {1}") \
TEST_COPROCESSOR( "ldc"two"l 0, cr0, [r15, #4]") \
TEST_COPROCESSOR( "ldc"two"l 0, cr0, [r15, #-4]") \
TEST_COPROCESSOR( "ldc"two" p0, cr0, [r15], {1}") \
TEST_COPROCESSOR( "ldc"two"l p0, cr0, [r15, #4]") \
TEST_COPROCESSOR( "ldc"two"l p0, cr0, [r15, #-4]") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##dff0001) " @ ldc"two"l 0, cr0, [r15, #4]!") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##d7f0001) " @ ldc"two"l 0, cr0, [r15, #-4]!") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##cff0001) " @ ldc"two"l 0, cr0, [r15], #4") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##c7f0001) " @ ldc"two"l 0, cr0, [r15], #-4") \
TEST_COPROCESSOR( "ldc"two"l 0, cr0, [r15], {1}")
TEST_COPROCESSOR( "ldc"two"l p0, cr0, [r15], {1}")
#define COPROCESSOR_INSTRUCTIONS_MC_MR(two,cc) \
\
TEST_COPROCESSOR( "mcrr"two" 0, 15, r0, r14, cr0") \
TEST_COPROCESSOR( "mcrr"two" 15, 0, r14, r0, cr15") \
TEST_COPROCESSOR( "mcrr"two" p0, 15, r0, r14, cr0") \
TEST_COPROCESSOR( "mcrr"two" p15, 0, r14, r0, cr15") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##c4f00f0) " @ mcrr"two" 0, 15, r0, r15, cr0") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##c40ff0f) " @ mcrr"two" 15, 0, r15, r0, cr15") \
TEST_COPROCESSOR( "mrrc"two" 0, 15, r0, r14, cr0") \
TEST_COPROCESSOR( "mrrc"two" 15, 0, r14, r0, cr15") \
TEST_COPROCESSOR( "mrrc"two" p0, 15, r0, r14, cr0") \
TEST_COPROCESSOR( "mrrc"two" p15, 0, r14, r0, cr15") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##c5f00f0) " @ mrrc"two" 0, 15, r0, r15, cr0") \
TEST_UNSUPPORTED(__inst_arm(0x##cc##c50ff0f) " @ mrrc"two" 15, 0, r15, r0, cr15") \
TEST_COPROCESSOR( "cdp"two" 15, 15, cr15, cr15, cr15, 7") \
TEST_COPROCESSOR( "cdp"two" 0, 0, cr0, cr0, cr0, 0") \
TEST_COPROCESSOR( "mcr"two" 15, 7, r15, cr15, cr15, 7") \
TEST_COPROCESSOR( "mcr"two" 0, 0, r0, cr0, cr0, 0") \
TEST_COPROCESSOR( "mrc"two" 15, 7, r15, cr15, cr15, 7") \
TEST_COPROCESSOR( "mrc"two" 0, 0, r0, cr0, cr0, 0")
TEST_COPROCESSOR( "cdp"two" p15, 15, cr15, cr15, cr15, 7") \
TEST_COPROCESSOR( "cdp"two" p0, 0, cr0, cr0, cr0, 0") \
TEST_COPROCESSOR( "mcr"two" p15, 7, r15, cr15, cr15, 7") \
TEST_COPROCESSOR( "mcr"two" p0, 0, r0, cr0, cr0, 0") \
TEST_COPROCESSOR( "mrc"two" p15, 7, r14, cr15, cr15, 7") \
TEST_COPROCESSOR( "mrc"two" p0, 0, r0, cr0, cr0, 0")
COPROCESSOR_INSTRUCTIONS_ST_LD("",e)
#if __LINUX_ARM_ARCH__ >= 5

1
arch/arm/probes/kprobes/test-core.h
View File

@@ -108,6 +108,7 @@ struct test_arg_end {
#define TESTCASE_START(title) \
__asm__ __volatile__ ( \
".syntax unified \n\t" \
"bl __kprobes_test_case_start \n\t" \
".pushsection .rodata \n\t" \
"10: \n\t" \

1
arch/arm64/Kconfig
View File

@@ -209,6 +209,7 @@ config ARM64
select SYSCTL_EXCEPTION_TRACE
select THREAD_INFO_IN_TASK
select ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT
select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
help
ARM 64-bit (AArch64) Linux support.

2
arch/arm64/OWNERS Normal file
View File

@@ -0,0 +1,2 @@
# include OWNERS from the authoritative android-mainline branch
include kernel/common:android-mainline:/arch/arm64/OWNERS

1
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@@ -192,6 +192,7 @@
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",

1
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@@ -322,6 +322,7 @@
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <0 75 0x4>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",

1
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@@ -325,6 +325,7 @@
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",

2
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
View File

@@ -124,7 +124,7 @@
#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0

2
arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
View File

@@ -130,7 +130,7 @@
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0

25
arch/arm64/configs/gki_defconfig
View File

@@ -86,6 +86,8 @@ CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
CONFIG_SHADOW_CALL_STACK=y
CONFIG_LTO_CLANG_FULL=y
CONFIG_CFI_CLANG=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
@@ -104,6 +106,7 @@ CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_CLEANCACHE=y
CONFIG_CMA=y
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_SYSFS=y
CONFIG_CMA_AREAS=16
CONFIG_READ_ONLY_THP_FOR_FS=y
CONFIG_NET=y
@@ -220,13 +223,20 @@ CONFIG_MAC802154=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
CONFIG_NET_SCH_TBF=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_BASIC=y
CONFIG_NET_CLS_TCINDEX=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_NET_CLS_BPF=y
CONFIG_NET_CLS_MATCHALL=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_ACT_GACT=y
CONFIG_NET_ACT_MIRRED=y
CONFIG_VSOCKETS=y
CONFIG_BPF_JIT=y
CONFIG_BT=y
@@ -279,12 +289,12 @@ CONFIG_DM_DEFAULT_KEY=y
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_AVB=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_WIREGUARD=y
CONFIG_IFB=y
CONFIG_TUN=y
CONFIG_VETH=y
CONFIG_PHYLIB=y
@@ -298,11 +308,10 @@ CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
# CONFIG_USB_NET_CDCETHER is not set
# CONFIG_USB_NET_CDC_NCM is not set
# CONFIG_USB_NET_NET1080 is not set
# CONFIG_USB_NET_CDC_SUBSET is not set
# CONFIG_USB_NET_ZAURUS is not set
CONFIG_USB_NET_AQC111=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
@@ -475,6 +484,8 @@ CONFIG_RTC_DRV_PL030=y
CONFIG_RTC_DRV_PL031=y
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_SYSFS_STATS=y
CONFIG_DMABUF_HEAPS_DEFERRED_FREE=y
CONFIG_DMABUF_HEAPS_PAGE_POOL=y
CONFIG_UIO=y
CONFIG_VHOST_VSOCK=y
CONFIG_STAGING=y
@@ -503,7 +514,6 @@ CONFIG_PWM=y
CONFIG_GENERIC_PHY=y
CONFIG_POWERCAP=y
CONFIG_DTPM=y
CONFIG_DTPM_CPU=y
CONFIG_RAS=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
@@ -620,6 +630,10 @@ CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_HEADERS_INSTALL=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_UBSAN=y
CONFIG_UBSAN_TRAP=y
CONFIG_UBSAN_LOCAL_BOUNDS=y
# CONFIG_UBSAN_MISC is not set
CONFIG_PAGE_OWNER=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_MEMORY_INIT=y
@@ -627,13 +641,16 @@ CONFIG_KASAN=y
CONFIG_KASAN_HW_TAGS=y
CONFIG_KFENCE=y
CONFIG_KFENCE_SAMPLE_INTERVAL=500
CONFIG_KFENCE_NUM_OBJECTS=63
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_TIMEOUT=-1
CONFIG_DETECT_HUNG_TASK=y
CONFIG_WQ_WATCHDOG=y
CONFIG_SCHEDSTATS=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_TRACE_MMIO_ACCESS=y
CONFIG_TRACEFS_DISABLE_AUTOMOUNT=y
CONFIG_KUNIT=y
CONFIG_KUNIT_DEBUGFS=y
# CONFIG_RUNTIME_TESTING_MENU is not set

1
arch/arm64/configs/rockpi4_defconfig
View File

@@ -218,7 +218,6 @@ CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_AVB=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y

13
arch/arm64/include/asm/assembler.h
View File

@@ -15,6 +15,7 @@
#include <asm-generic/export.h>
#include <asm/asm-offsets.h>
#include <asm/asm-bug.h>
#include <asm/cpufeature.h>
#include <asm/cputype.h>
#include <asm/debug-monitors.h>
@@ -270,12 +271,24 @@ alternative_endif
* provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
*/
.macro read_ctr, reg
#ifndef __KVM_NVHE_HYPERVISOR__
alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
mrs \reg, ctr_el0 // read CTR
nop
alternative_else
ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
alternative_endif
#else
alternative_if_not ARM64_KVM_PROTECTED_MODE
ASM_BUG()
alternative_else_nop_endif
alternative_cb kvm_compute_final_ctr_el0
movz \reg, #0
movk \reg, #0, lsl #16
movk \reg, #0, lsl #32
movk \reg, #0, lsl #48
alternative_cb_end
#endif
.endm

1
arch/arm64/include/asm/cpufeature.h
View File

@@ -607,7 +607,6 @@ void check_local_cpu_capabilities(void);
u64 read_sanitised_ftr_reg(u32 id);
u64 __read_sysreg_by_encoding(u32 sys_id);
int copy_ftr_reg(u32 id, struct arm64_ftr_reg *dst);
static inline bool cpu_supports_mixed_endian_el0(void)
{

19
arch/arm64/include/asm/kvm_cpufeature.h
View File

@@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2020 - Google LLC
* Author: Quentin Perret <qperret@google.com>
*/
#include <asm/cpufeature.h>
#ifndef KVM_HYP_CPU_FTR_REG
#if defined(__KVM_NVHE_HYPERVISOR__)
#define KVM_HYP_CPU_FTR_REG(name) extern struct arm64_ftr_reg name
#else
#define KVM_HYP_CPU_FTR_REG(name) extern struct arm64_ftr_reg kvm_nvhe_sym(name)
#endif
#endif
KVM_HYP_CPU_FTR_REG(arm64_ftr_reg_ctrel0);
KVM_HYP_CPU_FTR_REG(arm64_ftr_reg_id_aa64mmfr0_el1);
KVM_HYP_CPU_FTR_REG(arm64_ftr_reg_id_aa64mmfr1_el1);

4
arch/arm64/include/asm/kvm_host.h
View File

@@ -743,13 +743,9 @@ void kvm_clr_pmu_events(u32 clr);
void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
void setup_kvm_el2_caps(void);
#else
static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
static inline void kvm_clr_pmu_events(u32 clr) {}
static inline void setup_kvm_el2_caps(void) {}
#endif
void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);

3
arch/arm64/include/asm/kvm_hyp.h
View File

@@ -116,4 +116,7 @@ int __pkvm_init(phys_addr_t phys, unsigned long size, unsigned long nr_cpus,
void __noreturn __host_enter(struct kvm_cpu_context *host_ctxt);
#endif
extern u64 kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val);
extern u64 kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val);
#endif /* __ARM64_KVM_HYP_H__ */

31
arch/arm64/include/asm/kvm_pgtable.h
View File

@@ -60,9 +60,11 @@ struct kvm_pgtable_mm_ops {
* enum kvm_pgtable_stage2_flags - Stage-2 page-table flags.
* @KVM_PGTABLE_S2_NOFWB: Don't enforce Normal-WB even if the CPUs have
* ARM64_HAS_STAGE2_FWB.
* @KVM_PGTABLE_S2_IDMAP: Only use identity mappings.
*/
enum kvm_pgtable_stage2_flags {
KVM_PGTABLE_S2_NOFWB = BIT(0),
KVM_PGTABLE_S2_IDMAP = BIT(1),
};
/**
@@ -206,7 +208,7 @@ int kvm_pgtable_hyp_map(struct kvm_pgtable *pgt, u64 addr, u64 size, u64 phys,
u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift);
/**
* kvm_pgtable_stage2_init() - Initialise a guest stage-2 page-table.
* kvm_pgtable_stage2_init_flags() - Initialise a guest stage-2 page-table.
* @pgt: Uninitialised page-table structure to initialise.
* @arch: Arch-specific KVM structure representing the guest virtual
* machine.
@@ -224,7 +226,7 @@ int kvm_pgtable_stage2_init_flags(struct kvm_pgtable *pgt, struct kvm_arch *arch
/**
* kvm_pgtable_stage2_destroy() - Destroy an unused guest stage-2 page-table.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
*
* The page-table is assumed to be unreachable by any hardware walkers prior
* to freeing and therefore no TLB invalidation is performed.
@@ -233,7 +235,7 @@ void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt);
/**
* kvm_pgtable_stage2_map() - Install a mapping in a guest stage-2 page-table.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Intermediate physical address at which to place the mapping.
* @size: Size of the mapping.
* @phys: Physical address of the memory to map.
@@ -264,10 +266,9 @@ int kvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size,
void *mc);
/**
* kvm_pgtable_stage2_set_owner() - Annotate invalid mappings with metadata
* encoding the ownership of a page in the
* IPA space.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* kvm_pgtable_stage2_set_owner() - Unmap and annotate pages in the IPA space to
* track ownership.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Base intermediate physical address to annotate.
* @size: Size of the annotated range.
* @mc: Cache of pre-allocated and zeroed memory from which to allocate
@@ -286,7 +287,7 @@ int kvm_pgtable_stage2_set_owner(struct kvm_pgtable *pgt, u64 addr, u64 size,
/**
* kvm_pgtable_stage2_unmap() - Remove a mapping from a guest stage-2 page-table.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Intermediate physical address from which to remove the mapping.
* @size: Size of the mapping.
*
@@ -306,7 +307,7 @@ int kvm_pgtable_stage2_unmap(struct kvm_pgtable *pgt, u64 addr, u64 size);
/**
* kvm_pgtable_stage2_wrprotect() - Write-protect guest stage-2 address range
* without TLB invalidation.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Intermediate physical address from which to write-protect,
* @size: Size of the range.
*
@@ -323,7 +324,7 @@ int kvm_pgtable_stage2_wrprotect(struct kvm_pgtable *pgt, u64 addr, u64 size);
/**
* kvm_pgtable_stage2_mkyoung() - Set the access flag in a page-table entry.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Intermediate physical address to identify the page-table entry.
*
* The offset of @addr within a page is ignored.
@@ -337,7 +338,7 @@ kvm_pte_t kvm_pgtable_stage2_mkyoung(struct kvm_pgtable *pgt, u64 addr);
/**
* kvm_pgtable_stage2_mkold() - Clear the access flag in a page-table entry.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Intermediate physical address to identify the page-table entry.
*
* The offset of @addr within a page is ignored.
@@ -356,7 +357,7 @@ kvm_pte_t kvm_pgtable_stage2_mkold(struct kvm_pgtable *pgt, u64 addr);
/**
* kvm_pgtable_stage2_relax_perms() - Relax the permissions enforced by a
* page-table entry.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Intermediate physical address to identify the page-table entry.
* @prot: Additional permissions to grant for the mapping.
*
@@ -375,7 +376,7 @@ int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr,
/**
* kvm_pgtable_stage2_is_young() - Test whether a page-table entry has the
* access flag set.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Intermediate physical address to identify the page-table entry.
*
* The offset of @addr within a page is ignored.
@@ -388,7 +389,7 @@ bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr);
* kvm_pgtable_stage2_flush_range() - Clean and invalidate data cache to Point
* of Coherency for guest stage-2 address
* range.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Intermediate physical address from which to flush.
* @size: Size of the range.
*
@@ -427,7 +428,7 @@ int kvm_pgtable_walk(struct kvm_pgtable *pgt, u64 addr, u64 size,
* kvm_pgtable_stage2_find_range() - Find a range of Intermediate Physical
* Addresses with compatible permission
* attributes.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init().
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Address that must be covered by the range.
* @prot: Protection attributes that the range must be compatible with.
* @range: Range structure used to limit the search space at call time and

4
arch/arm64/include/asm/memory.h
View File

@@ -237,8 +237,8 @@ static inline const void *__tag_set(const void *addr, u8 tag)
#define arch_init_tags(max_tag) mte_init_tags(max_tag)
#define arch_get_random_tag() mte_get_random_tag()
#define arch_get_mem_tag(addr) mte_get_mem_tag(addr)
#define arch_set_mem_tag_range(addr, size, tag) \
mte_set_mem_tag_range((addr), (size), (tag))
#define arch_set_mem_tag_range(addr, size, tag, init) \
mte_set_mem_tag_range((addr), (size), (tag), (init))
#endif /* CONFIG_KASAN_HW_TAGS */
/*

19
arch/arm64/include/asm/mte-kasan.h
View File

@@ -53,7 +53,8 @@ static inline u8 mte_get_random_tag(void)
* Note: The address must be non-NULL and MTE_GRANULE_SIZE aligned and
* size must be non-zero and MTE_GRANULE_SIZE aligned.
*/
static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag)
static inline void mte_set_mem_tag_range(void *addr, size_t size,
u8 tag, bool init)
{
u64 curr, end;
@@ -63,19 +64,28 @@ static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag)
curr = (u64)__tag_set(addr, tag);
end = curr + size;
do {
/*
* 'asm volatile' is required to prevent the compiler to move
* the statement outside of the loop.
*/
if (init) {
do {
asm volatile(__MTE_PREAMBLE "stzg %0, [%0]"
:
: "r" (curr)
: "memory");
curr += MTE_GRANULE_SIZE;
} while (curr != end);
} else {
do {
asm volatile(__MTE_PREAMBLE "stg %0, [%0]"
:
: "r" (curr)
: "memory");
curr += MTE_GRANULE_SIZE;
} while (curr != end);
}
}
void mte_enable_kernel(void);
void mte_init_tags(u64 max_tag);
@@ -100,7 +110,8 @@ static inline u8 mte_get_random_tag(void)
return 0xFF;
}
static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag)
static inline void mte_set_mem_tag_range(void *addr, size_t size,
u8 tag, bool init)
{
}

10
arch/arm64/include/asm/word-at-a-time.h
View File

@@ -53,7 +53,7 @@ static inline unsigned long find_zero(unsigned long mask)
*/
static inline unsigned long load_unaligned_zeropad(const void *addr)
{
unsigned long ret, offset;
unsigned long ret, tmp;
/* Load word from unaligned pointer addr */
asm(
@@ -61,9 +61,9 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)
"2:\n"
" .pushsection .fixup,\"ax\"\n"
" .align 2\n"
"3: and %1, %2, #0x7\n"
" bic %2, %2, #0x7\n"
" ldr %0, [%2]\n"
"3: bic %1, %2, #0x7\n"
" ldr %0, [%1]\n"
" and %1, %2, #0x7\n"
" lsl %1, %1, #0x3\n"
#ifndef __AARCH64EB__
" lsr %0, %0, %1\n"
@@ -73,7 +73,7 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)
" b 2b\n"
" .popsection\n"
_ASM_EXTABLE(1b, 3b)
: "=&r" (ret), "=&r" (offset)
: "=&r" (ret), "=&r" (tmp)
: "r" (addr), "Q" (*(unsigned long *)addr));
return ret;

14
arch/arm64/kernel/cpufeature.c
View File

@@ -1199,18 +1199,6 @@ u64 read_sanitised_ftr_reg(u32 id)
}
EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
int copy_ftr_reg(u32 id, struct arm64_ftr_reg *dst)
{
struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
if (!regp)
return -EINVAL;
*dst = *regp;
return 0;
}
#define read_sysreg_case(r) \
case r: val = read_sysreg_s(r); break;
@@ -1354,6 +1342,7 @@ const struct cpumask *system_32bit_el0_cpumask(void)
return cpu_possible_mask;
}
EXPORT_SYMBOL_GPL(system_32bit_el0_cpumask);
static int __init parse_32bit_el0_param(char *str)
{
@@ -2942,7 +2931,6 @@ void __init setup_cpu_features(void)
setup_system_capabilities();
setup_elf_hwcaps(arm64_elf_hwcaps);
setup_kvm_el2_caps();
if (system_supports_32bit_el0())
setup_elf_hwcaps(compat_elf_hwcaps);

2
arch/arm64/kernel/crash_dump.c
View File

@@ -64,5 +64,7 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
ssize_t elfcorehdr_read(char *buf, size_t count, u64 *ppos)
{
memcpy(buf, phys_to_virt((phys_addr_t)*ppos), count);
*ppos += count;
return count;
}

1
arch/arm64/kernel/image-vars.h
View File

@@ -65,6 +65,7 @@ __efistub__ctype = _ctype;
KVM_NVHE_ALIAS(kvm_patch_vector_branch);
KVM_NVHE_ALIAS(kvm_update_va_mask);
KVM_NVHE_ALIAS(kvm_get_kimage_voffset);
KVM_NVHE_ALIAS(kvm_compute_final_ctr_el0);
/* Global kernel state accessed by nVHE hyp code. */
KVM_NVHE_ALIAS(kvm_vgic_global_state);

2
arch/arm64/kernel/sleep.S
View File

@@ -134,7 +134,7 @@ SYM_FUNC_START(_cpu_resume)
*/
bl cpu_do_resume
#if defined(CONFIG_KASAN) && CONFIG_KASAN_STACK
#if defined(CONFIG_KASAN) && defined(CONFIG_KASAN_STACK)
mov x0, sp
bl kasan_unpoison_task_stack_below
#endif

9
arch/arm64/kernel/stacktrace.c
View File

@@ -200,8 +200,9 @@ void show_stack(struct task_struct *tsk, unsigned long *sp, const char *loglvl)
#ifdef CONFIG_STACKTRACE
void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie,
struct task_struct *task, struct pt_regs *regs)
noinline void arch_stack_walk(stack_trace_consume_fn consume_entry,
void *cookie, struct task_struct *task,
struct pt_regs *regs)
{
struct stackframe frame;
@@ -209,8 +210,8 @@ void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie,
start_backtrace(&frame, regs->regs[29], regs->pc);
else if (task == current)
start_backtrace(&frame,
(unsigned long)__builtin_frame_address(0),
(unsigned long)arch_stack_walk);
(unsigned long)__builtin_frame_address(1),
(unsigned long)__builtin_return_address(0));
else
start_backtrace(&frame, thread_saved_fp(task),
thread_saved_pc(task));

3
arch/arm64/kvm/arm.c
View File

@@ -1739,6 +1739,9 @@ static int kvm_hyp_init_protection(u32 hyp_va_bits)
void *addr = phys_to_virt(hyp_mem_base);
int ret;
kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
ret = create_hyp_mappings(addr, addr + hyp_mem_size, PAGE_HYP);
if (ret)
return ret;

10
arch/arm64/kvm/hyp/include/hyp/switch.h
View File

@@ -162,7 +162,9 @@ static inline bool __translate_far_to_hpfar(u64 far, u64 *hpfar)
static inline bool __get_fault_info(u64 esr, struct kvm_vcpu_fault_info *fault)
{
fault->far_el2 = read_sysreg_el2(SYS_FAR);
u64 hpfar, far;
far = read_sysreg_el2(SYS_FAR);
/*
* The HPFAR can be invalid if the stage 2 fault did not
@@ -178,12 +180,14 @@ static inline bool __get_fault_info(u64 esr, struct kvm_vcpu_fault_info *fault)
if (!(esr & ESR_ELx_S1PTW) &&
(cpus_have_final_cap(ARM64_WORKAROUND_834220) ||
(esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
if (!__translate_far_to_hpfar(fault->far_el2, &fault->hpfar_el2))
if (!__translate_far_to_hpfar(far, &hpfar))
return false;
} else {
fault->hpfar_el2 = read_sysreg(hpfar_el2);
hpfar = read_sysreg(hpfar_el2);
}
fault->far_el2 = far;
fault->hpfar_el2 = hpfar;
return true;
}

1
arch/arm64/kvm/hyp/nvhe/hyp-main.c
View File

@@ -247,7 +247,6 @@ void handle_trap(struct kvm_cpu_context *host_ctxt)
sve_cond_update_zcr_vq(ZCR_ELx_LEN_MASK, SYS_ZCR_EL2);
break;
case ESR_ELx_EC_IABT_LOW:
fallthrough;
case ESR_ELx_EC_DABT_LOW:
handle_host_mem_abort(host_ctxt);
break;

7
arch/arm64/kvm/hyp/nvhe/hyp-smp.c
View File

@@ -38,10 +38,3 @@ unsigned long __hyp_per_cpu_offset(unsigned int cpu)
elf_base = (unsigned long)&__per_cpu_start;
return this_cpu_base - elf_base;
}
/*
* Define the CPU feature registers variables that will hold the copies of
* the host's sanitized values.
*/
#define KVM_HYP_CPU_FTR_REG(name) struct arm64_ftr_reg name
#include <asm/kvm_cpufeature.h>

20
arch/arm64/kvm/hyp/nvhe/mem_protect.c
View File

@@ -5,7 +5,6 @@
*/
#include <linux/kvm_host.h>
#include <asm/kvm_cpufeature.h>
#include <asm/kvm_emulate.h>
#include <asm/kvm_hyp.h>
#include <asm/kvm_mmu.h>
@@ -19,12 +18,20 @@
#include <nvhe/mem_protect.h>
#include <nvhe/mm.h>
#define KVM_HOST_S2_FLAGS (KVM_PGTABLE_S2_NOFWB | KVM_PGTABLE_S2_IDMAP)
extern unsigned long hyp_nr_cpus;
struct host_kvm host_kvm;
struct hyp_pool host_s2_mem;
struct hyp_pool host_s2_dev;
/*
* Copies of the host's CPU features registers holding sanitized values.
*/
u64 id_aa64mmfr0_el1_sys_val;
u64 id_aa64mmfr1_el1_sys_val;
static const u8 pkvm_hyp_id = 1;
static void *host_s2_zalloc_pages_exact(size_t size)
@@ -70,16 +77,13 @@ static int prepare_s2_pools(void *mem_pgt_pool, void *dev_pgt_pool)
static void prepare_host_vtcr(void)
{
u32 parange, phys_shift;
u64 mmfr0, mmfr1;
mmfr0 = arm64_ftr_reg_id_aa64mmfr0_el1.sys_val;
mmfr1 = arm64_ftr_reg_id_aa64mmfr1_el1.sys_val;
/* The host stage 2 is id-mapped, so use parange for T0SZ */
parange = kvm_get_parange(mmfr0);
parange = kvm_get_parange(id_aa64mmfr0_el1_sys_val);
phys_shift = id_aa64mmfr0_parange_to_phys_shift(parange);
host_kvm.arch.vtcr = kvm_get_vtcr(mmfr0, mmfr1, phys_shift);
host_kvm.arch.vtcr = kvm_get_vtcr(id_aa64mmfr0_el1_sys_val,
id_aa64mmfr1_el1_sys_val, phys_shift);
}
int kvm_host_prepare_stage2(void *mem_pgt_pool, void *dev_pgt_pool)
@@ -95,7 +99,7 @@ int kvm_host_prepare_stage2(void *mem_pgt_pool, void *dev_pgt_pool)
return ret;
ret = kvm_pgtable_stage2_init_flags(&host_kvm.pgt, &host_kvm.arch,
&host_kvm.mm_ops, KVM_PGTABLE_S2_NOFWB);
&host_kvm.mm_ops, KVM_HOST_S2_FLAGS);
if (ret)
return ret;

41
arch/arm64/kvm/hyp/pgtable.c
View File

@@ -516,17 +516,15 @@ static bool stage2_has_fwb(struct kvm_pgtable *pgt)
return !(pgt->flags & KVM_PGTABLE_S2_NOFWB);
}
static int stage2_set_prot_attr(enum kvm_pgtable_prot prot, kvm_pte_t *ptep,
struct kvm_pgtable *pgt)
#define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt))
static int stage2_set_prot_attr(struct kvm_pgtable *pgt, enum kvm_pgtable_prot prot,
kvm_pte_t *ptep)
{
bool device = prot & KVM_PGTABLE_PROT_DEVICE;
kvm_pte_t attr = device ? KVM_S2_MEMATTR(pgt, DEVICE_nGnRE) :
KVM_S2_MEMATTR(pgt, NORMAL);
u32 sh = KVM_PTE_LEAF_ATTR_LO_S2_SH_IS;
kvm_pte_t attr;
if (device)
attr = PAGE_S2_MEMATTR(DEVICE_nGnRE, stage2_has_fwb(pgt));
else
attr = PAGE_S2_MEMATTR(NORMAL, stage2_has_fwb(pgt));
if (!(prot & KVM_PGTABLE_PROT_X))
attr |= KVM_PTE_LEAF_ATTR_HI_S2_XN;
@@ -762,7 +760,10 @@ int kvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size,
.arg = &map_data,
};
ret = stage2_set_prot_attr(prot, &map_data.attr, pgt);
if (WARN_ON((pgt->flags & KVM_PGTABLE_S2_IDMAP) && (addr != phys)))
return -EINVAL;
ret = stage2_set_prot_attr(pgt, prot, &map_data.attr);
if (ret)
return ret;
@@ -794,19 +795,13 @@ int kvm_pgtable_stage2_set_owner(struct kvm_pgtable *pgt, u64 addr, u64 size,
return -EINVAL;
ret = kvm_pgtable_walk(pgt, addr, size, &walker);
dsb(ishst);
return ret;
}
static void stage2_flush_dcache(void *addr, u64 size)
{
__flush_dcache_area(addr, size);
}
static bool stage2_pte_cacheable(kvm_pte_t pte, struct kvm_pgtable *pgt)
static bool stage2_pte_cacheable(struct kvm_pgtable *pgt, kvm_pte_t pte)
{
u64 memattr = pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR;
return memattr == PAGE_S2_MEMATTR(NORMAL, stage2_has_fwb(pgt));
return memattr == KVM_S2_MEMATTR(pgt, NORMAL);
}
static int stage2_unmap_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep,
@@ -832,7 +827,7 @@ static int stage2_unmap_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep,
if (mm_ops->page_count(childp) != 1)
return 0;
} else if (stage2_pte_cacheable(pte, pgt)) {
} else if (stage2_pte_cacheable(pgt, pte)) {
need_flush = !stage2_has_fwb(pgt);
}
@@ -844,7 +839,7 @@ static int stage2_unmap_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep,
stage2_put_pte(ptep, mmu, addr, level, mm_ops);
if (need_flush) {
stage2_flush_dcache(kvm_pte_follow(pte, mm_ops),
__flush_dcache_area(kvm_pte_follow(pte, mm_ops),
kvm_granule_size(level));
}
@@ -994,10 +989,10 @@ static int stage2_flush_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep,
struct kvm_pgtable_mm_ops *mm_ops = pgt->mm_ops;
kvm_pte_t pte = *ptep;
if (!kvm_pte_valid(pte) || !stage2_pte_cacheable(pte, pgt))
if (!kvm_pte_valid(pte) || !stage2_pte_cacheable(pgt, pte))
return 0;
stage2_flush_dcache(kvm_pte_follow(pte, mm_ops), kvm_granule_size(level));
__flush_dcache_area(kvm_pte_follow(pte, mm_ops), kvm_granule_size(level));
return 0;
}
@@ -1030,11 +1025,11 @@ int kvm_pgtable_stage2_init_flags(struct kvm_pgtable *pgt, struct kvm_arch *arch
if (!pgt->pgd)
return -ENOMEM;
pgt->flags = flags;
pgt->ia_bits = ia_bits;
pgt->start_level = start_level;
pgt->mm_ops = mm_ops;
pgt->mmu = &arch->mmu;
pgt->flags = flags;
/* Ensure zeroed PGD pages are visible to the hardware walker */
dsb(ishst);
@@ -1115,7 +1110,7 @@ int kvm_pgtable_stage2_find_range(struct kvm_pgtable *pgt, u64 addr,
u32 level;
int ret;
ret = stage2_set_prot_attr(prot, &attr, pgt);
ret = stage2_set_prot_attr(pgt, prot, &attr);
if (ret)
return ret;
attr &= KVM_PTE_LEAF_S2_COMPAT_MASK;

9
arch/arm64/kvm/hyp/vgic-v3-sr.c
View File

@@ -429,6 +429,13 @@ u64 __vgic_v3_get_gic_config(void)
if (has_vhe())
flags = local_daif_save();
/*
* Table 11-2 "Permitted ICC_SRE_ELx.SRE settings" indicates
* that to be able to set ICC_SRE_EL1.SRE to 0, all the
* interrupt overrides must be set. You've got to love this.
*/
sysreg_clear_set(hcr_el2, 0, HCR_AMO | HCR_FMO | HCR_IMO);
isb();
write_gicreg(0, ICC_SRE_EL1);
isb();
@@ -436,6 +443,8 @@ u64 __vgic_v3_get_gic_config(void)
write_gicreg(sre, ICC_SRE_EL1);
isb();
sysreg_clear_set(hcr_el2, HCR_AMO | HCR_FMO | HCR_IMO, 0);
isb();
if (has_vhe())
local_daif_restore(flags);

22
arch/arm64/kvm/sys_regs.c
View File

@@ -21,7 +21,6 @@
#include <asm/debug-monitors.h>
#include <asm/esr.h>
#include <asm/kvm_arm.h>
#include <asm/kvm_cpufeature.h>
#include <asm/kvm_emulate.h>
#include <asm/kvm_hyp.h>
#include <asm/kvm_mmu.h>
@@ -2776,24 +2775,3 @@ void kvm_sys_reg_table_init(void)
/* Clear all higher bits. */
cache_levels &= (1 << (i*3))-1;
}
#define CPU_FTR_REG_HYP_COPY(id, name) \
{ .sys_id = id, .dst = (struct arm64_ftr_reg *)&kvm_nvhe_sym(name) }
struct __ftr_reg_copy_entry {
u32 sys_id;
struct arm64_ftr_reg *dst;
} hyp_ftr_regs[] __initdata = {
CPU_FTR_REG_HYP_COPY(SYS_CTR_EL0, arm64_ftr_reg_ctrel0),
CPU_FTR_REG_HYP_COPY(SYS_ID_AA64MMFR0_EL1, arm64_ftr_reg_id_aa64mmfr0_el1),
CPU_FTR_REG_HYP_COPY(SYS_ID_AA64MMFR1_EL1, arm64_ftr_reg_id_aa64mmfr1_el1),
};
void __init setup_kvm_el2_caps(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(hyp_ftr_regs); i++) {
WARN(copy_ftr_reg(hyp_ftr_regs[i].sys_id, hyp_ftr_regs[i].dst),
"%u feature register not found\n", hyp_ftr_regs[i].sys_id);
}
}

7
arch/arm64/kvm/va_layout.c
View File

@@ -288,3 +288,10 @@ void kvm_get_kimage_voffset(struct alt_instr *alt,
{
generate_mov_q(kimage_voffset, origptr, updptr, nr_inst);
}
void kvm_compute_final_ctr_el0(struct alt_instr *alt,
__le32 *origptr, __le32 *updptr, int nr_inst)
{
generate_mov_q(read_sanitised_ftr_reg(SYS_CTR_EL0),
origptr, updptr, nr_inst);
}

7
arch/arm64/mm/hugetlbpage.c
View File

@@ -252,7 +252,7 @@ void set_huge_swap_pte_at(struct mm_struct *mm, unsigned long addr,
set_pte(ptep, pte);
}
pte_t *huge_pte_alloc(struct mm_struct *mm,
pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long addr, unsigned long sz)
{
pgd_t *pgdp;
@@ -284,9 +284,8 @@ pte_t *huge_pte_alloc(struct mm_struct *mm,
*/
ptep = pte_alloc_map(mm, pmdp, addr);
} else if (sz == PMD_SIZE) {
if (IS_ENABLED(CONFIG_ARCH_WANT_HUGE_PMD_SHARE) &&
pud_none(READ_ONCE(*pudp)))
ptep = huge_pmd_share(mm, addr, pudp);
if (want_pmd_share(vma, addr) && pud_none(READ_ONCE(*pudp)))
ptep = huge_pmd_share(mm, vma, addr, pudp);
else
ptep = (pte_t *)pmd_alloc(mm, pudp, addr);
} else if (sz == (CONT_PMD_SIZE)) {

22
arch/arm64/mm/mmu.c
View File

@@ -1450,14 +1450,30 @@ static void __remove_pgd_mapping(pgd_t *pgdir, unsigned long start, u64 size)
static bool inside_linear_region(u64 start, u64 size)
{
u64 start_linear_pa = __pa(_PAGE_OFFSET(vabits_actual));
u64 end_linear_pa = __pa(PAGE_END - 1);
if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) {
/*
* Check for a wrap, it is possible because of randomized linear
* mapping the start physical address is actually bigger than
* the end physical address. In this case set start to zero
* because [0, end_linear_pa] range must still be able to cover
* all addressable physical addresses.
*/
if (start_linear_pa > end_linear_pa)
start_linear_pa = 0;
}
WARN_ON(start_linear_pa > end_linear_pa);
/*
* Linear mapping region is the range [PAGE_OFFSET..(PAGE_END - 1)]
* accommodating both its ends but excluding PAGE_END. Max physical
* range which can be mapped inside this linear mapping range, must
* also be derived from its end points.
*/
return start >= __pa(_PAGE_OFFSET(vabits_actual)) &&
(start + size - 1) <= __pa(PAGE_END - 1);
return start >= start_linear_pa && (start + size - 1) <= end_linear_pa;
}
int arch_add_memory(int nid, u64 start, u64 size,
@@ -1512,7 +1528,7 @@ int check_range_driver_managed(u64 start, u64 size, const char *resource_name)
res = lookup_resource(&iomem_resource, start);
if (!res) {
pr_err("%s: couldn't find memory resource for start 0x%lx\n",
pr_err("%s: couldn't find memory resource for start 0x%llx\n",
__func__, start);
return -EINVAL;
}

8
arch/ia64/include/asm/ptrace.h
View File

@@ -54,8 +54,7 @@
static inline unsigned long user_stack_pointer(struct pt_regs *regs)
{
/* FIXME: should this be bspstore + nr_dirty regs? */
return regs->ar_bspstore;
return regs->r12;
}
static inline int is_syscall_success(struct pt_regs *regs)
@@ -79,11 +78,6 @@ static inline long regs_return_value(struct pt_regs *regs)
unsigned long __ip = instruction_pointer(regs); \
(__ip & ~3UL) + ((__ip & 3UL) << 2); \
})
/*
* Why not default? Because user_stack_pointer() on ia64 gives register
* stack backing store instead...
*/
#define current_user_stack_pointer() (current_pt_regs()->r12)
/* given a pointer to a task_struct, return the user's pt_regs */
# define task_pt_regs(t) (((struct pt_regs *) ((char *) (t) + IA64_STK_OFFSET)) - 1)

2
arch/ia64/include/asm/syscall.h
View File

@@ -32,7 +32,7 @@ static inline void syscall_rollback(struct task_struct *task,
static inline long syscall_get_error(struct task_struct *task,
struct pt_regs *regs)
{
return regs->r10 == -1 ? regs->r8:0;
return regs->r10 == -1 ? -regs->r8:0;
}
static inline long syscall_get_return_value(struct task_struct *task,

22
arch/ia64/kernel/err_inject.c
View File

@@ -59,7 +59,7 @@ show_##name(struct device *dev, struct device_attribute *attr, \
char *buf) \
{ \
u32 cpu=dev->id; \
return sprintf(buf, "%lx\n", name[cpu]); \
return sprintf(buf, "%llx\n", name[cpu]); \
}
#define store(name) \
@@ -86,9 +86,9 @@ store_call_start(struct device *dev, struct device_attribute *attr,
#ifdef ERR_INJ_DEBUG
printk(KERN_DEBUG "pal_mc_err_inject for cpu%d:\n", cpu);
printk(KERN_DEBUG "err_type_info=%lx,\n", err_type_info[cpu]);
printk(KERN_DEBUG "err_struct_info=%lx,\n", err_struct_info[cpu]);
printk(KERN_DEBUG "err_data_buffer=%lx, %lx, %lx.\n",
printk(KERN_DEBUG "err_type_info=%llx,\n", err_type_info[cpu]);
printk(KERN_DEBUG "err_struct_info=%llx,\n", err_struct_info[cpu]);
printk(KERN_DEBUG "err_data_buffer=%llx, %llx, %llx.\n",
err_data_buffer[cpu].data1,
err_data_buffer[cpu].data2,
err_data_buffer[cpu].data3);
@@ -117,8 +117,8 @@ store_call_start(struct device *dev, struct device_attribute *attr,
#ifdef ERR_INJ_DEBUG
printk(KERN_DEBUG "Returns: status=%d,\n", (int)status[cpu]);
printk(KERN_DEBUG "capabilities=%lx,\n", capabilities[cpu]);
printk(KERN_DEBUG "resources=%lx\n", resources[cpu]);
printk(KERN_DEBUG "capabilities=%llx,\n", capabilities[cpu]);
printk(KERN_DEBUG "resources=%llx\n", resources[cpu]);
#endif
return size;
}
@@ -131,7 +131,7 @@ show_virtual_to_phys(struct device *dev, struct device_attribute *attr,
char *buf)
{
unsigned int cpu=dev->id;
return sprintf(buf, "%lx\n", phys_addr[cpu]);
return sprintf(buf, "%llx\n", phys_addr[cpu]);
}
static ssize_t
@@ -145,7 +145,7 @@ store_virtual_to_phys(struct device *dev, struct device_attribute *attr,
ret = get_user_pages_fast(virt_addr, 1, FOLL_WRITE, NULL);
if (ret<=0) {
#ifdef ERR_INJ_DEBUG
printk("Virtual address %lx is not existing.\n",virt_addr);
printk("Virtual address %llx is not existing.\n", virt_addr);
#endif
return -EINVAL;
}
@@ -163,7 +163,7 @@ show_err_data_buffer(struct device *dev,
{
unsigned int cpu=dev->id;
return sprintf(buf, "%lx, %lx, %lx\n",
return sprintf(buf, "%llx, %llx, %llx\n",
err_data_buffer[cpu].data1,
err_data_buffer[cpu].data2,
err_data_buffer[cpu].data3);
@@ -178,13 +178,13 @@ store_err_data_buffer(struct device *dev,
int ret;
#ifdef ERR_INJ_DEBUG
printk("write err_data_buffer=[%lx,%lx,%lx] on cpu%d\n",
printk("write err_data_buffer=[%llx,%llx,%llx] on cpu%d\n",
err_data_buffer[cpu].data1,
err_data_buffer[cpu].data2,
err_data_buffer[cpu].data3,
cpu);
#endif
ret=sscanf(buf, "%lx, %lx, %lx",
ret = sscanf(buf, "%llx, %llx, %llx",
&err_data_buffer[cpu].data1,
&err_data_buffer[cpu].data2,
&err_data_buffer[cpu].data3);

2
arch/ia64/kernel/mca.c
View File

@@ -1822,7 +1822,7 @@ ia64_mca_cpu_init(void *cpu_data)
data = mca_bootmem();
first_time = 0;
} else
data = (void *)__get_free_pages(GFP_KERNEL,
data = (void *)__get_free_pages(GFP_ATOMIC,
get_order(sz));
if (!data)
panic("Could not allocate MCA memory for cpu %d\n",

24
arch/ia64/kernel/ptrace.c
View File

@@ -2010,27 +2010,39 @@ static void syscall_get_set_args_cb(struct unw_frame_info *info, void *data)
{
struct syscall_get_set_args *args = data;
struct pt_regs *pt = args->regs;
unsigned long *krbs, cfm, ndirty;
unsigned long *krbs, cfm, ndirty, nlocals, nouts;
int i, count;
if (unw_unwind_to_user(info) < 0)
return;
/*
* We get here via a few paths:
* - break instruction: cfm is shared with caller.
* syscall args are in out= regs, locals are non-empty.
* - epsinstruction: cfm is set by br.call
* locals don't exist.
*
* For both cases argguments are reachable in cfm.sof - cfm.sol.
* CFM: [ ... | sor: 17..14 | sol : 13..7 | sof : 6..0 ]
*/
cfm = pt->cr_ifs;
nlocals = (cfm >> 7) & 0x7f; /* aka sol */
nouts = (cfm & 0x7f) - nlocals; /* aka sof - sol */
krbs = (unsigned long *)info->task + IA64_RBS_OFFSET/8;
ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
count = 0;
if (in_syscall(pt))
count = min_t(int, args->n, cfm & 0x7f);
count = min_t(int, args->n, nouts);
/* Iterate over outs. */
for (i = 0; i < count; i++) {
int j = ndirty + nlocals + i + args->i;
if (args->rw)
*ia64_rse_skip_regs(krbs, ndirty + i + args->i) =
args->args[i];
*ia64_rse_skip_regs(krbs, j) = args->args[i];
else
args->args[i] = *ia64_rse_skip_regs(krbs,
ndirty + i + args->i);
args->args[i] = *ia64_rse_skip_regs(krbs, j);
}
if (!args->rw) {

3
arch/ia64/mm/hugetlbpage.c
View File

@@ -25,7 +25,8 @@ unsigned int hpage_shift = HPAGE_SHIFT_DEFAULT;
EXPORT_SYMBOL(hpage_shift);
pte_t *
huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long addr, unsigned long sz)
{
unsigned long taddr = htlbpage_to_page(addr);
pgd_t *pgd;

4
arch/mips/mm/hugetlbpage.c
View File

@@ -21,8 +21,8 @@
#include <asm/tlb.h>
#include <asm/tlbflush.h>
pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr,
unsigned long sz)
pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long addr, unsigned long sz)
{
pgd_t *pgd;
p4d_t *p4d;

2
arch/nds32/mm/cacheflush.c
View File

@@ -238,7 +238,7 @@ void flush_dcache_page(struct page *page)
{
struct address_space *mapping;
mapping = page_mapping(page);
mapping = page_mapping_file(page);
if (mapping && !mapping_mapped(mapping))
set_bit(PG_dcache_dirty, &page->flags);
else {

2
arch/parisc/include/asm/cmpxchg.h
View File

@@ -72,7 +72,7 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
#endif
case 4: return __cmpxchg_u32((unsigned int *)ptr,
(unsigned int)old, (unsigned int)new_);
case 1: return __cmpxchg_u8((u8 *)ptr, (u8)old, (u8)new_);
case 1: return __cmpxchg_u8((u8 *)ptr, old & 0xff, new_ & 0xff);
}
__cmpxchg_called_with_bad_pointer();
return old;

2
arch/parisc/mm/hugetlbpage.c
View File

@@ -44,7 +44,7 @@ hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
}
pte_t *huge_pte_alloc(struct mm_struct *mm,
pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long addr, unsigned long sz)
{
pgd_t *pgd;

8
arch/powerpc/include/asm/dcr-native.h
View File

@@ -53,8 +53,8 @@ static inline void mtdcrx(unsigned int reg, unsigned int val)
#define mfdcr(rn) \
({unsigned int rval; \
if (__builtin_constant_p(rn) && rn < 1024) \
asm volatile("mfdcr %0," __stringify(rn) \
: "=r" (rval)); \
asm volatile("mfdcr %0, %1" : "=r" (rval) \
: "n" (rn)); \
else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
rval = mfdcrx(rn); \
else \
@@ -64,8 +64,8 @@ static inline void mtdcrx(unsigned int reg, unsigned int val)
#define mtdcr(rn, v) \
do { \
if (__builtin_constant_p(rn) && rn < 1024) \
asm volatile("mtdcr " __stringify(rn) ",%0" \
: : "r" (v)); \
asm volatile("mtdcr %0, %1" \
: : "n" (rn), "r" (v)); \
else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
mtdcrx(rn, v); \
else \

3
arch/powerpc/mm/hugetlbpage.c
View File

@@ -106,7 +106,8 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
* At this point we do the placement change only for BOOK3S 64. This would
* possibly work on other subarchs.
*/
pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long addr, unsigned long sz)
{
pgd_t *pg;
p4d_t *p4;

7
arch/riscv/include/asm/uaccess.h
View File

@@ -306,7 +306,9 @@ do { \
* data types like structures or arrays.
*
* @ptr must have pointer-to-simple-variable type, and @x must be assignable
* to the result of dereferencing @ptr.
* to the result of dereferencing @ptr. The value of @x is copied to avoid
* re-ordering where @x is evaluated inside the block that enables user-space
* access (thus bypassing user space protection if @x is a function).
*
* Caller must check the pointer with access_ok() before calling this
* function.
@@ -316,12 +318,13 @@ do { \
#define __put_user(x, ptr) \
({ \
__typeof__(*(ptr)) __user *__gu_ptr = (ptr); \
__typeof__(*__gu_ptr) __val = (x); \
long __pu_err = 0; \
\
__chk_user_ptr(__gu_ptr); \
\
__enable_user_access(); \
__put_user_nocheck(x, __gu_ptr, __pu_err); \
__put_user_nocheck(__val, __gu_ptr, __pu_err); \
__disable_user_access(); \
\
__pu_err; \

1
arch/riscv/kernel/entry.S
View File

@@ -447,6 +447,7 @@ ENDPROC(__switch_to)
#endif
.section ".rodata"
.align LGREG
/* Exception vector table */
ENTRY(excp_vect_table)
RISCV_PTR do_trap_insn_misaligned

2
arch/s390/include/asm/vdso/data.h
View File

@@ -6,7 +6,7 @@
#include <vdso/datapage.h>
struct arch_vdso_data {
__u64 tod_steering_delta;
__s64 tod_steering_delta;
__u64 tod_steering_end;
};

6
arch/s390/kernel/cpcmd.c
View File

@@ -37,10 +37,12 @@ static int diag8_noresponse(int cmdlen)
static int diag8_response(int cmdlen, char *response, int *rlen)
{
unsigned long _cmdlen = cmdlen | 0x40000000L;
unsigned long _rlen = *rlen;
register unsigned long reg2 asm ("2") = (addr_t) cpcmd_buf;
register unsigned long reg3 asm ("3") = (addr_t) response;
register unsigned long reg4 asm ("4") = cmdlen | 0x40000000L;
register unsigned long reg5 asm ("5") = *rlen;
register unsigned long reg4 asm ("4") = _cmdlen;
register unsigned long reg5 asm ("5") = _rlen;
asm volatile(
" diag %2,%0,0x8\n"

1
arch/s390/kernel/time.c
View File

@@ -398,6 +398,7 @@ static void clock_sync_global(unsigned long long delta)
tod_steering_delta);
tod_steering_end = now + (abs(tod_steering_delta) << 15);
vdso_data->arch_data.tod_steering_end = tod_steering_end;
vdso_data->arch_data.tod_steering_delta = tod_steering_delta;
/* Update LPAR offset. */
if (ptff_query(PTFF_QTO) && ptff(&qto, sizeof(qto), PTFF_QTO) == 0)

2
arch/s390/mm/hugetlbpage.c
View File

@@ -189,7 +189,7 @@ pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
return pte;
}
pte_t *huge_pte_alloc(struct mm_struct *mm,
pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long addr, unsigned long sz)
{
pgd_t *pgdp;

2
arch/sh/mm/hugetlbpage.c
View File

@@ -21,7 +21,7 @@
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
pte_t *huge_pte_alloc(struct mm_struct *mm,
pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long addr, unsigned long sz)
{
pgd_t *pgd;

11
arch/sparc/kernel/traps_64.c
View File

@@ -275,13 +275,12 @@ bool is_no_fault_exception(struct pt_regs *regs)
asi = (regs->tstate >> 24); /* saved %asi */
else
asi = (insn >> 5); /* immediate asi */
if ((asi & 0xf2) == ASI_PNF) {
if (insn & 0x1000000) { /* op3[5:4]=3 */
handle_ldf_stq(insn, regs);
return true;
} else if (insn & 0x200000) { /* op3[2], stores */
if ((asi & 0xf6) == ASI_PNF) {
if (insn & 0x200000) /* op3[2], stores */
return false;
}
if (insn & 0x1000000) /* op3[5:4]=3 (fp) */
handle_ldf_stq(insn, regs);
else
handle_ld_nf(insn, regs);
return true;
}

2
arch/sparc/mm/hugetlbpage.c
View File

@@ -272,7 +272,7 @@ static unsigned long huge_tte_to_size(pte_t pte)
return size;
}
pte_t *huge_pte_alloc(struct mm_struct *mm,
pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long addr, unsigned long sz)
{
pgd_t *pgd;

1
arch/x86/Kconfig
View File

@@ -162,6 +162,7 @@ config X86
select HAVE_ARCH_TRANSPARENT_HUGEPAGE
select HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD if X86_64
select HAVE_ARCH_USERFAULTFD_WP if X86_64 && USERFAULTFD
select HAVE_ARCH_USERFAULTFD_MINOR if X86_64 && USERFAULTFD
select HAVE_ARCH_VMAP_STACK if X86_64
select HAVE_ARCH_WITHIN_STACK_FRAMES
select HAVE_ASM_MODVERSIONS

2
arch/x86/Makefile
View File

@@ -34,7 +34,7 @@ M16_CFLAGS := $(call cc-option, -m16, $(CODE16GCC_CFLAGS))
REALMODE_CFLAGS := $(M16_CFLAGS) -g -Os -DDISABLE_BRANCH_PROFILING \
-Wall -Wstrict-prototypes -march=i386 -mregparm=3 \
-fno-strict-aliasing -fomit-frame-pointer -fno-pic \
-mno-mmx -mno-sse
-mno-mmx -mno-sse $(call cc-option,-fcf-protection=none)
REALMODE_CFLAGS += -ffreestanding
REALMODE_CFLAGS += -fno-stack-protector

2
arch/x86/OWNERS Normal file
View File

@@ -0,0 +1,2 @@
# include OWNERS from the authoritative android-mainline branch
include kernel/common:android-mainline:/arch/x86/OWNERS

24
arch/x86/configs/gki_defconfig
View File

@@ -56,7 +56,6 @@ CONFIG_CMDLINE="stack_depot_disable=on"
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
CONFIG_ENERGY_MODEL=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_TIMES=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
@@ -87,6 +86,7 @@ CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_CLEANCACHE=y
CONFIG_CMA=y
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_SYSFS=y
CONFIG_CMA_AREAS=16
CONFIG_READ_ONLY_THP_FOR_FS=y
CONFIG_NET=y
@@ -203,13 +203,20 @@ CONFIG_MAC802154=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
CONFIG_NET_SCH_TBF=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_BASIC=y
CONFIG_NET_CLS_TCINDEX=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_NET_CLS_BPF=y
CONFIG_NET_CLS_MATCHALL=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_ACT_GACT=y
CONFIG_NET_ACT_MIRRED=y
CONFIG_VSOCKETS=y
CONFIG_BPF_JIT=y
CONFIG_BT=y
@@ -258,12 +265,12 @@ CONFIG_DM_DEFAULT_KEY=y
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_AVB=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_WIREGUARD=y
CONFIG_IFB=y
CONFIG_TUN=y
CONFIG_VETH=y
CONFIG_PHYLIB=y
@@ -277,11 +284,10 @@ CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
# CONFIG_USB_NET_CDCETHER is not set
# CONFIG_USB_NET_CDC_NCM is not set
# CONFIG_USB_NET_NET1080 is not set
# CONFIG_USB_NET_CDC_SUBSET is not set
# CONFIG_USB_NET_ZAURUS is not set
CONFIG_USB_NET_AQC111=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
@@ -432,6 +438,8 @@ CONFIG_EDAC=y
CONFIG_RTC_CLASS=y
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_SYSFS_STATS=y
CONFIG_DMABUF_HEAPS_DEFERRED_FREE=y
CONFIG_DMABUF_HEAPS_PAGE_POOL=y
CONFIG_UIO=y
CONFIG_VHOST_VSOCK=y
CONFIG_STAGING=y
@@ -446,7 +454,6 @@ CONFIG_IIO_BUFFER=y
CONFIG_IIO_TRIGGER=y
CONFIG_POWERCAP=y
CONFIG_DTPM=y
CONFIG_DTPM_CPU=y
CONFIG_RAS=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
@@ -565,16 +572,23 @@ CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_HEADERS_INSTALL=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_UBSAN=y
CONFIG_UBSAN_TRAP=y
CONFIG_UBSAN_LOCAL_BOUNDS=y
# CONFIG_UBSAN_MISC is not set
CONFIG_PAGE_OWNER=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_KFENCE=y
CONFIG_KFENCE_SAMPLE_INTERVAL=500
CONFIG_KFENCE_NUM_OBJECTS=63
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_TIMEOUT=-1
CONFIG_DETECT_HUNG_TASK=y
CONFIG_WQ_WATCHDOG=y
CONFIG_SCHEDSTATS=y
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_TRACEFS_DISABLE_AUTOMOUNT=y
CONFIG_UNWINDER_FRAME_POINTER=y
CONFIG_KUNIT=y
CONFIG_KUNIT_DEBUGFS=y

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