Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux
Pull RISC-V updates from Palmer Dabbelt:
"This contains an assortment of RISC-V related patches that I'd like to
target for the 5.2 merge window. Most of the patches are cleanups, but
there are a handful of user-visible changes:
- The nosmp and nr_cpus command-line arguments are now supported,
which work like normal.
- The SBI console no longer installs itself as a preferred console,
we rely on standard mechanisms (/chosen, command-line, hueristics)
instead.
- sfence_remove_sfence_vma{,_asid} now pass their arguments along to
the SBI call.
- Modules now support BUG().
- A missing sfence.vma during boot has been added. This bug only
manifests during boot.
- The arch/riscv support for SiFive's L2 cache controller has been
merged, which should un-block the EDAC framework work.
I've only tested this on QEMU again, as I didn't have time to get
things running on the Unleashed. The latest master from this morning
merges in cleanly and passes the tests as well"
* tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: (31 commits)
riscv: fix locking violation in page fault handler
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
RISC-V: Add DT documentation for SiFive L2 Cache Controller
RISC-V: Avoid using invalid intermediate translations
riscv: Support BUG() in kernel module
riscv: Add the support for c.ebreak check in is_valid_bugaddr()
riscv: support trap-based WARN()
riscv: fix sbi_remote_sfence_vma{,_asid}.
riscv: move switch_mm to its own file
riscv: move flush_icache_{all,mm} to cacheflush.c
tty: Don't force RISCV SBI console as preferred console
RISC-V: Access CSRs using CSR numbers
RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
RISC-V: Use tabs to align macro values in asm/csr.h
RISC-V: Fix minor checkpatch issues.
RISC-V: Support nr_cpus command line option.
RISC-V: Implement nosmp commandline option.
RISC-V: Add RISC-V specific arch_match_cpu_phys_id
riscv: vdso: drop unnecessary cc-ldoption
riscv: call pm_power_off from machine_halt / machine_power_off
...
This commit is contained in:
Linus Torvalds
@@ -9,3 +9,5 @@ obj-y += fault.o
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obj-y += extable.o
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obj-y += ioremap.o
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obj-y += cacheflush.o
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obj-y += context.o
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obj-y += sifive_l2_cache.o
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@@ -14,6 +14,67 @@
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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#ifdef CONFIG_SMP
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#include <asm/sbi.h>
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void flush_icache_all(void)
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{
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sbi_remote_fence_i(NULL);
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}
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/*
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* Performs an icache flush for the given MM context. RISC-V has no direct
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* mechanism for instruction cache shoot downs, so instead we send an IPI that
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* informs the remote harts they need to flush their local instruction caches.
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* To avoid pathologically slow behavior in a common case (a bunch of
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* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
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* IPIs for harts that are not currently executing a MM context and instead
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* schedule a deferred local instruction cache flush to be performed before
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* execution resumes on each hart.
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*/
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void flush_icache_mm(struct mm_struct *mm, bool local)
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{
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unsigned int cpu;
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cpumask_t others, hmask, *mask;
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preempt_disable();
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/* Mark every hart's icache as needing a flush for this MM. */
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mask = &mm->context.icache_stale_mask;
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cpumask_setall(mask);
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/* Flush this hart's I$ now, and mark it as flushed. */
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mask);
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local_flush_icache_all();
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/*
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* Flush the I$ of other harts concurrently executing, and mark them as
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* flushed.
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*/
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cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
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local |= cpumask_empty(&others);
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if (mm != current->active_mm || !local) {
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cpumask_clear(&hmask);
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riscv_cpuid_to_hartid_mask(&others, &hmask);
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sbi_remote_fence_i(hmask.bits);
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} else {
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/*
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* It's assumed that at least one strongly ordered operation is
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* performed on this hart between setting a hart's cpumask bit
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* and scheduling this MM context on that hart. Sending an SBI
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* remote message will do this, but in the case where no
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* messages are sent we still need to order this hart's writes
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* with flush_icache_deferred().
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*/
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smp_mb();
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}
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preempt_enable();
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}
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#endif /* CONFIG_SMP */
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void flush_icache_pte(pte_t pte)
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{
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struct page *page = pte_page(pte);
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69
arch/riscv/mm/context.c
Normal file
69
arch/riscv/mm/context.c
Normal file
@@ -0,0 +1,69 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/mm.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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/*
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* When necessary, performs a deferred icache flush for the given MM context,
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* on the local CPU. RISC-V has no direct mechanism for instruction cache
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* shoot downs, so instead we send an IPI that informs the remote harts they
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* need to flush their local instruction caches. To avoid pathologically slow
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* behavior in a common case (a bunch of single-hart processes on a many-hart
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* machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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* executing a MM context and instead schedule a deferred local instruction
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* cache flush to be performed before execution resumes on each hart. This
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* actually performs that local instruction cache flush, which implicitly only
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* refers to the current hart.
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*/
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static inline void flush_icache_deferred(struct mm_struct *mm)
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{
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#ifdef CONFIG_SMP
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unsigned int cpu = smp_processor_id();
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cpumask_t *mask = &mm->context.icache_stale_mask;
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if (cpumask_test_cpu(cpu, mask)) {
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cpumask_clear_cpu(cpu, mask);
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/*
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* Ensure the remote hart's writes are visible to this hart.
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* This pairs with a barrier in flush_icache_mm.
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*/
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smp_mb();
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local_flush_icache_all();
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}
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#endif
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}
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void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *task)
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{
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unsigned int cpu;
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if (unlikely(prev == next))
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return;
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/*
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* Mark the current MM context as inactive, and the next as
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* active. This is at least used by the icache flushing
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* routines in order to determine who should be flushed.
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*/
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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/*
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* Use the old spbtr name instead of using the current satp
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* name to support binutils 2.29 which doesn't know about the
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* privileged ISA 1.10 yet.
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*/
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csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE);
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local_flush_tlb_all();
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flush_icache_deferred(next);
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}
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@@ -229,8 +229,9 @@ vmalloc_fault:
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pte_t *pte_k;
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int index;
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/* User mode accesses just cause a SIGSEGV */
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if (user_mode(regs))
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goto bad_area;
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return do_trap(regs, SIGSEGV, code, addr, tsk);
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/*
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* Synchronize this task's top level page-table
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@@ -239,13 +240,9 @@ vmalloc_fault:
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* Do _not_ use "tsk->active_mm->pgd" here.
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* We might be inside an interrupt in the middle
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* of a task switch.
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*
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* Note: Use the old spbtr name instead of using the current
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* satp name to support binutils 2.29 which doesn't know about
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* the privileged ISA 1.10 yet.
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*/
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index = pgd_index(addr);
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pgd = (pgd_t *)pfn_to_virt(csr_read(sptbr)) + index;
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pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP)) + index;
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pgd_k = init_mm.pgd + index;
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if (!pgd_present(*pgd_k))
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175
arch/riscv/mm/sifive_l2_cache.c
Normal file
175
arch/riscv/mm/sifive_l2_cache.c
Normal file
@@ -0,0 +1,175 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SiFive L2 cache controller Driver
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*
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* Copyright (C) 2018-2019 SiFive, Inc.
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*
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*/
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#include <linux/debugfs.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <asm/sifive_l2_cache.h>
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#define SIFIVE_L2_DIRECCFIX_LOW 0x100
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#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
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#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
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#define SIFIVE_L2_DATECCFIX_LOW 0x140
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#define SIFIVE_L2_DATECCFIX_HIGH 0x144
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#define SIFIVE_L2_DATECCFIX_COUNT 0x148
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#define SIFIVE_L2_DATECCFAIL_LOW 0x160
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#define SIFIVE_L2_DATECCFAIL_HIGH 0x164
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#define SIFIVE_L2_DATECCFAIL_COUNT 0x168
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#define SIFIVE_L2_CONFIG 0x00
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#define SIFIVE_L2_WAYENABLE 0x08
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#define SIFIVE_L2_ECCINJECTERR 0x40
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#define SIFIVE_L2_MAX_ECCINTR 3
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static void __iomem *l2_base;
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static int g_irq[SIFIVE_L2_MAX_ECCINTR];
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enum {
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DIR_CORR = 0,
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DATA_CORR,
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DATA_UNCORR,
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};
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#ifdef CONFIG_DEBUG_FS
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static struct dentry *sifive_test;
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static ssize_t l2_write(struct file *file, const char __user *data,
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size_t count, loff_t *ppos)
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{
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unsigned int val;
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if (kstrtouint_from_user(data, count, 0, &val))
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return -EINVAL;
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if ((val >= 0 && val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
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writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
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else
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return -EINVAL;
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return count;
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}
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static const struct file_operations l2_fops = {
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.owner = THIS_MODULE,
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.open = simple_open,
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.write = l2_write
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};
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static void setup_sifive_debug(void)
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{
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sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
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debugfs_create_file("sifive_debug_inject_error", 0200,
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sifive_test, NULL, &l2_fops);
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}
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#endif
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static void l2_config_read(void)
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{
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u32 regval, val;
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regval = readl(l2_base + SIFIVE_L2_CONFIG);
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val = regval & 0xFF;
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pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
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val = (regval & 0xFF00) >> 8;
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pr_info("L2CACHE: No. of ways per bank: %d\n", val);
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val = (regval & 0xFF0000) >> 16;
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pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
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val = (regval & 0xFF000000) >> 24;
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pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
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regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
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pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
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}
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static const struct of_device_id sifive_l2_ids[] = {
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{ .compatible = "sifive,fu540-c000-ccache" },
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{ /* end of table */ },
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};
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static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
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int register_sifive_l2_error_notifier(struct notifier_block *nb)
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{
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return atomic_notifier_chain_register(&l2_err_chain, nb);
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}
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EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
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int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
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{
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return atomic_notifier_chain_unregister(&l2_err_chain, nb);
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}
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EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
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static irqreturn_t l2_int_handler(int irq, void *device)
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{
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unsigned int regval, add_h, add_l;
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if (irq == g_irq[DIR_CORR]) {
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add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
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add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
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pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
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regval = readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
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atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
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"DirECCFix");
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}
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if (irq == g_irq[DATA_CORR]) {
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add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
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add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
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pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
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regval = readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
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atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
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"DatECCFix");
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}
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if (irq == g_irq[DATA_UNCORR]) {
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add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
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add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
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pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
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regval = readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
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atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
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"DatECCFail");
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}
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return IRQ_HANDLED;
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}
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int __init sifive_l2_init(void)
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{
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struct device_node *np;
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struct resource res;
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int i, rc;
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np = of_find_matching_node(NULL, sifive_l2_ids);
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if (!np)
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return -ENODEV;
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if (of_address_to_resource(np, 0, &res))
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return -ENODEV;
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l2_base = ioremap(res.start, resource_size(&res));
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if (!l2_base)
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return -ENOMEM;
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for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
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g_irq[i] = irq_of_parse_and_map(np, i);
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rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
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if (rc) {
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pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
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return rc;
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}
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}
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l2_config_read();
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#ifdef CONFIG_DEBUG_FS
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setup_sifive_debug();
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#endif
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return 0;
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}
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device_initcall(sifive_l2_init);
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Reference in New Issue
Block a user