Merge tag 'pinctrl-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.20 series:
There were no significant changes to the core this time! Bur the new
Qualcomm, Mediatek and Broadcom drivers are quite interesting as they
will be used in a few million embedded devices the coming years as it
seems.
New drivers:
- Broadcom Northstar pin control driver.
- Mediatek MT8183 subdriver.
- Mediatek MT7623 subdriver.
- Mediatek MT6765 subdriver.
- Meson g12a subdriver.
- Nuvoton NPCM7xx pin control and GPIO driver.
- Qualcomm QCS404 pin control and GPIO subdriver.
- Qualcomm SDM660 pin control and GPIO subdriver.
- Renesas R8A7744 PFC subdriver.
- Renesas R8A774C0 PFC subdriver.
- Renesas RZ/N1 pinctrl driver
Major improvements:
- Pulled the GPIO support for Ingenic over from the GPIO subsystem
and consolidated it all in the Ingenic pin control driver.
- Major cleanups and consolidation work in all Intel drivers.
- Major cleanups and consolidation work in all Mediatek drivers.
- Lots of incremental improvements to the Renesas PFC pin controller
family.
- All drivers doing GPIO now include <linux/gpio/driver.h> and
nothing else"
* tag 'pinctrl-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits)
pinctrl: sunxi: Fix a memory leak in 'sunxi_pinctrl_build_state()'
gpio: uniphier: include <linux/bits.h> instead of <linux/bitops.h>
pinctrl: uniphier: include <linux/bits.h> instead of <linux/bitops.h>
dt-bindings: pinctrl: bcm4708-pinmux: improve example binding
pinctrl: geminilake: Sort register offsets by value
pinctrl: geminilake: Get rid of unneeded ->probe() stub
pinctrl: geminilake: Update pin list for B0 stepping
pinctrl: renesas: Fix platform_no_drv_owner.cocci warnings
pinctrl: mediatek: Make eint_m u16
pinctrl: bcm: ns: Use uintptr_t for casting data
pinctrl: madera: Fix uninitialized variable bug in madera_mux_set_mux
pinctrl: gemini: Fix up TVC clock group
pinctrl: gemini: Drop noisy debug prints
pinctrl: gemini: Mask and set properly
pinctrl: mediatek: select GPIOLIB
pinctrl: rza1: don't manually release devm managed resources
MAINTAINERS: update entry for Mediatek pin controller
pinctrl: bcm: add Northstar driver
dt-bindings: pinctrl: document Broadcom Northstar pin mux controller
pinctrl: qcom: fix 'const' pointer handling
...
This commit is contained in:
Linus Torvalds
114
include/dt-bindings/gpio/meson-g12a-gpio.h
Normal file
114
include/dt-bindings/gpio/meson-g12a-gpio.h
Normal file
@@ -0,0 +1,114 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
|
||||
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
|
||||
#define _DT_BINDINGS_MESON_G12A_GPIO_H
|
||||
|
||||
/* First GPIO chip */
|
||||
#define GPIOAO_0 0
|
||||
#define GPIOAO_1 1
|
||||
#define GPIOAO_2 2
|
||||
#define GPIOAO_3 3
|
||||
#define GPIOAO_4 4
|
||||
#define GPIOAO_5 5
|
||||
#define GPIOAO_6 6
|
||||
#define GPIOAO_7 7
|
||||
#define GPIOAO_8 8
|
||||
#define GPIOAO_9 9
|
||||
#define GPIOAO_10 10
|
||||
#define GPIOAO_11 11
|
||||
#define GPIOE_0 12
|
||||
#define GPIOE_1 13
|
||||
#define GPIOE_2 14
|
||||
|
||||
/* Second GPIO chip */
|
||||
#define GPIOZ_0 0
|
||||
#define GPIOZ_1 1
|
||||
#define GPIOZ_2 2
|
||||
#define GPIOZ_3 3
|
||||
#define GPIOZ_4 4
|
||||
#define GPIOZ_5 5
|
||||
#define GPIOZ_6 6
|
||||
#define GPIOZ_7 7
|
||||
#define GPIOZ_8 8
|
||||
#define GPIOZ_9 9
|
||||
#define GPIOZ_10 10
|
||||
#define GPIOZ_11 11
|
||||
#define GPIOZ_12 12
|
||||
#define GPIOZ_13 13
|
||||
#define GPIOZ_14 14
|
||||
#define GPIOZ_15 15
|
||||
#define GPIOH_0 16
|
||||
#define GPIOH_1 17
|
||||
#define GPIOH_2 18
|
||||
#define GPIOH_3 19
|
||||
#define GPIOH_4 20
|
||||
#define GPIOH_5 21
|
||||
#define GPIOH_6 22
|
||||
#define GPIOH_7 23
|
||||
#define GPIOH_8 24
|
||||
#define BOOT_0 25
|
||||
#define BOOT_1 26
|
||||
#define BOOT_2 27
|
||||
#define BOOT_3 28
|
||||
#define BOOT_4 29
|
||||
#define BOOT_5 30
|
||||
#define BOOT_6 31
|
||||
#define BOOT_7 32
|
||||
#define BOOT_8 33
|
||||
#define BOOT_9 34
|
||||
#define BOOT_10 35
|
||||
#define BOOT_11 36
|
||||
#define BOOT_12 37
|
||||
#define BOOT_13 38
|
||||
#define BOOT_14 39
|
||||
#define BOOT_15 40
|
||||
#define GPIOC_0 41
|
||||
#define GPIOC_1 42
|
||||
#define GPIOC_2 43
|
||||
#define GPIOC_3 44
|
||||
#define GPIOC_4 45
|
||||
#define GPIOC_5 46
|
||||
#define GPIOC_6 47
|
||||
#define GPIOC_7 48
|
||||
#define GPIOA_0 49
|
||||
#define GPIOA_1 50
|
||||
#define GPIOA_2 51
|
||||
#define GPIOA_3 52
|
||||
#define GPIOA_4 53
|
||||
#define GPIOA_5 54
|
||||
#define GPIOA_6 55
|
||||
#define GPIOA_7 56
|
||||
#define GPIOA_8 57
|
||||
#define GPIOA_9 58
|
||||
#define GPIOA_10 59
|
||||
#define GPIOA_11 60
|
||||
#define GPIOA_12 61
|
||||
#define GPIOA_13 62
|
||||
#define GPIOA_14 63
|
||||
#define GPIOA_15 64
|
||||
#define GPIOX_0 65
|
||||
#define GPIOX_1 66
|
||||
#define GPIOX_2 67
|
||||
#define GPIOX_3 68
|
||||
#define GPIOX_4 69
|
||||
#define GPIOX_5 70
|
||||
#define GPIOX_6 71
|
||||
#define GPIOX_7 72
|
||||
#define GPIOX_8 73
|
||||
#define GPIOX_9 74
|
||||
#define GPIOX_10 75
|
||||
#define GPIOX_11 76
|
||||
#define GPIOX_12 77
|
||||
#define GPIOX_13 78
|
||||
#define GPIOX_14 79
|
||||
#define GPIOX_15 80
|
||||
#define GPIOX_16 81
|
||||
#define GPIOX_17 82
|
||||
#define GPIOX_18 83
|
||||
#define GPIOX_19 84
|
||||
|
||||
#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
|
||||
141
include/dt-bindings/pinctrl/rzn1-pinctrl.h
Normal file
141
include/dt-bindings/pinctrl/rzn1-pinctrl.h
Normal file
@@ -0,0 +1,141 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Defines macros and constants for Renesas RZ/N1 pin controller pin
|
||||
* muxing functions.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_RZN1_PINCTRL_H
|
||||
#define __DT_BINDINGS_RZN1_PINCTRL_H
|
||||
|
||||
#define RZN1_PINMUX(_gpio, _func) \
|
||||
(((_func) << 8) | (_gpio))
|
||||
|
||||
/*
|
||||
* Given the different levels of muxing on the SoC, it was decided to
|
||||
* 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO
|
||||
* muxes are all represented by one single value.
|
||||
*
|
||||
* You can derive the hardware value pretty easily too, as
|
||||
* 0...9 are Level 1
|
||||
* 10...71 are Level 2. The Level 2 mux will be set to this
|
||||
* value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be
|
||||
* set accordingly.
|
||||
* 72...103 are for the 2 MDIO muxes.
|
||||
*/
|
||||
#define RZN1_FUNC_HIGHZ 0
|
||||
#define RZN1_FUNC_0L 1
|
||||
#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2
|
||||
#define RZN1_FUNC_CLK_ETH_NAND 3
|
||||
#define RZN1_FUNC_QSPI 4
|
||||
#define RZN1_FUNC_SDIO 5
|
||||
#define RZN1_FUNC_LCD 6
|
||||
#define RZN1_FUNC_LCD_E 7
|
||||
#define RZN1_FUNC_MSEBIM 8
|
||||
#define RZN1_FUNC_MSEBIS 9
|
||||
#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */
|
||||
|
||||
#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0)
|
||||
#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1)
|
||||
#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2)
|
||||
#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3)
|
||||
#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4)
|
||||
#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5)
|
||||
#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6)
|
||||
#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7)
|
||||
#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8)
|
||||
#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9)
|
||||
#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10)
|
||||
#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11)
|
||||
#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12)
|
||||
#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13)
|
||||
#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14)
|
||||
#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15)
|
||||
#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16)
|
||||
#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17)
|
||||
#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18)
|
||||
#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19)
|
||||
#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20)
|
||||
#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21)
|
||||
#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22)
|
||||
#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23)
|
||||
#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24)
|
||||
#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25)
|
||||
#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26)
|
||||
#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27)
|
||||
#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28)
|
||||
#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29)
|
||||
#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30)
|
||||
#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31)
|
||||
#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32)
|
||||
#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33)
|
||||
#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34)
|
||||
#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35)
|
||||
#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36)
|
||||
#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37)
|
||||
#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38)
|
||||
#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39)
|
||||
#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40)
|
||||
#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41)
|
||||
#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42)
|
||||
#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43)
|
||||
#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44)
|
||||
#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45)
|
||||
#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46)
|
||||
#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47)
|
||||
#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48)
|
||||
#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49)
|
||||
#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50)
|
||||
#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51)
|
||||
#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52)
|
||||
#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53)
|
||||
#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54)
|
||||
#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55)
|
||||
#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56)
|
||||
#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57)
|
||||
#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58)
|
||||
#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59)
|
||||
#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60)
|
||||
#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61)
|
||||
|
||||
#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62)
|
||||
|
||||
/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */
|
||||
#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0)
|
||||
#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1)
|
||||
#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2)
|
||||
#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3)
|
||||
#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4)
|
||||
#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5)
|
||||
#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6)
|
||||
#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7)
|
||||
/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
|
||||
#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8)
|
||||
#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9)
|
||||
#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10)
|
||||
#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11)
|
||||
#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12)
|
||||
#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13)
|
||||
#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14)
|
||||
#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15)
|
||||
|
||||
/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */
|
||||
#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16)
|
||||
#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17)
|
||||
#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18)
|
||||
#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19)
|
||||
#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20)
|
||||
#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21)
|
||||
#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22)
|
||||
#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23)
|
||||
/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
|
||||
#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24)
|
||||
#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25)
|
||||
#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26)
|
||||
#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27)
|
||||
#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28)
|
||||
#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29)
|
||||
#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30)
|
||||
#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31)
|
||||
|
||||
#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32)
|
||||
|
||||
#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */
|
||||
Reference in New Issue
Block a user