xiaomi-sm8450/android_kernel_xiaomi_sm8450
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Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next

Просмотр исходного кода 
* clk-mediatek:
  clk: mediatek: add audsys support for MT2701
  clk: mediatek: add devm_of_platform_populate() for MT7622 audsys
  dt-bindings: clock: mediatek: add audsys support for MT2701
  dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
  clk: mediatek: update missing clock data for MT7622 audsys
  clk: mediatek: fix PWM clock source by adding a fixed-factor clock
  dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4

* clk-hisi:
  clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
  clk: hisilicon: mark wdt_mux_p[] as const
  clk: hisilicon: Mark phase_ops static
  clk: hi3798cv200: add emmc sample and drive clock
  clk: hisilicon: add hisi phase clock support
  clk: hi3798cv200: add COMBPHY0 clock support
  clk: hi3798cv200: fix define indentation
  clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
  clk: hi3798cv200: correct IR clock parent
  clk: hi3798cv200: fix unregister call sequence in error path

* clk-allwinner:
  clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
  clk: sunxi-ng: add support for the Allwinner H6 CCU
  dt-bindings: add device tree binding for Allwinner H6 main CCU
  clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
  clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
  clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
  clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
  clk: sunxi-ng: Add check for minimal rate to NM PLLs
  clk: sunxi-ng: Use u64 for calculation of nkmp rate
  clk: sunxi-ng: Mask nkmp factors when setting register
  clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name

* clk-ux500:
  clk: ux500: Drop AB8540/9540 support

* clk-renesas: (27 commits)
  clk: renesas: cpg-mssr: Adjust r8a77980 ifdef
  clk: renesas: rcar-gen3: Always use readl()/writel()
  clk: renesas: sh73a0: Always use readl()/writel()
  clk: renesas: rza1: Always use readl()/writel()
  clk: renesas: rcar-gen2: Always use readl()/writel()
  clk: renesas: r8a7740: Always use readl()/writel()
  clk: renesas: r8a73a4: Always use readl()/writel()
  clk: renesas: mstp: Always use readl()/writel()
  clk: renesas: div6: Always use readl()/writel()
  clk: fix false-positive Wmaybe-uninitialized warning
  clk: renesas: r8a77965: Replace DU2 clock
  clk: renesas: cpg-mssr: Add support for R-Car M3-N
  clk: renesas: cpg-mssr: add R8A77980 support
  dt-bindings: clock: add R8A77980 CPG core clock definitions
  clk: renesas: r8a7792: Add rwdt clock
  clk: renesas: r8a7794: Add rwdt clock
  clk: renesas: r8a7791/r8a7793: Add rwdt clock
  clk: renesas: r8a7790: Add rwdt clock
  clk: renesas: r8a7745: Add rwdt clock
  clk: renesas: r8a7743: Add rwdt clock
  ...
Этот коммит содержится в:
Stephen Boyd
2018-04-06 13:21:57 -07:00
родитель fbc20b8c3c b572f6393e c744b63b6c 26b99db0b6 726fef09b8 aa584d28f3
Коммит b03781920c
59 изменённых файлов: 2980 добавлений и 793 удалений
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55
include/dt-bindings/clock/histb-clock.h
Просмотреть файл

@@ -22,18 +22,18 @@
#define HISTB_OSC_CLK 0
#define HISTB_APB_CLK 1
#define HISTB_AHB_CLK 2
#define HISTB_UART1_CLK 3
#define HISTB_UART2_CLK 4
#define HISTB_UART3_CLK 5
#define HISTB_I2C0_CLK 6
#define HISTB_I2C1_CLK 7
#define HISTB_I2C2_CLK 8
#define HISTB_I2C3_CLK 9
#define HISTB_I2C4_CLK 10
#define HISTB_I2C5_CLK 11
#define HISTB_SPI0_CLK 12
#define HISTB_SPI1_CLK 13
#define HISTB_SPI2_CLK 14
#define HISTB_UART1_CLK 3
#define HISTB_UART2_CLK 4
#define HISTB_UART3_CLK 5
#define HISTB_I2C0_CLK 6
#define HISTB_I2C1_CLK 7
#define HISTB_I2C2_CLK 8
#define HISTB_I2C3_CLK 9
#define HISTB_I2C4_CLK 10
#define HISTB_I2C5_CLK 11
#define HISTB_SPI0_CLK 12
#define HISTB_SPI1_CLK 13
#define HISTB_SPI2_CLK 14
#define HISTB_SCI_CLK 15
#define HISTB_FMC_CLK 16
#define HISTB_MMC_BIU_CLK 17
@@ -43,7 +43,7 @@
#define HISTB_SDIO0_BIU_CLK 21
#define HISTB_SDIO0_CIU_CLK 22
#define HISTB_SDIO0_DRV_CLK 23
#define HISTB_SDIO0_SAMPLE_CLK 24
#define HISTB_SDIO0_SAMPLE_CLK 24
#define HISTB_PCIE_AUX_CLK 25
#define HISTB_PCIE_PIPE_CLK 26
#define HISTB_PCIE_SYS_CLK 27
@@ -53,21 +53,22 @@
#define HISTB_ETH1_MAC_CLK 31
#define HISTB_ETH1_MACIF_CLK 32
#define HISTB_COMBPHY1_CLK 33
#define HISTB_USB2_BUS_CLK 34
#define HISTB_USB2_PHY_CLK 35
#define HISTB_USB2_UTMI_CLK 36
#define HISTB_USB2_12M_CLK 37
#define HISTB_USB2_48M_CLK 38
#define HISTB_USB2_OTG_UTMI_CLK 39
#define HISTB_USB2_PHY1_REF_CLK 40
#define HISTB_USB2_PHY2_REF_CLK 41
#define HISTB_USB2_BUS_CLK 34
#define HISTB_USB2_PHY_CLK 35
#define HISTB_USB2_UTMI_CLK 36
#define HISTB_USB2_12M_CLK 37
#define HISTB_USB2_48M_CLK 38
#define HISTB_USB2_OTG_UTMI_CLK 39
#define HISTB_USB2_PHY1_REF_CLK 40
#define HISTB_USB2_PHY2_REF_CLK 41
#define HISTB_COMBPHY0_CLK 42
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1
#define HISTB_IR_CLK 2
#define HISTB_TIMER01_CLK 3
#define HISTB_LEDC_CLK 4
#define HISTB_UART0_CLK 5
#define HISTB_LSADC_CLK 6
#define HISTB_MCE_CLK 1
#define HISTB_IR_CLK 2
#define HISTB_TIMER01_CLK 3
#define HISTB_LEDC_CLK 4
#define HISTB_UART0_CLK 5
#define HISTB_LSADC_CLK 6
#endif /* __DTS_HISTB_CLOCK_H */

3
include/dt-bindings/clock/mt2701-clk.h
Просмотреть файл

@@ -176,7 +176,8 @@
#define CLK_TOP_AUD_EXT1 156
#define CLK_TOP_AUD_EXT2 157
#define CLK_TOP_NFI1X_PAD 158
#define CLK_TOP_NR 159
#define CLK_TOP_AXISEL_D4 159
#define CLK_TOP_NR 160
/* APMIXEDSYS */

3
include/dt-bindings/clock/mt7622-clk.h
Просмотреть файл

@@ -235,7 +235,8 @@
#define CLK_AUDIO_MEM_ASRC3 43
#define CLK_AUDIO_MEM_ASRC4 44
#define CLK_AUDIO_MEM_ASRC5 45
#define CLK_AUDIO_NR_CLK 46
#define CLK_AUDIO_AFE_CONN 46
#define CLK_AUDIO_NR_CLK 47
/* SSUSBSYS */

62
include/dt-bindings/clock/r8a77965-cpg-mssr.h Обычный файл
Просмотреть файл

@@ -0,0 +1,62 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a77965 CPG Core Clocks */
#define R8A77965_CLK_Z 0
#define R8A77965_CLK_ZR 1
#define R8A77965_CLK_ZG 2
#define R8A77965_CLK_ZTR 3
#define R8A77965_CLK_ZTRD2 4
#define R8A77965_CLK_ZT 5
#define R8A77965_CLK_ZX 6
#define R8A77965_CLK_S0D1 7
#define R8A77965_CLK_S0D2 8
#define R8A77965_CLK_S0D3 9
#define R8A77965_CLK_S0D4 10
#define R8A77965_CLK_S0D6 11
#define R8A77965_CLK_S0D8 12
#define R8A77965_CLK_S0D12 13
#define R8A77965_CLK_S1D1 14
#define R8A77965_CLK_S1D2 15
#define R8A77965_CLK_S1D4 16
#define R8A77965_CLK_S2D1 17
#define R8A77965_CLK_S2D2 18
#define R8A77965_CLK_S2D4 19
#define R8A77965_CLK_S3D1 20
#define R8A77965_CLK_S3D2 21
#define R8A77965_CLK_S3D4 22
#define R8A77965_CLK_LB 23
#define R8A77965_CLK_CL 24
#define R8A77965_CLK_ZB3 25
#define R8A77965_CLK_ZB3D2 26
#define R8A77965_CLK_CR 27
#define R8A77965_CLK_CRD2 28
#define R8A77965_CLK_SD0H 29
#define R8A77965_CLK_SD0 30
#define R8A77965_CLK_SD1H 31
#define R8A77965_CLK_SD1 32
#define R8A77965_CLK_SD2H 33
#define R8A77965_CLK_SD2 34
#define R8A77965_CLK_SD3H 35
#define R8A77965_CLK_SD3 36
#define R8A77965_CLK_SSP2 37
#define R8A77965_CLK_SSP1 38
#define R8A77965_CLK_SSPRS 39
#define R8A77965_CLK_RPC 40
#define R8A77965_CLK_RPCD2 41
#define R8A77965_CLK_MSO 42
#define R8A77965_CLK_CANFD 43
#define R8A77965_CLK_HDMI 44
#define R8A77965_CLK_CSI0 45
#define R8A77965_CLK_CP 46
#define R8A77965_CLK_CPEX 47
#define R8A77965_CLK_R 48
#define R8A77965_CLK_OSC 49
#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */

51
include/dt-bindings/clock/r8a77980-cpg-mssr.h Обычный файл
Просмотреть файл

@@ -0,0 +1,51 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a77980 CPG Core Clocks */
#define R8A77980_CLK_Z2 0
#define R8A77980_CLK_ZR 1
#define R8A77980_CLK_ZTR 2
#define R8A77980_CLK_ZTRD2 3
#define R8A77980_CLK_ZT 4
#define R8A77980_CLK_ZX 5
#define R8A77980_CLK_S0D1 6
#define R8A77980_CLK_S0D2 7
#define R8A77980_CLK_S0D3 8
#define R8A77980_CLK_S0D4 9
#define R8A77980_CLK_S0D6 10
#define R8A77980_CLK_S0D12 11
#define R8A77980_CLK_S0D24 12
#define R8A77980_CLK_S1D1 13
#define R8A77980_CLK_S1D2 14
#define R8A77980_CLK_S1D4 15
#define R8A77980_CLK_S2D1 16
#define R8A77980_CLK_S2D2 17
#define R8A77980_CLK_S2D4 18
#define R8A77980_CLK_S3D1 19
#define R8A77980_CLK_S3D2 20
#define R8A77980_CLK_S3D4 21
#define R8A77980_CLK_LB 22
#define R8A77980_CLK_CL 23
#define R8A77980_CLK_ZB3 24
#define R8A77980_CLK_ZB3D2 25
#define R8A77980_CLK_ZB3D4 26
#define R8A77980_CLK_SD0H 27
#define R8A77980_CLK_SD0 28
#define R8A77980_CLK_RPC 29
#define R8A77980_CLK_RPCD2 30
#define R8A77980_CLK_MSO 31
#define R8A77980_CLK_CANFD 32
#define R8A77980_CLK_CSI0 33
#define R8A77980_CLK_CP 34
#define R8A77980_CLK_CPEX 35
#define R8A77980_CLK_R 36
#define R8A77980_CLK_OSC 37
#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */

125
include/dt-bindings/clock/sun50i-h6-ccu.h Обычный файл
Просмотреть файл

@@ -0,0 +1,125 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
#define _DT_BINDINGS_CLK_SUN50I_H6_H_
#define CLK_PLL_PERIPH0 3
#define CLK_CPUX 21
#define CLK_APB1 26
#define CLK_DE 29
#define CLK_BUS_DE 30
#define CLK_DEINTERLACE 31
#define CLK_BUS_DEINTERLACE 32
#define CLK_GPU 33
#define CLK_BUS_GPU 34
#define CLK_CE 35
#define CLK_BUS_CE 36
#define CLK_VE 37
#define CLK_BUS_VE 38
#define CLK_EMCE 39
#define CLK_BUS_EMCE 40
#define CLK_VP9 41
#define CLK_BUS_VP9 42
#define CLK_BUS_DMA 43
#define CLK_BUS_MSGBOX 44
#define CLK_BUS_SPINLOCK 45
#define CLK_BUS_HSTIMER 46
#define CLK_AVS 47
#define CLK_BUS_DBG 48
#define CLK_BUS_PSI 49
#define CLK_BUS_PWM 50
#define CLK_BUS_IOMMU 51
#define CLK_MBUS_DMA 53
#define CLK_MBUS_VE 54
#define CLK_MBUS_CE 55
#define CLK_MBUS_TS 56
#define CLK_MBUS_NAND 57
#define CLK_MBUS_CSI 58
#define CLK_MBUS_DEINTERLACE 59
#define CLK_NAND0 61
#define CLK_NAND1 62
#define CLK_BUS_NAND 63
#define CLK_MMC0 64
#define CLK_MMC1 65
#define CLK_MMC2 66
#define CLK_BUS_MMC0 67
#define CLK_BUS_MMC1 68
#define CLK_BUS_MMC2 69
#define CLK_BUS_UART0 70
#define CLK_BUS_UART1 71
#define CLK_BUS_UART2 72
#define CLK_BUS_UART3 73
#define CLK_BUS_I2C0 74
#define CLK_BUS_I2C1 75
#define CLK_BUS_I2C2 76
#define CLK_BUS_I2C3 77
#define CLK_BUS_SCR0 78
#define CLK_BUS_SCR1 79
#define CLK_SPI0 80
#define CLK_SPI1 81
#define CLK_BUS_SPI0 82
#define CLK_BUS_SPI1 83
#define CLK_BUS_EMAC 84
#define CLK_TS 85
#define CLK_BUS_TS 86
#define CLK_IR_TX 87
#define CLK_BUS_IR_TX 88
#define CLK_BUS_THS 89
#define CLK_I2S3 90
#define CLK_I2S0 91
#define CLK_I2S1 92
#define CLK_I2S2 93
#define CLK_BUS_I2S0 94
#define CLK_BUS_I2S1 95
#define CLK_BUS_I2S2 96
#define CLK_BUS_I2S3 97
#define CLK_SPDIF 98
#define CLK_BUS_SPDIF 99
#define CLK_DMIC 100
#define CLK_BUS_DMIC 101
#define CLK_AUDIO_HUB 102
#define CLK_BUS_AUDIO_HUB 103
#define CLK_USB_OHCI0 104
#define CLK_USB_PHY0 105
#define CLK_USB_PHY1 106
#define CLK_USB_OHCI3 107
#define CLK_USB_PHY3 108
#define CLK_USB_HSIC_12M 109
#define CLK_USB_HSIC 110
#define CLK_BUS_OHCI0 111
#define CLK_BUS_OHCI3 112
#define CLK_BUS_EHCI0 113
#define CLK_BUS_XHCI 114
#define CLK_BUS_EHCI3 115
#define CLK_BUS_OTG 116
#define CLK_PCIE_REF_100M 117
#define CLK_PCIE_REF 118
#define CLK_PCIE_REF_OUT 119
#define CLK_PCIE_MAXI 120
#define CLK_PCIE_AUX 121
#define CLK_BUS_PCIE 122
#define CLK_HDMI 123
#define CLK_HDMI_SLOW 124
#define CLK_HDMI_CEC 125
#define CLK_BUS_HDMI 126
#define CLK_BUS_TCON_TOP 127
#define CLK_TCON_LCD0 128
#define CLK_BUS_TCON_LCD0 129
#define CLK_TCON_TV0 130
#define CLK_BUS_TCON_TV0 131
#define CLK_CSI_CCI 132
#define CLK_CSI_TOP 133
#define CLK_CSI_MCLK 134
#define CLK_BUS_CSI 135
#define CLK_HDCP 136
#define CLK_BUS_HDCP 137
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */

2
include/dt-bindings/clock/sun8i-h3-ccu.h
Просмотреть файл

@@ -43,6 +43,8 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
#define _DT_BINDINGS_CLK_SUN8I_H3_H_
#define CLK_PLL_VIDEO 6
#define CLK_PLL_PERIPH0 9
#define CLK_CPUX 14

73
include/dt-bindings/reset/sun50i-h6-ccu.h Обычный файл
Просмотреть файл

@@ -0,0 +1,73 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
#define _DT_BINDINGS_RESET_SUN50I_H6_H_
#define RST_MBUS 0
#define RST_BUS_DE 1
#define RST_BUS_DEINTERLACE 2
#define RST_BUS_GPU 3
#define RST_BUS_CE 4
#define RST_BUS_VE 5
#define RST_BUS_EMCE 6
#define RST_BUS_VP9 7
#define RST_BUS_DMA 8
#define RST_BUS_MSGBOX 9
#define RST_BUS_SPINLOCK 10
#define RST_BUS_HSTIMER 11
#define RST_BUS_DBG 12
#define RST_BUS_PSI 13
#define RST_BUS_PWM 14
#define RST_BUS_IOMMU 15
#define RST_BUS_DRAM 16
#define RST_BUS_NAND 17
#define RST_BUS_MMC0 18
#define RST_BUS_MMC1 19
#define RST_BUS_MMC2 20
#define RST_BUS_UART0 21
#define RST_BUS_UART1 22
#define RST_BUS_UART2 23
#define RST_BUS_UART3 24
#define RST_BUS_I2C0 25
#define RST_BUS_I2C1 26
#define RST_BUS_I2C2 27
#define RST_BUS_I2C3 28
#define RST_BUS_SCR0 29
#define RST_BUS_SCR1 30
#define RST_BUS_SPI0 31
#define RST_BUS_SPI1 32
#define RST_BUS_EMAC 33
#define RST_BUS_TS 34
#define RST_BUS_IR_TX 35
#define RST_BUS_THS 36
#define RST_BUS_I2S0 37
#define RST_BUS_I2S1 38
#define RST_BUS_I2S2 39
#define RST_BUS_I2S3 40
#define RST_BUS_SPDIF 41
#define RST_BUS_DMIC 42
#define RST_BUS_AUDIO_HUB 43
#define RST_USB_PHY0 44
#define RST_USB_PHY1 45
#define RST_USB_PHY3 46
#define RST_USB_HSIC 47
#define RST_BUS_OHCI0 48
#define RST_BUS_OHCI3 49
#define RST_BUS_EHCI0 50
#define RST_BUS_XHCI 51
#define RST_BUS_EHCI3 52
#define RST_BUS_OTG 53
#define RST_BUS_PCIE 54
#define RST_PCIE_POWERUP 55
#define RST_BUS_HDMI 56
#define RST_BUS_HDMI_SUB 57
#define RST_BUS_TCON_TOP 58
#define RST_BUS_TCON_LCD0 59
#define RST_BUS_TCON_TV0 60
#define RST_BUS_CSI 61
#define RST_BUS_HDCP 62
#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */