Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next
* clk-mediatek: clk: mediatek: add audsys support for MT2701 clk: mediatek: add devm_of_platform_populate() for MT7622 audsys dt-bindings: clock: mediatek: add audsys support for MT2701 dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device clk: mediatek: update missing clock data for MT7622 audsys clk: mediatek: fix PWM clock source by adding a fixed-factor clock dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4 * clk-hisi: clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc() clk: hisilicon: mark wdt_mux_p[] as const clk: hisilicon: Mark phase_ops static clk: hi3798cv200: add emmc sample and drive clock clk: hisilicon: add hisi phase clock support clk: hi3798cv200: add COMBPHY0 clock support clk: hi3798cv200: fix define indentation clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK clk: hi3798cv200: correct IR clock parent clk: hi3798cv200: fix unregister call sequence in error path * clk-allwinner: clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU clk: sunxi-ng: add support for the Allwinner H6 CCU dt-bindings: add device tree binding for Allwinner H6 main CCU clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate clk: sunxi-ng: h3: h5: Add minimal rate for video PLL clk: sunxi-ng: Add check for minimal rate to NM PLLs clk: sunxi-ng: Use u64 for calculation of nkmp rate clk: sunxi-ng: Mask nkmp factors when setting register clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name * clk-ux500: clk: ux500: Drop AB8540/9540 support * clk-renesas: (27 commits) clk: renesas: cpg-mssr: Adjust r8a77980 ifdef clk: renesas: rcar-gen3: Always use readl()/writel() clk: renesas: sh73a0: Always use readl()/writel() clk: renesas: rza1: Always use readl()/writel() clk: renesas: rcar-gen2: Always use readl()/writel() clk: renesas: r8a7740: Always use readl()/writel() clk: renesas: r8a73a4: Always use readl()/writel() clk: renesas: mstp: Always use readl()/writel() clk: renesas: div6: Always use readl()/writel() clk: fix false-positive Wmaybe-uninitialized warning clk: renesas: r8a77965: Replace DU2 clock clk: renesas: cpg-mssr: Add support for R-Car M3-N clk: renesas: cpg-mssr: add R8A77980 support dt-bindings: clock: add R8A77980 CPG core clock definitions clk: renesas: r8a7792: Add rwdt clock clk: renesas: r8a7794: Add rwdt clock clk: renesas: r8a7791/r8a7793: Add rwdt clock clk: renesas: r8a7790: Add rwdt clock clk: renesas: r8a7745: Add rwdt clock clk: renesas: r8a7743: Add rwdt clock ...
This commit is contained in:
Stephen Boyd
@@ -54,6 +54,12 @@ config COMMON_CLK_MT2701_BDPSYS
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---help---
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This driver supports MediaTek MT2701 bdpsys clocks.
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config COMMON_CLK_MT2701_AUDSYS
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bool "Clock driver for Mediatek MT2701 audsys"
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depends on COMMON_CLK_MT2701
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---help---
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This driver supports Mediatek MT2701 audsys clocks.
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config COMMON_CLK_MT2712
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bool "Clock driver for MediaTek MT2712"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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@@ -6,6 +6,7 @@ obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
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obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o
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obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
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obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
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obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
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obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
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obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
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186
drivers/clk/mediatek/clk-mt2701-aud.c
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186
drivers/clk/mediatek/clk-mt2701-aud.c
Normal file
@@ -0,0 +1,186 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt2701-clk.h>
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#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audio0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audio1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audio2_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audio3_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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static const struct mtk_gate_regs audio0_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs audio1_cg_regs = {
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.set_ofs = 0x10,
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.clr_ofs = 0x10,
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.sta_ofs = 0x10,
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};
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static const struct mtk_gate_regs audio2_cg_regs = {
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.set_ofs = 0x14,
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.clr_ofs = 0x14,
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.sta_ofs = 0x14,
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};
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static const struct mtk_gate_regs audio3_cg_regs = {
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.set_ofs = 0x634,
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.clr_ofs = 0x634,
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.sta_ofs = 0x634,
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};
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static const struct mtk_gate audio_clks[] = {
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/* AUDIO0 */
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GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
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GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
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GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
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GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
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GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
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/* AUDIO1 */
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GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
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GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
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GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
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GATE_AUDIO1(CLK_AUD_I2SIN4, "audio_i2sin4", "aud_mux1_sel", 3),
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GATE_AUDIO1(CLK_AUD_I2SIN5, "audio_i2sin5", "aud_mux1_sel", 4),
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GATE_AUDIO1(CLK_AUD_I2SIN6, "audio_i2sin6", "aud_mux1_sel", 5),
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GATE_AUDIO1(CLK_AUD_I2SO1, "audio_i2so1", "aud_mux1_sel", 6),
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GATE_AUDIO1(CLK_AUD_I2SO2, "audio_i2so2", "aud_mux1_sel", 7),
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GATE_AUDIO1(CLK_AUD_I2SO3, "audio_i2so3", "aud_mux1_sel", 8),
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GATE_AUDIO1(CLK_AUD_I2SO4, "audio_i2so4", "aud_mux1_sel", 9),
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GATE_AUDIO1(CLK_AUD_I2SO5, "audio_i2so5", "aud_mux1_sel", 10),
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GATE_AUDIO1(CLK_AUD_I2SO6, "audio_i2so6", "aud_mux1_sel", 11),
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GATE_AUDIO1(CLK_AUD_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
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GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
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GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
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GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
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GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
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GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
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GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
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GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
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GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
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/* AUDIO2 */
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GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
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GATE_AUDIO2(CLK_AUD_MMIF_UL2, "audio_ul2", "aud_mux1_sel", 1),
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GATE_AUDIO2(CLK_AUD_MMIF_UL3, "audio_ul3", "aud_mux1_sel", 2),
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GATE_AUDIO2(CLK_AUD_MMIF_UL4, "audio_ul4", "aud_mux1_sel", 3),
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GATE_AUDIO2(CLK_AUD_MMIF_UL5, "audio_ul5", "aud_mux1_sel", 4),
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GATE_AUDIO2(CLK_AUD_MMIF_UL6, "audio_ul6", "aud_mux1_sel", 5),
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GATE_AUDIO2(CLK_AUD_MMIF_DL1, "audio_dl1", "aud_mux1_sel", 6),
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GATE_AUDIO2(CLK_AUD_MMIF_DL2, "audio_dl2", "aud_mux1_sel", 7),
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GATE_AUDIO2(CLK_AUD_MMIF_DL3, "audio_dl3", "aud_mux1_sel", 8),
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GATE_AUDIO2(CLK_AUD_MMIF_DL4, "audio_dl4", "aud_mux1_sel", 9),
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GATE_AUDIO2(CLK_AUD_MMIF_DL5, "audio_dl5", "aud_mux1_sel", 10),
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GATE_AUDIO2(CLK_AUD_MMIF_DL6, "audio_dl6", "aud_mux1_sel", 11),
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GATE_AUDIO2(CLK_AUD_MMIF_DLMCH, "audio_dlmch", "aud_mux1_sel", 12),
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GATE_AUDIO2(CLK_AUD_MMIF_ARB1, "audio_arb1", "aud_mux1_sel", 13),
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GATE_AUDIO2(CLK_AUD_MMIF_AWB1, "audio_awb", "aud_mux1_sel", 14),
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GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
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GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
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/* AUDIO3 */
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GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
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GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
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GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
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GATE_AUDIO3(CLK_AUD_ASRCI6, "audio_asrci6", "asm_h_sel", 5),
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GATE_AUDIO3(CLK_AUD_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
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GATE_AUDIO3(CLK_AUD_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
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GATE_AUDIO3(CLK_AUD_ASRCO5, "audio_asrco5", "asm_h_sel", 8),
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GATE_AUDIO3(CLK_AUD_ASRCO6, "audio_asrco6", "asm_h_sel", 9),
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GATE_AUDIO3(CLK_AUD_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
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GATE_AUDIO3(CLK_AUD_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
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GATE_AUDIO3(CLK_AUD_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
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GATE_AUDIO3(CLK_AUD_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
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GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
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};
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static const struct of_device_id of_match_clk_mt2701_aud[] = {
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{ .compatible = "mediatek,mt2701-audsys", },
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{}
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};
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static int clk_mt2701_aud_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
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mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r) {
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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goto err_clk_provider;
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}
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r = devm_of_platform_populate(&pdev->dev);
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if (r)
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goto err_plat_populate;
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return 0;
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err_plat_populate:
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of_clk_del_provider(node);
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err_clk_provider:
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return r;
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}
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static struct platform_driver clk_mt2701_aud_drv = {
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.probe = clk_mt2701_aud_probe,
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.driver = {
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.name = "clk-mt2701-aud",
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.of_match_table = of_match_clk_mt2701_aud,
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},
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};
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builtin_platform_driver(clk_mt2701_aud_drv);
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@@ -148,6 +148,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
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FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
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FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
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FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
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FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
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};
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static const char * const axi_parents[] = {
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@@ -857,13 +858,13 @@ static const struct mtk_gate peri_clks[] = {
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GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
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GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
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GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
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GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
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GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
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GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
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GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
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GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
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GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
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GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
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GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
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GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
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GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
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GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
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GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
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GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
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GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
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GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
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GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
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@@ -106,6 +106,7 @@ static const struct mtk_gate audio_clks[] = {
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GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
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GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
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GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
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GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
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/* AUDIO2 */
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GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
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GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
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@@ -149,11 +150,23 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev)
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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if (r) {
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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goto err_clk_provider;
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}
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r = devm_of_platform_populate(&pdev->dev);
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if (r)
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goto err_plat_populate;
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return 0;
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err_plat_populate:
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of_clk_del_provider(node);
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err_clk_provider:
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return r;
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}
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Reference in New Issue
Block a user