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x86/pmc_atom: Eisable a few S0ix wake up events for S0ix residency

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Disable PMC S0IX_WAKE_EN events coming from LPC block(unused) and
also from GPIO_SUS ored dedicated IRQs (must be disabled as per PMC
programming rule), GPIOSCORE ored dedicated IRQs (must be disabled
as per PMC programming rule), GPIO_SUS shared IRQ (not necessary
since the IOAPIC_DS wake event will still work), GPIO_SCORE shared
IRQ (not necessary since the IOAPIC_DS wake event will still work).

Signed-off-by: Aubrey Li <aubrey.li@linux.intel.com>
Link: http://lkml.kernel.org/r/53B0FF22.5080403@linux.intel.com
Signed-off-by: Olivier Leveque <olivier.leveque@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
Li, Aubrey
2014-06-30 14:09:38 +08:00
committed by H. Peter Anvin
parent 93e5eadd1f
commit b00055cade
2 changed files with 63 additions and 0 deletions
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21
arch/x86/include/asm/pmc_atom.h
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@@ -19,6 +19,27 @@
/* ValleyView Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
/* PMC Memory mapped IO registers */
#define PMC_BASE_ADDR_OFFSET 0x44
#define PMC_BASE_ADDR_MASK 0xFFFFFE00
#define PMC_MMIO_REG_LEN 0x100
#define PMC_REG_BIT_WIDTH 32
/* S0ix wake event control */
#define PMC_S0IX_WAKE_EN 0x3C
#define BIT_LPC_CLOCK_RUN BIT(4)
#define BIT_SHARED_IRQ_GPSC BIT(5)
#define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
#define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
#define BIT_SHARED_IRQ_GPSS BIT(20)
#define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \
BIT_SHARED_IRQ_GPSC | \
BIT_ORED_DEDICATED_IRQ_GPSS | \
BIT_ORED_DEDICATED_IRQ_GPSC | \
BIT_SHARED_IRQ_GPSS)
/* PMC I/O Registers */
#define ACPI_BASE_ADDR_OFFSET 0x40
#define ACPI_BASE_ADDR_MASK 0xFFFFFE00