ARC: Boot #2: Verbose Boot reporting / feature verification
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
@@ -12,8 +12,26 @@
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#ifdef __KERNEL__
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/* Build Configuration Registers */
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#define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
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#define ARC_REG_CRC_BCR 0x62
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#define ARC_REG_DVFB_BCR 0x64
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#define ARC_REG_EXTARITH_BCR 0x65
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#define ARC_REG_VECBASE_BCR 0x68
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#define ARC_REG_PERIBASE_BCR 0x69
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#define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */
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#define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */
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#define ARC_REG_MMU_BCR 0x6f
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#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
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#define ARC_REG_TIMERS_BCR 0x75
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#define ARC_REG_ICCM_BCR 0x78
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#define ARC_REG_XY_MEM_BCR 0x79
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#define ARC_REG_MAC_BCR 0x7a
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#define ARC_REG_MUL_BCR 0x7b
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#define ARC_REG_SWAP_BCR 0x7c
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#define ARC_REG_NORM_BCR 0x7d
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#define ARC_REG_MIXMAX_BCR 0x7e
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#define ARC_REG_BARREL_BCR 0x7f
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#define ARC_REG_D_UNCACH_BCR 0x6A
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/* status32 Bits Positions */
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#define STATUS_H_BIT 0 /* CPU Halted */
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@@ -88,16 +106,6 @@
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#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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#if defined(CONFIG_ARC_MMU_V1)
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#define CONFIG_ARC_MMU_VER 1
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#elif defined(CONFIG_ARC_MMU_V2)
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#else
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#error "Error: MMU ver"
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#endif
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/* MMU Management regs */
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#define ARC_REG_TLBPD0 0x405
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#define ARC_REG_TLBPD1 0x406
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@@ -277,6 +285,13 @@ struct arc_fpu {
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***************************************************************
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* Build Configuration Registers, with encoded hardware config
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*/
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struct bcr_identity {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int chip_id:16, cpu_id:8, family:8;
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#else
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unsigned int family:8, cpu_id:8, chip_id:16;
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#endif
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};
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struct bcr_mmu_1_2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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@@ -296,6 +311,38 @@ struct bcr_mmu_3 {
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#endif
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};
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#define EXTN_SWAP_VALID 0x1
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#define EXTN_NORM_VALID 0x2
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#define EXTN_MINMAX_VALID 0x2
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#define EXTN_BARREL_VALID 0x2
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struct bcr_extn {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
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norm:2, swap:1;
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#else
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unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
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crc:1, pad:20;
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#endif
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};
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/* DSP Options Ref Manual */
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struct bcr_extn_mac_mul {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:16, type:8, ver:8;
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#else
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unsigned int ver:8, type:8, pad:16;
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#endif
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};
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struct bcr_extn_xymem {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
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#else
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unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
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#endif
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};
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struct bcr_cache {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
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@@ -304,6 +351,48 @@ struct bcr_cache {
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#endif
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};
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struct bcr_perip {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int start:8, pad2:8, sz:8, pad:8;
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#else
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unsigned int pad:8, sz:8, pad2:8, start:8;
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#endif
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};
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struct bcr_iccm {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int base:16, pad:5, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, pad:5, base:16;
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#endif
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};
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/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
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struct bcr_dccm_base {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int addr:24, ver:8;
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#else
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unsigned int ver:8, addr:24;
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#endif
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};
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/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
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struct bcr_dccm {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int res:21, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, res:21;
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#endif
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};
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/* Both SP and DP FPU BCRs have same format */
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struct bcr_fp {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int fast:1, ver:8;
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#else
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unsigned int ver:8, fast:1;
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#endif
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};
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/*
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*******************************************************************
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* Generic structures to hold build configuration used at runtime
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@@ -317,9 +406,22 @@ struct cpuinfo_arc_cache {
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unsigned int has_aliasing, sz, line_len, assoc, ver;
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};
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struct cpuinfo_arc_ccm {
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unsigned int base_addr, sz;
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};
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struct cpuinfo_arc {
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struct cpuinfo_arc_cache icache, dcache;
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struct cpuinfo_arc_mmu mmu;
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struct bcr_identity core;
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unsigned int timers;
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unsigned int vec_base;
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unsigned int uncached_base;
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struct cpuinfo_arc_ccm iccm, dccm;
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struct bcr_extn extn;
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struct bcr_extn_xymem extn_xymem;
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struct bcr_extn_mac_mul extn_mac_mul;
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struct bcr_fp fp, dpfp;
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};
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extern struct cpuinfo_arc cpuinfo_arc700[];
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56
arch/arc/include/asm/defines.h
Normal file
56
arch/arc/include/asm/defines.h
Normal file
@@ -0,0 +1,56 @@
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARC_ASM_DEFINES_H__
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#define __ARC_ASM_DEFINES_H__
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#if defined(CONFIG_ARC_MMU_V1)
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#define CONFIG_ARC_MMU_VER 1
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#elif defined(CONFIG_ARC_MMU_V2)
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#endif
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#ifdef CONFIG_ARC_HAS_LLSC
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#define __CONFIG_ARC_HAS_LLSC_VAL 1
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#else
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#define __CONFIG_ARC_HAS_LLSC_VAL 0
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#endif
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#ifdef CONFIG_ARC_HAS_SWAPE
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#define __CONFIG_ARC_HAS_SWAPE_VAL 1
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#else
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#define __CONFIG_ARC_HAS_SWAPE_VAL 0
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#endif
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#ifdef CONFIG_ARC_HAS_RTSC
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#define __CONFIG_ARC_HAS_RTSC_VAL 1
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#else
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#define __CONFIG_ARC_HAS_RTSC_VAL 0
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#endif
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#ifdef CONFIG_ARC_MMU_SASID
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#define __CONFIG_ARC_MMU_SASID_VAL 1
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#else
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#define __CONFIG_ARC_MMU_SASID_VAL 0
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#endif
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#ifdef CONFIG_ARC_HAS_ICACHE
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#define __CONFIG_ARC_HAS_ICACHE 1
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#else
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#define __CONFIG_ARC_HAS_ICACHE 0
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#endif
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#ifdef CONFIG_ARC_HAS_DCACHE
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#define __CONFIG_ARC_HAS_DCACHE 1
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#else
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#define __CONFIG_ARC_HAS_DCACHE 0
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#endif
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#endif /* __ARC_ASM_DEFINES_H__ */
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@@ -13,6 +13,20 @@
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#define COMMAND_LINE_SIZE 256
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/*
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* Data structure to map a ID to string
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* Used a lot for bootup reporting of hardware diversity
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*/
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struct id_to_str {
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int id;
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const char *str;
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};
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struct cpuinfo_data {
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struct id_to_str info;
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int up_range;
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};
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extern int root_mountflags, end_mem;
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extern int running_on_hw;
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