Merge tag 'drm-for-v4.13' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie: "This is the main pull request for the drm, I think I've got one later driver pull for mediatek SoC driver, I'm undecided on if it needs to go to you yet. Otherwise summary below: Core drm: - Atomic add driver private objects - Deprecate preclose hook in modern drivers - MST bandwidth tracking - Use kvmalloc in more places - Add mode_valid hook for crtc/encoder/bridge - Reduce sync_file construction time - Documentation updates - New DRM synchronisation object support New drivers: - pl111 - pl111 CLCD display controller Panel: - Innolux P079ZCA panel driver - Add NL12880B20-05, NL192108AC18-02D, P320HVN03 panels - panel-samsung-s6e3ha2: Add s6e3hf2 panel support i915: - SKL+ watermark fixes - G4x/G33 reset improvements - DP AUX backlight improvements - Buffer based GuC/host communication - New getparam for (sub)slice infomation - Cannonlake and Coffeelake initial patches - Execbuf optimisations radeon/amdgpu: - Lots of Vega10 bug fixes - Preliminary raven support - KIQ support for compute rings - MEC queue management rework - DCE6 Audio support - SR-IOV improvements - Better radeon/amdgpu selection support nouveau: - HDMI stereoscopic support - Display code rework for >= GM20x GPUs msm: - GEM rework for fine-grained locking - Per-process pagetable work - HDMI fixes for Snapdragon 820. vc4: - Remove 256MB CMA limit from vc4 - Add out-fence support - Add support for cygnus - Get/set tiling ioctls support - Add T-format tiling support for scanout zte: - add VGA support. etnaviv: - Thermal throttle support for newer GPUs - Restore userspace buffer cache performance - dma-buf sync fix stm: - add stm32f429 display support exynos: - Rework vblank handling - Fixup sw-trigger code sun4i: - V3s display engine support - HDMI support for older SoCs - Preliminary work on dual-pipeline SoCs. rcar-du: - VSP work imx-drm: - Remove counter load enable from PRE - Double read/write reduction flag support tegra: - Documentation for the host1x and drm driver. - Lots of staging ioctl fixes due to grate project work. omapdrm: - dma-buf fence support - TILER rotation fixes" * tag 'drm-for-v4.13' of git://people.freedesktop.org/~airlied/linux: (1270 commits) drm: Remove unused drm_file parameter to drm_syncobj_replace_fence() drm/amd/powerplay: fix bug fail to remove sysfs when rmmod amdgpu. amdgpu: Set cik/si_support to 1 by default if radeon isn't built drm/amdgpu/gfx9: fix driver reload with KIQ drm/amdgpu/gfx8: fix driver reload with KIQ drm/amdgpu: Don't call amd_powerplay_destroy() if we don't have powerplay drm/ttm: Fix use-after-free in ttm_bo_clean_mm drm/amd/amdgpu: move get memory type function from early init to sw init drm/amdgpu/cgs: always set reference clock in mode_info drm/amdgpu: fix vblank_time when displays are off drm/amd/powerplay: power value format change for Vega10 drm/amdgpu/gfx9: support the amdgpu.disable_cu option drm/amd/powerplay: change PPSMC_MSG_GetCurrPkgPwr for Vega10 drm/amdgpu: Make amdgpu_cs_parser_init static (v2) drm/amdgpu/cs: fix a typo in a comment drm/amdgpu: Fix the exported always on CU bitmap drm/amdgpu/gfx9: gfx_v9_0_enable_gfx_static_mg_power_gating() can be static drm/amdgpu/psp: upper_32_bits/lower_32_bits for address setup drm/amd/powerplay/cz: print message if smc message fails drm/amdgpu: fix typo in amdgpu_debugfs_test_ib_init ...
This commit is contained in:
Linus Torvalds
@@ -5,7 +5,7 @@ with HDMI output and the HVS (Hardware Video Scaler) for compositing
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display planes.
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Required properties for VC4:
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- compatible: Should be "brcm,bcm2835-vc4"
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- compatible: Should be "brcm,bcm2835-vc4" or "brcm,cygnus-vc4"
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Required properties for Pixel Valve:
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- compatible: Should be one of "brcm,bcm2835-pixelvalve0",
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@@ -54,11 +54,14 @@ Required properties for VEC:
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See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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Required properties for V3D:
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- compatible: Should be "brcm,bcm2835-v3d"
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- compatible: Should be "brcm,bcm2835-v3d" or "brcm,cygnus-v3d"
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- reg: Physical base address and length of the V3D's registers
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- interrupts: The interrupt number
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See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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Optional properties for V3D:
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- clocks: The clock the unit runs on
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Required properties for DSI:
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- compatible: Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1"
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- reg: Physical base address and length of the DSI block's registers
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@@ -8,12 +8,13 @@ Required properties:
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- compatible: value should be one of:
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"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
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- reg: physical base address and length of the DECON registers set.
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- interrupts: should contain a list of all DECON IP block interrupts in the
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order: VSYNC, LCD_SYSTEM. The interrupt specifier format
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depends on the interrupt controller used.
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- interrupt-names: should contain the interrupt names: "vsync", "lcd_sys"
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in the same order as they were listed in the interrupts
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property.
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- interrupt-names: should contain the interrupt names depending on mode of work:
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video mode: "vsync",
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command mode: "lcd_sys",
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command mode with software trigger: "lcd_sys", "te".
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- interrupts or interrupts-extended: list of interrupt specifiers corresponding
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to names privided in interrupt-names, as described in
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interrupt-controller/interrupts.txt
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- clocks: must include clock specifiers corresponding to entries in the
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clock-names property.
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- clock-names: list of clock names sorted in the same order as the clocks
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@@ -0,0 +1,8 @@
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AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel
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Required properties:
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- compatible: should be "auo,p320hvn03"
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- power-supply: as specified in the base binding
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@@ -0,0 +1,23 @@
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Innolux P079ZCA 7.85" 768x1024 TFT LCD panel
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Required properties:
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- compatible: should be "innolux,p079zca"
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- reg: DSI virtual channel of the peripheral
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- power-supply: phandle of the regulator that provides the supply voltage
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- enable-gpios: panel enable gpio
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Optional properties:
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- backlight: phandle of the backlight device attached to the panel
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Example:
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&mipi_dsi {
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panel {
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compatible = "innolux,p079zca";
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reg = <0>;
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power-supply = <...>;
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backlight = <&backlight>;
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enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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};
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@@ -0,0 +1,8 @@
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NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
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Required properties:
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- compatible: should be "nec,nl12880bc20-05"
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- power-supply: as specified in the base binding
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@@ -0,0 +1,8 @@
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NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
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Required properties:
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- compatible: should be "nlt,nl192108ac18-02d"
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- power-supply: as specified in the base binding
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@@ -1,7 +1,10 @@
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Samsung S6E3HA2 5.7" 1440x2560 AMOLED panel
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Samsung S6E3HF2 5.65" 1600x2560 AMOLED panel
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Required properties:
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- compatible: "samsung,s6e3ha2"
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- compatible: should be one of:
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"samsung,s6e3ha2",
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"samsung,s6e3hf2".
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- reg: the virtual channel number of a DSI peripheral
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- vdd3-supply: I/O voltage supply
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- vci-supply: voltage supply for analog circuits
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36
Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
Normal file
36
Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
Normal file
@@ -0,0 +1,36 @@
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* STMicroelectronics STM32 lcd-tft display controller
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- ltdc: lcd-tft display controller host
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must be a sub-node of st-display-subsystem
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Required properties:
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- compatible: "st,stm32-ltdc"
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- reg: Physical base address of the IP registers and length of memory mapped region.
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- clocks: A list of phandle + clock-specifier pairs, one for each
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entry in 'clock-names'.
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- clock-names: A list of clock names. For ltdc it should contain:
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- "lcd" for the clock feeding the output pixel clock & IP clock.
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- resets: reset to be used by the device (defined by use of RCC macro).
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Required nodes:
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- Video port for RGB output.
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Example:
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/ {
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...
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soc {
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...
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ltdc: display-controller@40016800 {
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compatible = "st,stm32-ltdc";
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reg = <0x40016800 0x200>;
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interrupts = <88>, <89>;
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resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
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clocks = <&rcc 1 CLK_LCD>;
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clock-names = "lcd";
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port {
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ltdc_out_rgb: endpoint {
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};
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};
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};
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};
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};
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@@ -4,6 +4,44 @@ Allwinner A10 Display Pipeline
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The Allwinner A10 Display pipeline is composed of several components
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that are going to be documented below:
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For the input port of all components up to the TCON in the display
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pipeline, if there are multiple components, the local endpoint IDs
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must correspond to the index of the upstream block. For example, if
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the remote endpoint is Frontend 1, then the local endpoint ID must
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be 1.
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Conversely, for the output ports of the same group, the remote endpoint
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ID must be the index of the local hardware block. If the local backend
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is backend 1, then the remote endpoint ID must be 1.
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HDMI Encoder
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------------
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The HDMI Encoder supports the HDMI video and audio outputs, and does
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CEC. It is one end of the pipeline.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun5i-a10s-hdmi
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- reg: base address and size of memory-mapped region
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the HDMI encoder
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* ahb: the HDMI interface clock
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* mod: the HDMI module clock
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* pll-0: the first video PLL
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* pll-1: the second video PLL
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- clock-names: the clock names mentioned above
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- dmas: phandles to the DMA channels used by the HDMI encoder
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* ddc-tx: The channel for DDC transmission
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* ddc-rx: The channel for DDC reception
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* audio-tx: The channel used for audio transmission
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- dma-names: the channel names mentioned above
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint. The second should be the
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output, usually to an HDMI connector.
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TV Encoder
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----------
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@@ -31,6 +69,7 @@ Required properties:
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* allwinner,sun6i-a31-tcon
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* allwinner,sun6i-a31s-tcon
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* allwinner,sun8i-a33-tcon
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* allwinner,sun8i-v3s-tcon
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- reg: base address and size of memory-mapped region
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the TCON. Three are needed:
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@@ -47,12 +86,15 @@ Required properties:
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint, the second one the output
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The output should have two endpoints. The first is the block
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connected to the TCON channel 0 (usually a panel or a bridge), the
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second the block connected to the TCON channel 1 (usually the TV
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encoder)
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The output may have multiple endpoints. The TCON has two channels,
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usually with the first channel being used for the panels interfaces
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(RGB, LVDS, etc.), and the second being used for the outputs that
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require another controller (TV Encoder, HDMI, etc.). The endpoints
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will take an extra property, allwinner,tcon-channel, to specify the
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channel the endpoint is associated to. If that property is not
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present, the endpoint number will be used as the channel number.
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On SoCs other than the A33, there is one more clock required:
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On SoCs other than the A33 and V3s, there is one more clock required:
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- 'tcon-ch1': The clock driving the TCON channel 1
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DRC
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@@ -138,6 +180,26 @@ Required properties:
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoints, the second one the outputs
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Display Engine 2.0 Mixer
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------------------------
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The DE2 mixer have many functionalities, currently only layer blending is
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supported.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun8i-v3s-de2-mixer
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- reg: base address and size of the memory-mapped region.
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- clocks: phandles to the clocks feeding the mixer
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* bus: the mixer interface clock
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* mod: the mixer module clock
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- clock-names: the clock names mentioned above
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- resets: phandles to the reset controllers driving the mixer
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoints, the second one the output
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Display Engine Pipeline
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-----------------------
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@@ -148,13 +210,15 @@ extra node.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun5i-a10s-display-engine
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* allwinner,sun5i-a13-display-engine
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* allwinner,sun6i-a31-display-engine
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* allwinner,sun6i-a31s-display-engine
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* allwinner,sun8i-a33-display-engine
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* allwinner,sun8i-v3s-display-engine
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- allwinner,pipelines: list of phandle to the display engine
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frontends available.
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frontends (DE 1.0) or mixers (DE 2.0) available.
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Example:
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@@ -173,6 +237,57 @@ panel: panel {
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};
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};
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connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&hdmi_out_con>;
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};
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};
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};
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hdmi: hdmi@01c16000 {
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compatible = "allwinner,sun5i-a10s-hdmi";
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reg = <0x01c16000 0x1000>;
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interrupts = <58>;
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clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
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<&ccu CLK_PLL_VIDEO0_2X>,
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<&ccu CLK_PLL_VIDEO1_2X>;
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clock-names = "ahb", "mod", "pll-0", "pll-1";
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dmas = <&dma SUN4I_DMA_NORMAL 16>,
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<&dma SUN4I_DMA_NORMAL 16>,
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<&dma SUN4I_DMA_DEDICATED 24>;
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dma-names = "ddc-tx", "ddc-rx", "audio-tx";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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hdmi_in_tcon0: endpoint {
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remote-endpoint = <&tcon0_out_hdmi>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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hdmi_out_con: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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};
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};
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tve0: tv-encoder@01c0a000 {
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compatible = "allwinner,sun4i-a10-tv-encoder";
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reg = <0x01c0a000 0x1000>;
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@@ -58,6 +58,18 @@ Required properties:
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integer cells. The first cell is the offset of SYSCTRL register used
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to control TV Encoder DAC power, and the second cell is the bit mask.
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* VGA output device
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Required properties:
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- compatible: should be "zte,zx296718-vga"
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- reg: Physical base address and length of the VGA device IO region
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- interrupts : VGA interrupt number to CPU
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- clocks: Phandle with clock-specifier pointing to VGA I2C clock.
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- clock-names: Must be "i2c_wclk".
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- zte,vga-power-control: the phandle to SYSCTRL block followed by two
|
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integer cells. The first cell is the offset of SYSCTRL register used
|
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to control VGA DAC power, and the second cell is the bit mask.
|
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Example:
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vou: vou@1440000 {
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@@ -81,6 +93,15 @@ vou: vou@1440000 {
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"main_wclk", "aux_wclk";
|
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};
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vga: vga@8000 {
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compatible = "zte,zx296718-vga";
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reg = <0x8000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topcrm VGA_I2C_WCLK>;
|
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clock-names = "i2c_wclk";
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zte,vga-power-control = <&sysctrl 0x170 0xe0>;
|
||||
};
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hdmi: hdmi@c000 {
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compatible = "zte,zx296718-hdmi";
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reg = <0xc000 0x4000>;
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@@ -227,6 +227,7 @@ nexbox Nexbox
|
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newhaven Newhaven Display International
|
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ni National Instruments
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nintendo Nintendo
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nlt NLT Technologies, Ltd.
|
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nokia Nokia
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nordic Nordic Semiconductor
|
||||
nuvoton Nuvoton Technology Corporation
|
||||
|
||||
Reference in New Issue
Block a user