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MIPS: lantiq: adds code for booting GPHY

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The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to
boot them up.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4522
This commit is contained in:
John Crispin
2012-11-09 13:43:30 +01:00
parent f2bbe41c50
commit af14a456c5
2 changed files with 39 additions and 0 deletions
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3
arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -82,6 +82,9 @@ extern __iomem void *ltq_cgu_membase;
#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
/* allow booting xrx200 phys */
int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
/* request a non-gpio and set the PIO config */
#define PMU_PPE BIT(13)
extern void ltq_pmu_enable(unsigned int module);