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powerpc/8xx: Declare SPRG2 as a SCRATCH register

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Since commit 469d62be92, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
LEROY Christophe
2014-08-29 11:14:37 +02:00
committed by Scott Wood
parent c822e73731
commit ae466bde19
2 changed files with 7 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/powerpc/include/asm/reg.h
View File

@@ -950,7 +950,7 @@
* 32-bit 8xx: * 32-bit 8xx:
* - SPRG0 scratch for exception vectors * - SPRG0 scratch for exception vectors
* - SPRG1 scratch for exception vectors * - SPRG1 scratch for exception vectors
* - SPRG2 apparently unused but initialized * - SPRG2 scratch for exception vectors
* *
*/ */
#ifdef CONFIG_PPC64 #ifdef CONFIG_PPC64
@@ -1060,6 +1060,7 @@
#ifdef CONFIG_8xx #ifdef CONFIG_8xx
#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
#endif #endif

10
arch/powerpc/kernel/head_8xx.S
View File

@@ -301,7 +301,7 @@ InstructionTLBMiss:
stw r11, 4(r0) stw r11, 4(r0)
#else #else
mtspr SPRN_DAR, r10 mtspr SPRN_DAR, r10
mtspr SPRN_SPRG2, r11 mtspr SPRN_SPRG_SCRATCH2, r11
#endif #endif
mfspr r10, SPRN_SRR0 /* Get effective address of fault */ mfspr r10, SPRN_SRR0 /* Get effective address of fault */
#ifdef CONFIG_8xx_CPU15 #ifdef CONFIG_8xx_CPU15
@@ -363,7 +363,7 @@ InstructionTLBMiss:
mfspr r10, SPRN_DAR mfspr r10, SPRN_DAR
mtcr r10 mtcr r10
mtspr SPRN_DAR, r11 /* Tag DAR */ mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r11, SPRN_SPRG2 mfspr r11, SPRN_SPRG_SCRATCH2
#else #else
lwz r11, 0(r0) lwz r11, 0(r0)
mtcr r11 mtcr r11
@@ -386,7 +386,7 @@ InstructionTLBMiss:
mtcr r10 mtcr r10
li r11, 0x00f0 li r11, 0x00f0
mtspr SPRN_DAR, r11 /* Tag DAR */ mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r11, SPRN_SPRG2 mfspr r11, SPRN_SPRG_SCRATCH2
#else #else
lwz r11, 0(r0) lwz r11, 0(r0)
mtcr r11 mtcr r11
@@ -409,7 +409,7 @@ DataStoreTLBMiss:
stw r11, 4(r0) stw r11, 4(r0)
#else #else
mtspr SPRN_DAR, r10 mtspr SPRN_DAR, r10
mtspr SPRN_SPRG2, r11 mtspr SPRN_SPRG_SCRATCH2, r11
#endif #endif
mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
@@ -487,7 +487,7 @@ DataStoreTLBMiss:
mfspr r10, SPRN_DAR mfspr r10, SPRN_DAR
mtcr r10 mtcr r10
mtspr SPRN_DAR, r11 /* Tag DAR */ mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r11, SPRN_SPRG2 mfspr r11, SPRN_SPRG_SCRATCH2
#else #else
mtspr SPRN_DAR, r11 /* Tag DAR */ mtspr SPRN_DAR, r11 /* Tag DAR */
lwz r11, 0(r0) lwz r11, 0(r0)