Merge remote-tracking branches 'spi/topic/a3700', 'spi/topic/atmel', 'spi/topic/bcm53xx', 'spi/topic/davinci' and 'spi/topic/dw' into spi-next
Este cometimento está contido em:
Mark Brown
@@ -27,6 +27,8 @@
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#define DRIVER_NAME "armada_3700_spi"
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#define A3700_SPI_MAX_SPEED_HZ 100000000
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#define A3700_SPI_MAX_PRESCALE 30
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#define A3700_SPI_TIMEOUT 10
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/* SPI Register Offest */
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@@ -184,12 +186,15 @@ static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
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return 0;
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}
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static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi)
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static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable)
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{
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u32 val;
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
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val |= A3700_SPI_FIFO_MODE;
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if (enable)
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val |= A3700_SPI_FIFO_MODE;
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else
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val &= ~A3700_SPI_FIFO_MODE;
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
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}
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@@ -297,7 +302,7 @@ static int a3700_spi_init(struct a3700_spi *a3700_spi)
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a3700_spi_deactivate_cs(a3700_spi, i);
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/* Enable FIFO mode */
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a3700_spi_fifo_mode_set(a3700_spi);
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a3700_spi_fifo_mode_set(a3700_spi, true);
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/* Set SPI mode */
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a3700_spi_mode_set(a3700_spi, master->mode_bits);
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@@ -416,15 +421,20 @@ static void a3700_spi_transfer_setup(struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct a3700_spi *a3700_spi;
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unsigned int byte_len;
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a3700_spi = spi_master_get_devdata(spi->master);
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a3700_spi_clock_set(a3700_spi, xfer->speed_hz);
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byte_len = xfer->bits_per_word >> 3;
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/* Use 4 bytes long transfers. Each transfer method has its way to deal
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* with the remaining bytes for non 4-bytes aligned transfers.
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*/
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a3700_spi_bytelen_set(a3700_spi, 4);
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a3700_spi_fifo_thres_set(a3700_spi, byte_len);
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/* Initialize the working buffers */
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a3700_spi->tx_buf = xfer->tx_buf;
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a3700_spi->rx_buf = xfer->rx_buf;
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a3700_spi->buf_len = xfer->len;
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}
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static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
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@@ -491,7 +501,7 @@ static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
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u32 val;
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while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
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val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf);
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val = *(u32 *)a3700_spi->tx_buf;
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spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
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a3700_spi->buf_len -= 4;
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a3700_spi->tx_buf += 4;
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@@ -514,9 +524,8 @@ static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
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while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
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val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
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if (a3700_spi->buf_len >= 4) {
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u32 data = le32_to_cpu(val);
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memcpy(a3700_spi->rx_buf, &data, 4);
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memcpy(a3700_spi->rx_buf, &val, 4);
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a3700_spi->buf_len -= 4;
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a3700_spi->rx_buf += 4;
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@@ -579,27 +588,26 @@ static int a3700_spi_prepare_message(struct spi_master *master,
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if (ret)
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return ret;
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a3700_spi_bytelen_set(a3700_spi, 4);
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a3700_spi_mode_set(a3700_spi, spi->mode);
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return 0;
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}
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static int a3700_spi_transfer_one(struct spi_master *master,
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static int a3700_spi_transfer_one_fifo(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
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int ret = 0, timeout = A3700_SPI_TIMEOUT;
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unsigned int nbits = 0;
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unsigned int nbits = 0, byte_len;
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u32 val;
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a3700_spi_transfer_setup(spi, xfer);
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/* Make sure we use FIFO mode */
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a3700_spi_fifo_mode_set(a3700_spi, true);
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a3700_spi->tx_buf = xfer->tx_buf;
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a3700_spi->rx_buf = xfer->rx_buf;
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a3700_spi->buf_len = xfer->len;
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/* Configure FIFO thresholds */
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byte_len = xfer->bits_per_word >> 3;
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a3700_spi_fifo_thres_set(a3700_spi, byte_len);
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if (xfer->tx_buf)
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nbits = xfer->tx_nbits;
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@@ -615,6 +623,11 @@ static int a3700_spi_transfer_one(struct spi_master *master,
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a3700_spi_header_set(a3700_spi);
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if (xfer->rx_buf) {
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/* Clear WFIFO, since it's last 2 bytes are shifted out during
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* a read operation
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*/
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spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
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/* Set read data length */
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spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
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a3700_spi->buf_len);
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@@ -729,6 +742,63 @@ out:
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return ret;
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}
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static int a3700_spi_transfer_one_full_duplex(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
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u32 val;
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/* Disable FIFO mode */
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a3700_spi_fifo_mode_set(a3700_spi, false);
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while (a3700_spi->buf_len) {
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/* When we have less than 4 bytes to transfer, switch to 1 byte
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* mode. This is reset after each transfer
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*/
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if (a3700_spi->buf_len < 4)
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a3700_spi_bytelen_set(a3700_spi, 1);
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if (a3700_spi->byte_len == 1)
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val = *a3700_spi->tx_buf;
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else
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val = *(u32 *)a3700_spi->tx_buf;
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spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
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/* Wait for all the data to be shifted in / out */
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while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) &
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A3700_SPI_XFER_DONE))
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cpu_relax();
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val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
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memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len);
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a3700_spi->buf_len -= a3700_spi->byte_len;
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a3700_spi->tx_buf += a3700_spi->byte_len;
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a3700_spi->rx_buf += a3700_spi->byte_len;
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}
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spi_finalize_current_transfer(master);
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return 0;
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}
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static int a3700_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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a3700_spi_transfer_setup(spi, xfer);
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if (xfer->tx_buf && xfer->rx_buf)
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return a3700_spi_transfer_one_full_duplex(master, spi, xfer);
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return a3700_spi_transfer_one_fifo(master, spi, xfer);
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}
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static int a3700_spi_unprepare_message(struct spi_master *master,
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struct spi_message *message)
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{
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@@ -778,7 +848,6 @@ static int a3700_spi_probe(struct platform_device *pdev)
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master->transfer_one = a3700_spi_transfer_one;
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master->unprepare_message = a3700_spi_unprepare_message;
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master->set_cs = a3700_spi_set_cs;
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master->flags = SPI_MASTER_HALF_DUPLEX;
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master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL |
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SPI_RX_QUAD | SPI_TX_QUAD);
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@@ -818,6 +887,11 @@ static int a3700_spi_probe(struct platform_device *pdev)
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goto error;
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}
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master->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ,
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clk_get_rate(spi->clk));
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master->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk),
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A3700_SPI_MAX_PRESCALE);
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ret = a3700_spi_init(spi);
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if (ret)
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goto error_clk;
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