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drm/amdgpu/gfx9: derive tile pipes from golden settings

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rather than hardcoding it.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2017-05-02 16:15:06 -04:00
parent f47b77b4e4
commit ad7d0ff3e7
1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@@ -771,7 +771,6 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_VEGA10: case CHIP_VEGA10:
adev->gfx.config.max_shader_engines = 4; adev->gfx.config.max_shader_engines = 4;
adev->gfx.config.max_tile_pipes = 8; //??
adev->gfx.config.max_cu_per_sh = 16; adev->gfx.config.max_cu_per_sh = 16;
adev->gfx.config.max_sh_per_se = 1; adev->gfx.config.max_sh_per_se = 1;
adev->gfx.config.max_backends_per_se = 4; adev->gfx.config.max_backends_per_se = 4;
@@ -800,6 +799,10 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.gb_addr_config, adev->gfx.config.gb_addr_config,
GB_ADDR_CONFIG, GB_ADDR_CONFIG,
NUM_PIPES); NUM_PIPES);
adev->gfx.config.max_tile_pipes =
adev->gfx.config.gb_addr_config_fields.num_pipes;
adev->gfx.config.gb_addr_config_fields.num_banks = 1 << adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
REG_GET_FIELD( REG_GET_FIELD(
adev->gfx.config.gb_addr_config, adev->gfx.config.gb_addr_config,