KVM: MIPS/T&E: Expose read-only CP0_IntCtl register
Expose the CP0_IntCtl register through the KVM register access API, which is a required register since MIPS32r2. It is currently read-only since the VS field isn't implemented due to lack of Config3.VInt or Config3.VEIC. It is implemented in trap_emul.c so that a VZ implementation can allow writes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
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@@ -2073,6 +2073,7 @@ registers, find a list below:
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MIPS | KVM_REG_MIPS_CP0_ENTRYHI | 64
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MIPS | KVM_REG_MIPS_CP0_COMPARE | 32
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MIPS | KVM_REG_MIPS_CP0_STATUS | 32
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MIPS | KVM_REG_MIPS_CP0_INTCTL | 32
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MIPS | KVM_REG_MIPS_CP0_CAUSE | 32
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MIPS | KVM_REG_MIPS_CP0_EPC | 64
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MIPS | KVM_REG_MIPS_CP0_PRID | 32
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