xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'master' into sh/smp

Browse Source 
Conflicts:
	arch/sh/mm/cache-sh4.c
This commit is contained in:
Paul Mundt
2009-09-01 13:54:14 +09:00
parent e76a0136a3 ce3f7cb96e
commit ac6a0cf671
414 changed files with 15153 additions and 2589 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/sh/include/asm/Kbuild
View File

@@ -1,6 +1,6 @@
include include/asm-generic/Kbuild.asm
header-y += cpu-features.h
header-y += cachectl.h cpu-features.h
unifdef-y += unistd_32.h
unifdef-y += unistd_64.h

31
arch/sh/include/asm/bug.h
View File

@@ -2,6 +2,7 @@
#define __ASM_SH_BUG_H
#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */
#define BUGFLAG_UNWINDER (1 << 1)
#ifdef CONFIG_GENERIC_BUG
#define HAVE_ARCH_BUG
@@ -72,6 +73,36 @@ do { \
unlikely(__ret_warn_on); \
})
#define UNWINDER_BUG() \
do { \
__asm__ __volatile__ ( \
"1:\t.short %O0\n" \
_EMIT_BUG_ENTRY \
: \
: "n" (TRAPA_BUG_OPCODE), \
"i" (__FILE__), \
"i" (__LINE__), \
"i" (BUGFLAG_UNWINDER), \
"i" (sizeof(struct bug_entry))); \
} while (0)
#define UNWINDER_BUG_ON(x) ({ \
int __ret_unwinder_on = !!(x); \
if (__builtin_constant_p(__ret_unwinder_on)) { \
if (__ret_unwinder_on) \
UNWINDER_BUG(); \
} else { \
if (unlikely(__ret_unwinder_on)) \
UNWINDER_BUG(); \
} \
unlikely(__ret_unwinder_on); \
})
#else
#define UNWINDER_BUG BUG
#define UNWINDER_BUG_ON BUG_ON
#endif /* CONFIG_GENERIC_BUG */
#include <asm-generic/bug.h>

19
arch/sh/include/asm/cachectl.h Normal file
View File

@@ -0,0 +1,19 @@
#ifndef _SH_CACHECTL_H
#define _SH_CACHECTL_H
/* Definitions for the cacheflush system call. */
#define CACHEFLUSH_D_INVAL 0x1 /* invalidate (without write back) */
#define CACHEFLUSH_D_WB 0x2 /* write back (without invalidate) */
#define CACHEFLUSH_D_PURGE 0x3 /* writeback and invalidate */
#define CACHEFLUSH_I 0x4
/*
* Options for cacheflush system call
*/
#define ICACHE CACHEFLUSH_I /* flush instruction cache */
#define DCACHE CACHEFLUSH_D_PURGE /* writeback and flush data cache */
#define BCACHE (ICACHE|DCACHE) /* flush both caches */
#endif /* _SH_CACHECTL_H */

16
arch/sh/include/asm/device.h
View File

@@ -3,7 +3,9 @@
*
* This file is released under the GPLv2
*/
#include <asm-generic/device.h>
struct dev_archdata {
};
struct platform_device;
/* allocate contiguous memory chunk and fill in struct resource */
@@ -12,3 +14,15 @@ int platform_resource_setup_memory(struct platform_device *pdev,
void plat_early_device_setup(void);
#define PDEV_ARCHDATA_FLAG_INIT 0
#define PDEV_ARCHDATA_FLAG_IDLE 1
#define PDEV_ARCHDATA_FLAG_SUSP 2
struct pdev_archdata {
int hwblk_id;
#ifdef CONFIG_PM_RUNTIME
unsigned long flags;
struct list_head entry;
struct mutex mutex;
#endif
};

30
arch/sh/include/asm/dwarf.h
View File

@@ -200,7 +200,7 @@
*/
static __always_inline unsigned long dwarf_read_arch_reg(unsigned int reg)
{
unsigned long value;
unsigned long value = 0;
switch (reg) {
case 14:
@@ -265,10 +265,7 @@ struct dwarf_frame {
unsigned long pc;
struct dwarf_reg *regs;
unsigned int num_regs; /* how many regs are allocated? */
unsigned int depth; /* what level are we in the callstack? */
struct list_head reg_list;
unsigned long cfa;
@@ -292,20 +289,15 @@ struct dwarf_frame {
* @flags: Describes how to calculate the value of this register
*/
struct dwarf_reg {
struct list_head link;
unsigned int number;
unsigned long addr;
unsigned long flags;
#define DWARF_REG_OFFSET (1 << 0)
};
/**
* dwarf_stack - a DWARF stack contains a collection of DWARF frames
* @depth: the number of frames in the stack
* @level: an array of DWARF frames, indexed by stack level
*
*/
struct dwarf_stack {
unsigned int depth;
struct dwarf_frame **level;
#define DWARF_VAL_OFFSET (1 << 1)
#define DWARF_UNDEFINED (1 << 2)
};
/*
@@ -370,17 +362,16 @@ static inline unsigned int DW_CFA_operand(unsigned long insn)
#define DW_EXT_HI 0xffffffff
#define DW_EXT_DWARF64 DW_EXT_HI
extern void dwarf_unwinder_init(void);
extern struct dwarf_frame *dwarf_unwind_stack(unsigned long,
struct dwarf_frame *);
#endif /* __ASSEMBLY__ */
#endif /* !__ASSEMBLY__ */
#define CFI_STARTPROC .cfi_startproc
#define CFI_ENDPROC .cfi_endproc
#define CFI_DEF_CFA .cfi_def_cfa
#define CFI_REGISTER .cfi_register
#define CFI_REL_OFFSET .cfi_rel_offset
#define CFI_UNDEFINED .cfi_undefined
#else
@@ -394,6 +385,7 @@ extern struct dwarf_frame *dwarf_unwind_stack(unsigned long,
#define CFI_DEF_CFA CFI_IGNORE
#define CFI_REGISTER CFI_IGNORE
#define CFI_REL_OFFSET CFI_IGNORE
#define CFI_UNDEFINED CFI_IGNORE
#ifndef __ASSEMBLY__
static inline void dwarf_unwinder_init(void)

2
arch/sh/include/asm/entry-macros.S
View File

@@ -7,7 +7,7 @@
.endm
.macro sti
mov #0xf0, r11
mov #0xfffffff0, r11
extu.b r11, r11
not r11, r11
stc sr, r10

1
arch/sh/include/asm/ftrace.h
View File

@@ -4,6 +4,7 @@
#ifdef CONFIG_FUNCTION_TRACER
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
#define FTRACE_SYSCALL_MAX NR_syscalls
#ifndef __ASSEMBLY__
extern void mcount(void);

4
arch/sh/include/asm/hwblk.h
View File

@@ -5,7 +5,9 @@
#include <asm/io.h>
#define HWBLK_CNT_USAGE 0
#define HWBLK_CNT_NR 1
#define HWBLK_CNT_IDLE 1
#define HWBLK_CNT_DEVICES 2
#define HWBLK_CNT_NR 3
#define HWBLK_AREA_FLAG_PARENT (1 << 0) /* valid parent */

16
arch/sh/include/asm/io.h
View File

@@ -92,8 +92,12 @@
static inline void ctrl_delay(void)
{
#ifdef P2SEG
#ifdef CONFIG_CPU_SH4
__raw_readw(CCN_PVR);
#elif defined(P2SEG)
__raw_readw(P2SEG);
#else
#error "Need a dummy address for delay"
#endif
}
@@ -146,6 +150,7 @@ __BUILD_MEMORY_STRING(q, u64)
#define readl_relaxed(a) readl(a)
#define readq_relaxed(a) readq(a)
#ifndef CONFIG_GENERIC_IOMAP
/* Simple MMIO */
#define ioread8(a) __raw_readb(a)
#define ioread16(a) __raw_readw(a)
@@ -166,6 +171,15 @@ __BUILD_MEMORY_STRING(q, u64)
#define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c))
#define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c))
#define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c))
#endif
#define mmio_insb(p,d,c) __raw_readsb(p,d,c)
#define mmio_insw(p,d,c) __raw_readsw(p,d,c)
#define mmio_insl(p,d,c) __raw_readsl(p,d,c)
#define mmio_outsb(p,s,c) __raw_writesb(p,s,c)
#define mmio_outsw(p,s,c) __raw_writesw(p,s,c)
#define mmio_outsl(p,s,c) __raw_writesl(p,s,c)
/* synco on SH-4A, otherwise a nop */
#define mmiowb() wmb()

8
arch/sh/include/asm/pgtable_32.h
View File

@@ -87,6 +87,14 @@
#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
#ifndef CONFIG_X2TLB
/* copy the ptea attributes */
static inline unsigned long copy_ptea_attributes(unsigned long x)
{
return ((x >> 28) & 0xe) | (x & 0x1);
}
#endif
/* Mask which drops unused bits from the PTEL value */
#if defined(CONFIG_CPU_SH3)
#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \

2
arch/sh/include/asm/processor.h
View File

@@ -32,7 +32,7 @@ enum cpu_type {
/* SH-4A types */
CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
CPU_SH7723, CPU_SH7724, CPU_SHX3,
CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
/* SH4AL-DSP types */
CPU_SH7343, CPU_SH7722, CPU_SH7366,

5
arch/sh/include/asm/system.h
View File

@@ -169,6 +169,11 @@ BUILD_TRAP_HANDLER(breakpoint);
BUILD_TRAP_HANDLER(singlestep);
BUILD_TRAP_HANDLER(fpu_error);
BUILD_TRAP_HANDLER(fpu_state_restore);
BUILD_TRAP_HANDLER(unwinder);
#ifdef CONFIG_BUG
extern void handle_BUG(struct pt_regs *);
#endif
#define arch_align_stack(x) (x)

28
arch/sh/include/asm/system_32.h
View File

@@ -14,12 +14,12 @@ do { \
(u32 *)&tsk->thread.dsp_status; \
__asm__ __volatile__ ( \
".balign 4\n\t" \
"movs.l @r2+, a0\n\t" \
"movs.l @r2+, a1\n\t" \
"movs.l @r2+, a0g\n\t" \
"movs.l @r2+, a1g\n\t" \
"movs.l @r2+, m0\n\t" \
"movs.l @r2+, m1\n\t" \
"movs.l @r2+, a0\n\t" \
"movs.l @r2+, x0\n\t" \
"movs.l @r2+, x1\n\t" \
"movs.l @r2+, y0\n\t" \
@@ -39,20 +39,20 @@ do { \
\
__asm__ __volatile__ ( \
".balign 4\n\t" \
"stc.l mod, @-r2\n\t" \
"stc.l mod, @-r2\n\t" \
"stc.l re, @-r2\n\t" \
"stc.l rs, @-r2\n\t" \
"sts.l dsr, @-r2\n\t" \
"sts.l y1, @-r2\n\t" \
"sts.l y0, @-r2\n\t" \
"sts.l x1, @-r2\n\t" \
"sts.l x0, @-r2\n\t" \
"sts.l a0, @-r2\n\t" \
".word 0xf653 ! movs.l a1, @-r2\n\t" \
".word 0xf6f3 ! movs.l a0g, @-r2\n\t" \
".word 0xf6d3 ! movs.l a1g, @-r2\n\t" \
".word 0xf6c3 ! movs.l m0, @-r2\n\t" \
".word 0xf6e3 ! movs.l m1, @-r2\n\t" \
"sts.l dsr, @-r2\n\t" \
"movs.l y1, @-r2\n\t" \
"movs.l y0, @-r2\n\t" \
"movs.l x1, @-r2\n\t" \
"movs.l x0, @-r2\n\t" \
"movs.l m1, @-r2\n\t" \
"movs.l m0, @-r2\n\t" \
"movs.l a1g, @-r2\n\t" \
"movs.l a0g, @-r2\n\t" \
"movs.l a1, @-r2\n\t" \
"movs.l a0, @-r2\n\t" \
: : "r" (__ts2)); \
} while (0)
@@ -214,7 +214,7 @@ static inline reg_size_t register_align(void *val)
}
int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
struct mem_access *ma);
struct mem_access *ma, int);
asmlinkage void do_address_error(struct pt_regs *regs,
unsigned long writeaccess,

2
arch/sh/include/asm/unistd_32.h
View File

@@ -132,7 +132,7 @@
#define __NR_clone 120
#define __NR_setdomainname 121
#define __NR_uname 122
#define __NR_modify_ldt 123
#define __NR_cacheflush 123
#define __NR_adjtimex 124
#define __NR_mprotect 125
#define __NR_sigprocmask 126

2
arch/sh/include/asm/unistd_64.h
View File

@@ -137,7 +137,7 @@
#define __NR_clone 120
#define __NR_setdomainname 121
#define __NR_uname 122
#define __NR_modify_ldt 123
#define __NR_cacheflush 123
#define __NR_adjtimex 124
#define __NR_mprotect 125
#define __NR_sigprocmask 126

6
arch/sh/include/asm/unwinder.h
View File

@@ -22,4 +22,10 @@ extern void stack_reader_dump(struct task_struct *, struct pt_regs *,
unsigned long *, const struct stacktrace_ops *,
void *);
/*
* Used by fault handling code to signal to the unwinder code that it
* should switch to a different unwinder.
*/
extern int unwinder_faulted;
#endif /* _LINUX_UNWINDER_H */

21
arch/sh/include/asm/watchdog.h
View File

@@ -13,10 +13,18 @@
#ifdef __KERNEL__
#include <linux/types.h>
#include <cpu/watchdog.h>
#include <asm/io.h>
#include <linux/io.h>
/*
#define WTCNT_HIGH 0x5a
#define WTCSR_HIGH 0xa5
#define WTCSR_CKS2 0x04
#define WTCSR_CKS1 0x02
#define WTCSR_CKS0 0x01
#include <cpu/watchdog.h>
/*
* See cpu-sh2/watchdog.h for explanation of this stupidity..
*/
#ifndef WTCNT_R
@@ -27,13 +35,6 @@
# define WTCSR_R WTCSR
#endif
#define WTCNT_HIGH 0x5a
#define WTCSR_HIGH 0xa5
#define WTCSR_CKS2 0x04
#define WTCSR_CKS1 0x02
#define WTCSR_CKS0 0x01
/*
* CKS0-2 supports a number of clock division ratios. At the time the watchdog
* is enabled, it defaults to a 41 usec overflow period .. we overload this to

4
arch/sh/include/cpu-sh4/cpu/freq.h
View File

@@ -22,6 +22,10 @@
#define MSTPCR0 0xa4150030
#define MSTPCR1 0xa4150034
#define MSTPCR2 0xa4150038
#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
#define FRQCR 0xffc80000
#define OSCCR 0xffc80018
#define PLLCR 0xffc80024
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
#define FRQCR 0xffc80000

243
arch/sh/include/cpu-sh4/cpu/sh7757.h Normal file
View File

@@ -0,0 +1,243 @@
#ifndef __ASM_SH7757_H__
#define __ASM_SH7757_H__
enum {
/* PTA */
GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
/* PTB */
GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
/* PTC */
GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
/* PTD */
GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
/* PTE */
GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
/* PTF */
GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
/* PTG */
GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4,
GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
/* PTH */
GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
/* PTI */
GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4,
GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0,
/* PTJ */
GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4,
GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
/* PTK */
GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
/* PTL */
GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
/* PTM */
GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
/* PTN */
GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
/* PTO */
GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4,
GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0,
/* PTP */
GPIO_PTP6, GPIO_PTP5, GPIO_PTP4,
GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
/* PTQ */
GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
/* PTR */
GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
/* PTS */
GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
/* PTT */
GPIO_PTT5, GPIO_PTT4,
GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
/* PTU */
GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
/* PTV */
GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
/* PTW */
GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
/* PTX */
GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
/* PTY */
GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
/* PTZ */
GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
/* PTA (mobule: LBSC, CPG, LPC) */
GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY,
GPIO_FN_MD10, GPIO_FN_MD9, GPIO_FN_MD8,
GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
/* PTB (mobule: LBSC, EtherC, SIM, LPC) */
GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO,
GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO,
GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
GPIO_FN_WPSZ1, GPIO_FN_WPSZ0, GPIO_FN_FWID, GPIO_FN_FLSHSZ,
GPIO_FN_LPC_SPIEN, GPIO_FN_BASEL,
/* PTC (mobule: SD) */
GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0,
/* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4,
GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
GPIO_FN_MD6, GPIO_FN_MD5, GPIO_FN_MD3, GPIO_FN_MD2,
GPIO_FN_MD1, GPIO_FN_MD0, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
/* PTE (mobule: EtherC) */
GPIO_FN_ET0_CRS_DV, GPIO_FN_ET0_TXD1,
GPIO_FN_ET0_TXD0, GPIO_FN_ET0_TX_EN,
GPIO_FN_ET0_REF_CLK, GPIO_FN_ET0_RXD1,
GPIO_FN_ET0_RXD0, GPIO_FN_ET0_RX_ER,
/* PTF (mobule: EtherC) */
GPIO_FN_ET1_CRS_DV, GPIO_FN_ET1_TXD1,
GPIO_FN_ET1_TXD0, GPIO_FN_ET1_TX_EN,
GPIO_FN_ET1_REF_CLK, GPIO_FN_ET1_RXD1,
GPIO_FN_ET1_RXD0, GPIO_FN_ET1_RX_ER,
/* PTG (mobule: SYSTEM, PWMX, LPC) */
GPIO_FN_STATUS0, GPIO_FN_STATUS1,
GPIO_FN_PWX0, GPIO_FN_PWX1, GPIO_FN_PWX2, GPIO_FN_PWX3,
GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD, GPIO_FN_LDRQ,
/* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
GPIO_FN_TCLK, GPIO_FN_RXD4, GPIO_FN_TXD4,
GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO,
GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB,
GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1,
GPIO_FN_SP0_SS1,
/* PTI (mobule: INTC) */
GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12,
GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8,
/* PTJ (mobule: SCIF234, SERMUX) */
GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_RXD2, GPIO_FN_TXD2,
GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD,
GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS,
/* PTK (mobule: SERMUX) */
GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD,
GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS,
GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR,
GPIO_FN_COM2_DCD, GPIO_FN_COM2_RI,
/* PTL (mobule: SERMUX) */
GPIO_FN_RAC_TXD, GPIO_FN_RAC_RXD,
GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS,
GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR,
GPIO_FN_RAC_DCD, GPIO_FN_RAC_RI,
/* PTM (mobule: IIC, LPC) */
GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7,
GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_FMS1,
/* PTN (mobule: SCIF234, EVC) */
GPIO_FN_SCK2, GPIO_FN_RTS4, GPIO_FN_RTS3, GPIO_FN_RTS2,
GPIO_FN_CTS4, GPIO_FN_CTS3, GPIO_FN_CTS2,
GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4,
GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0,
/* PTO (mobule: SGPIO) */
GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD,
GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO,
GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD,
GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO,
/* PTP (mobule: JMC, SCIF234) */
GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
GPIO_FN_JMCRST, GPIO_FN_SCK4, GPIO_FN_SCK3,
/* PTQ (mobule: LPC) */
GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0,
GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK,
/* PTR (mobule: GRA, IIC) */
GPIO_FN_DDC3, GPIO_FN_DDC2,
GPIO_FN_SDA8, GPIO_FN_SCL8, GPIO_FN_SDA2, GPIO_FN_SCL2,
GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0,
/* PTS (mobule: GRA, IIC) */
GPIO_FN_DDC1, GPIO_FN_DDC0,
GPIO_FN_SDA9, GPIO_FN_SCL9, GPIO_FN_SDA5, GPIO_FN_SCL5,
GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3,
/* PTT (mobule: SYSTEM, PWMX) */
GPIO_FN_AUDSYNC, GPIO_FN_AUDCK,
GPIO_FN_AUDATA3, GPIO_FN_AUDATA2,
GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
GPIO_FN_PWX7, GPIO_FN_PWX6, GPIO_FN_PWX5, GPIO_FN_PWX4,
/* PTU (mobule: LBSC, DMAC) */
GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CS0,
GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_A25, GPIO_FN_A24,
GPIO_FN_DREQ0, GPIO_FN_DACK0,
/* PTV (mobule: LBSC, DMAC) */
GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
GPIO_FN_TEND0, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_TEND1,
/* PTW (mobule: LBSC) */
GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
/* PTX (mobule: LBSC) */
GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
/* PTY (mobule: LBSC) */
GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
};
#endif /* __ASM_SH7757_H__ */

2
arch/sh/include/mach-common/mach/sh7785lcr.h
View File

@@ -35,6 +35,8 @@
#define PCA9564_ADDR 0x06000000 /* I2C */
#define PCA9564_SIZE 0x00000100
#define PCA9564_PROTO_32BIT_ADDR 0x14000000
#define SM107_MEM_ADDR 0x10000000
#define SM107_MEM_SIZE 0x00e00000
#define SM107_REG_ADDR 0x13e00000

6
arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt
View File

@@ -16,6 +16,12 @@ LIST "--------------------------------"
LIST "disable watchdog"
EW 0xa4520004, 0xa507
LIST "invalidate instruction cache"
ED 0xff00001c, 0x00000800
LIST "invalidate TLBs"
ED 0xff000010, 0x00000004
LIST "select mode for cs5 + cs6"
ED 0xff800020, 0xa5a50001
ED 0xfec10000, 0x0000001b

13
arch/sh/include/mach-kfr2r09/mach/romimage.h
View File

@@ -73,3 +73,16 @@
.endm
#include "partner-jet-setup.txt"
/* execute icbi after enabling cache */
mov.l 1f, r0
icbi @r0
/* jump to cached area */
mova 2f, r0
jmp @r0
nop
.align 2
1: .long 0xa8000000
2: