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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Browse Source 
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68k,m68knommu: merge header files

Resolve trivial conflict in arch/m68knommu/include/asm/Kbuild
This commit is contained in:
Linus Torvalds
2009-01-26 10:33:01 -08:00
parent 9f4863b7dc 49148020bc
commit ac3d266bf1
355 changed files with 266 additions and 101 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/m68k/include/asm/Kbuild Normal file
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include include/asm-generic/Kbuild.asm
header-y += cachectl.h

1266
arch/m68k/include/asm/MC68328.h Normal file
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arch/m68k/include/asm/MC68332.h Normal file
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/* include/asm-m68knommu/MC68332.h: '332 control registers
*
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
*
*/
#ifndef _MC68332_H_
#define _MC68332_H_
#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
#define WORD_REF(addr) (*((volatile unsigned short*)addr))
#define PORTE_ADDR 0xfffa11
#define PORTE BYTE_REF(PORTE_ADDR)
#define DDRE_ADDR 0xfffa15
#define DDRE BYTE_REF(DDRE_ADDR)
#define PEPAR_ADDR 0xfffa17
#define PEPAR BYTE_REF(PEPAR_ADDR)
#define PORTF_ADDR 0xfffa19
#define PORTF BYTE_REF(PORTF_ADDR)
#define DDRF_ADDR 0xfffa1d
#define DDRF BYTE_REF(DDRF_ADDR)
#define PFPAR_ADDR 0xfffa1f
#define PFPAR BYTE_REF(PFPAR_ADDR)
#define PORTQS_ADDR 0xfffc15
#define PORTQS BYTE_REF(PORTQS_ADDR)
#define DDRQS_ADDR 0xfffc17
#define DDRQS BYTE_REF(DDRQS_ADDR)
#define PQSPAR_ADDR 0xfffc16
#define PQSPAR BYTE_REF(PQSPAR_ADDR)
#define CSPAR0_ADDR 0xFFFA44
#define CSPAR0 WORD_REF(CSPAR0_ADDR)
#define CSPAR1_ADDR 0xFFFA46
#define CSPAR1 WORD_REF(CSPAR1_ADDR)
#define CSARBT_ADDR 0xFFFA48
#define CSARBT WORD_REF(CSARBT_ADDR)
#define CSOPBT_ADDR 0xFFFA4A
#define CSOPBT WORD_REF(CSOPBT_ADDR)
#define CSBAR0_ADDR 0xFFFA4C
#define CSBAR0 WORD_REF(CSBAR0_ADDR)
#define CSOR0_ADDR 0xFFFA4E
#define CSOR0 WORD_REF(CSOR0_ADDR)
#define CSBAR1_ADDR 0xFFFA50
#define CSBAR1 WORD_REF(CSBAR1_ADDR)
#define CSOR1_ADDR 0xFFFA52
#define CSOR1 WORD_REF(CSOR1_ADDR)
#define CSBAR2_ADDR 0xFFFA54
#define CSBAR2 WORD_REF(CSBAR2_ADDR)
#define CSOR2_ADDR 0xFFFA56
#define CSOR2 WORD_REF(CSOR2_ADDR)
#define CSBAR3_ADDR 0xFFFA58
#define CSBAR3 WORD_REF(CSBAR3_ADDR)
#define CSOR3_ADDR 0xFFFA5A
#define CSOR3 WORD_REF(CSOR3_ADDR)
#define CSBAR4_ADDR 0xFFFA5C
#define CSBAR4 WORD_REF(CSBAR4_ADDR)
#define CSOR4_ADDR 0xFFFA5E
#define CSOR4 WORD_REF(CSOR4_ADDR)
#define CSBAR5_ADDR 0xFFFA60
#define CSBAR5 WORD_REF(CSBAR5_ADDR)
#define CSOR5_ADDR 0xFFFA62
#define CSOR5 WORD_REF(CSOR5_ADDR)
#define CSBAR6_ADDR 0xFFFA64
#define CSBAR6 WORD_REF(CSBAR6_ADDR)
#define CSOR6_ADDR 0xFFFA66
#define CSOR6 WORD_REF(CSOR6_ADDR)
#define CSBAR7_ADDR 0xFFFA68
#define CSBAR7 WORD_REF(CSBAR7_ADDR)
#define CSOR7_ADDR 0xFFFA6A
#define CSOR7 WORD_REF(CSOR7_ADDR)
#define CSBAR8_ADDR 0xFFFA6C
#define CSBAR8 WORD_REF(CSBAR8_ADDR)
#define CSOR8_ADDR 0xFFFA6E
#define CSOR8 WORD_REF(CSOR8_ADDR)
#define CSBAR9_ADDR 0xFFFA70
#define CSBAR9 WORD_REF(CSBAR9_ADDR)
#define CSOR9_ADDR 0xFFFA72
#define CSOR9 WORD_REF(CSOR9_ADDR)
#define CSBAR10_ADDR 0xFFFA74
#define CSBAR10 WORD_REF(CSBAR10_ADDR)
#define CSOR10_ADDR 0xFFFA76
#define CSOR10 WORD_REF(CSOR10_ADDR)
#define CSOR_MODE_ASYNC 0x0000
#define CSOR_MODE_SYNC 0x8000
#define CSOR_MODE_MASK 0x8000
#define CSOR_BYTE_DISABLE 0x0000
#define CSOR_BYTE_UPPER 0x4000
#define CSOR_BYTE_LOWER 0x2000
#define CSOR_BYTE_BOTH 0x6000
#define CSOR_BYTE_MASK 0x6000
#define CSOR_RW_RSVD 0x0000
#define CSOR_RW_READ 0x0800
#define CSOR_RW_WRITE 0x1000
#define CSOR_RW_BOTH 0x1800
#define CSOR_RW_MASK 0x1800
#define CSOR_STROBE_DS 0x0400
#define CSOR_STROBE_AS 0x0000
#define CSOR_STROBE_MASK 0x0400
#define CSOR_DSACK_WAIT(x) (wait << 6)
#define CSOR_DSACK_FTERM (14 << 6)
#define CSOR_DSACK_EXTERNAL (15 << 6)
#define CSOR_DSACK_MASK 0x03c0
#define CSOR_SPACE_CPU 0x0000
#define CSOR_SPACE_USER 0x0010
#define CSOR_SPACE_SU 0x0020
#define CSOR_SPACE_BOTH 0x0030
#define CSOR_SPACE_MASK 0x0030
#define CSOR_IPL_ALL 0x0000
#define CSOR_IPL_PRIORITY(x) (x << 1)
#define CSOR_IPL_MASK 0x000e
#define CSOR_AVEC_ON 0x0001
#define CSOR_AVEC_OFF 0x0000
#define CSOR_AVEC_MASK 0x0001
#define CSBAR_ADDR(x) ((addr >> 11) << 3)
#define CSBAR_ADDR_MASK 0xfff8
#define CSBAR_BLKSIZE_2K 0x0000
#define CSBAR_BLKSIZE_8K 0x0001
#define CSBAR_BLKSIZE_16K 0x0002
#define CSBAR_BLKSIZE_64K 0x0003
#define CSBAR_BLKSIZE_128K 0x0004
#define CSBAR_BLKSIZE_256K 0x0005
#define CSBAR_BLKSIZE_512K 0x0006
#define CSBAR_BLKSIZE_1M 0x0007
#define CSBAR_BLKSIZE_MASK 0x0007
#define CSPAR_DISC 0
#define CSPAR_ALT 1
#define CSPAR_CS8 2
#define CSPAR_CS16 3
#define CSPAR_MASK 3
#define CSPAR0_CSBOOT(x) (x << 0)
#define CSPAR0_CS0(x) (x << 2)
#define CSPAR0_CS1(x) (x << 4)
#define CSPAR0_CS2(x) (x << 6)
#define CSPAR0_CS3(x) (x << 8)
#define CSPAR0_CS4(x) (x << 10)
#define CSPAR0_CS5(x) (x << 12)
#define CSPAR1_CS6(x) (x << 0)
#define CSPAR1_CS7(x) (x << 2)
#define CSPAR1_CS8(x) (x << 4)
#define CSPAR1_CS9(x) (x << 6)
#define CSPAR1_CS10(x) (x << 8)
#endif

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arch/m68k/include/asm/MC68EZ328.h Normal file
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arch/m68k/include/asm/MC68VZ328.h Normal file
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67
arch/m68k/include/asm/a.out-core.h Normal file
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/* a.out coredump register dumper
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_A_OUT_CORE_H
#define _ASM_A_OUT_CORE_H
#ifdef __KERNEL__
#include <linux/user.h>
#include <linux/elfcore.h>
/*
* fill in the user structure for an a.out core dump
*/
static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
{
struct switch_stack *sw;
/* changed the size calculations - should hopefully work better. lbt */
dump->magic = CMAGIC;
dump->start_code = 0;
dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
dump->u_dsize = ((unsigned long) (current->mm->brk +
(PAGE_SIZE-1))) >> PAGE_SHIFT;
dump->u_dsize -= dump->u_tsize;
dump->u_ssize = 0;
if (dump->start_stack < TASK_SIZE)
dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
dump->u_ar0 = offsetof(struct user, regs);
sw = ((struct switch_stack *)regs) - 1;
dump->regs.d1 = regs->d1;
dump->regs.d2 = regs->d2;
dump->regs.d3 = regs->d3;
dump->regs.d4 = regs->d4;
dump->regs.d5 = regs->d5;
dump->regs.d6 = sw->d6;
dump->regs.d7 = sw->d7;
dump->regs.a0 = regs->a0;
dump->regs.a1 = regs->a1;
dump->regs.a2 = regs->a2;
dump->regs.a3 = sw->a3;
dump->regs.a4 = sw->a4;
dump->regs.a5 = sw->a5;
dump->regs.a6 = sw->a6;
dump->regs.d0 = regs->d0;
dump->regs.orig_d0 = regs->orig_d0;
dump->regs.stkadj = regs->stkadj;
dump->regs.sr = regs->sr;
dump->regs.pc = regs->pc;
dump->regs.fmtvec = (regs->format << 12) | regs->vector;
/* dump floating point stuff */
dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp);
}
#endif /* __KERNEL__ */
#endif /* _ASM_A_OUT_CORE_H */

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#ifndef __M68K_A_OUT_H__
#define __M68K_A_OUT_H__
struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
unsigned a_text; /* length of text, in bytes */
unsigned a_data; /* length of data, in bytes */
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
unsigned a_syms; /* length of symbol table data in file, in bytes */
unsigned a_entry; /* start address */
unsigned a_trsize; /* length of relocation info for text, in bytes */
unsigned a_drsize; /* length of relocation info for data, in bytes */
};
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
#endif /* __M68K_A_OUT_H__ */

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arch/m68k/include/asm/adb_iop.h Normal file
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/*
* ADB through the IOP
* Written by Joshua M. Thompson
*/
/* IOP number and channel number for ADB */
#define ADB_IOP IOP_NUM_ISM
#define ADB_CHAN 2
/* From the A/UX headers...maybe important, maybe not */
#define ADB_IOP_LISTEN 0x01
#define ADB_IOP_TALK 0x02
#define ADB_IOP_EXISTS 0x04
#define ADB_IOP_FLUSH 0x08
#define ADB_IOP_RESET 0x10
#define ADB_IOP_INT 0x20
#define ADB_IOP_POLL 0x40
#define ADB_IOP_UNINT 0x80
#define AIF_RESET 0x00
#define AIF_FLUSH 0x01
#define AIF_LISTEN 0x08
#define AIF_TALK 0x0C
/* Flag bits in struct adb_iopmsg */
#define ADB_IOP_EXPLICIT 0x80 /* nonzero if explicit command */
#define ADB_IOP_AUTOPOLL 0x40 /* auto/SRQ polling enabled */
#define ADB_IOP_SRQ 0x04 /* SRQ detected */
#define ADB_IOP_TIMEOUT 0x02 /* nonzero if timeout */
#ifndef __ASSEMBLY__
struct adb_iopmsg {
__u8 flags; /* ADB flags */
__u8 count; /* no. of data bytes */
__u8 cmd; /* ADB command */
__u8 data[8]; /* ADB data */
__u8 spare[21]; /* spare */
};
#endif /* __ASSEMBLY__ */

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arch/m68k/include/asm/amigahw.h Normal file
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/*
** asm-m68k/amigahw.h -- This header defines some macros and pointers for
** the various Amiga custom hardware registers.
** The naming conventions used here conform to those
** used in the Amiga Hardware Reference Manual, 3rd Edition
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 9/24/92 by Greg Harp
*/
#ifndef _M68K_AMIGAHW_H
#define _M68K_AMIGAHW_H
#include <linux/ioport.h>
/*
* Different Amiga models
*/
#define AMI_UNKNOWN (0)
#define AMI_500 (1)
#define AMI_500PLUS (2)
#define AMI_600 (3)
#define AMI_1000 (4)
#define AMI_1200 (5)
#define AMI_2000 (6)
#define AMI_2500 (7)
#define AMI_3000 (8)
#define AMI_3000T (9)
#define AMI_3000PLUS (10)
#define AMI_4000 (11)
#define AMI_4000T (12)
#define AMI_CDTV (13)
#define AMI_CD32 (14)
#define AMI_DRACO (15)
/*
* Chipsets
*/
extern unsigned long amiga_chipset;
#define CS_STONEAGE (0)
#define CS_OCS (1)
#define CS_ECS (2)
#define CS_AGA (3)
/*
* Miscellaneous
*/
extern unsigned long amiga_eclock; /* 700 kHz E Peripheral Clock */
extern unsigned long amiga_colorclock; /* 3.5 MHz Color Clock */
extern unsigned long amiga_chip_size; /* Chip RAM Size (bytes) */
extern unsigned char amiga_vblank; /* VBLANK Frequency */
#define AMIGAHW_DECLARE(name) unsigned name : 1
#define AMIGAHW_SET(name) (amiga_hw_present.name = 1)
#define AMIGAHW_PRESENT(name) (amiga_hw_present.name)
struct amiga_hw_present {
/* video hardware */
AMIGAHW_DECLARE(AMI_VIDEO); /* Amiga Video */
AMIGAHW_DECLARE(AMI_BLITTER); /* Amiga Blitter */
AMIGAHW_DECLARE(AMBER_FF); /* Amber Flicker Fixer */
/* sound hardware */
AMIGAHW_DECLARE(AMI_AUDIO); /* Amiga Audio */
/* disk storage interfaces */
AMIGAHW_DECLARE(AMI_FLOPPY); /* Amiga Floppy */
AMIGAHW_DECLARE(A3000_SCSI); /* SCSI (wd33c93, A3000 alike) */
AMIGAHW_DECLARE(A4000_SCSI); /* SCSI (ncr53c710, A4000T alike) */
AMIGAHW_DECLARE(A1200_IDE); /* IDE (A1200 alike) */
AMIGAHW_DECLARE(A4000_IDE); /* IDE (A4000 alike) */
AMIGAHW_DECLARE(CD_ROM); /* CD ROM drive */
/* other I/O hardware */
AMIGAHW_DECLARE(AMI_KEYBOARD); /* Amiga Keyboard */
AMIGAHW_DECLARE(AMI_MOUSE); /* Amiga Mouse */
AMIGAHW_DECLARE(AMI_SERIAL); /* Amiga Serial */
AMIGAHW_DECLARE(AMI_PARALLEL); /* Amiga Parallel */
/* real time clocks */
AMIGAHW_DECLARE(A2000_CLK); /* Hardware Clock (A2000 alike) */
AMIGAHW_DECLARE(A3000_CLK); /* Hardware Clock (A3000 alike) */
/* supporting hardware */
AMIGAHW_DECLARE(CHIP_RAM); /* Chip RAM */
AMIGAHW_DECLARE(PAULA); /* Paula (8364) */
AMIGAHW_DECLARE(DENISE); /* Denise (8362) */
AMIGAHW_DECLARE(DENISE_HR); /* Denise (8373) */
AMIGAHW_DECLARE(LISA); /* Lisa (8375) */
AMIGAHW_DECLARE(AGNUS_PAL); /* Normal/Fat PAL Agnus (8367/8371) */
AMIGAHW_DECLARE(AGNUS_NTSC); /* Normal/Fat NTSC Agnus (8361/8370) */
AMIGAHW_DECLARE(AGNUS_HR_PAL); /* Fat Hires PAL Agnus (8372) */
AMIGAHW_DECLARE(AGNUS_HR_NTSC); /* Fat Hires NTSC Agnus (8372) */
AMIGAHW_DECLARE(ALICE_PAL); /* PAL Alice (8374) */
AMIGAHW_DECLARE(ALICE_NTSC); /* NTSC Alice (8374) */
AMIGAHW_DECLARE(MAGIC_REKICK); /* A3000 Magic Hard Rekick */
AMIGAHW_DECLARE(PCMCIA); /* PCMCIA Slot */
AMIGAHW_DECLARE(GG2_ISA); /* GG2 Zorro2ISA Bridge */
AMIGAHW_DECLARE(ZORRO); /* Zorro AutoConfig */
AMIGAHW_DECLARE(ZORRO3); /* Zorro III */
};
extern struct amiga_hw_present amiga_hw_present;
struct CUSTOM {
unsigned short bltddat;
unsigned short dmaconr;
unsigned short vposr;
unsigned short vhposr;
unsigned short dskdatr;
unsigned short joy0dat;
unsigned short joy1dat;
unsigned short clxdat;
unsigned short adkconr;
unsigned short pot0dat;
unsigned short pot1dat;
unsigned short potgor;
unsigned short serdatr;
unsigned short dskbytr;
unsigned short intenar;
unsigned short intreqr;
unsigned char *dskptr;
unsigned short dsklen;
unsigned short dskdat;
unsigned short refptr;
unsigned short vposw;
unsigned short vhposw;
unsigned short copcon;
unsigned short serdat;
unsigned short serper;
unsigned short potgo;
unsigned short joytest;
unsigned short strequ;
unsigned short strvbl;
unsigned short strhor;
unsigned short strlong;
unsigned short bltcon0;
unsigned short bltcon1;
unsigned short bltafwm;
unsigned short bltalwm;
unsigned char *bltcpt;
unsigned char *bltbpt;
unsigned char *bltapt;
unsigned char *bltdpt;
unsigned short bltsize;
unsigned char pad2d;
unsigned char bltcon0l;
unsigned short bltsizv;
unsigned short bltsizh;
unsigned short bltcmod;
unsigned short bltbmod;
unsigned short bltamod;
unsigned short bltdmod;
unsigned short spare2[4];
unsigned short bltcdat;
unsigned short bltbdat;
unsigned short bltadat;
unsigned short spare3[3];
unsigned short deniseid;
unsigned short dsksync;
unsigned short *cop1lc;
unsigned short *cop2lc;
unsigned short copjmp1;
unsigned short copjmp2;
unsigned short copins;
unsigned short diwstrt;
unsigned short diwstop;
unsigned short ddfstrt;
unsigned short ddfstop;
unsigned short dmacon;
unsigned short clxcon;
unsigned short intena;
unsigned short intreq;
unsigned short adkcon;
struct {
unsigned short *audlc;
unsigned short audlen;
unsigned short audper;
unsigned short audvol;
unsigned short auddat;
unsigned short audspare[2];
} aud[4];
unsigned char *bplpt[8];
unsigned short bplcon0;
unsigned short bplcon1;
unsigned short bplcon2;
unsigned short bplcon3;
unsigned short bpl1mod;
unsigned short bpl2mod;
unsigned short bplcon4;
unsigned short clxcon2;
unsigned short bpldat[8];
unsigned char *sprpt[8];
struct {
unsigned short pos;
unsigned short ctl;
unsigned short dataa;
unsigned short datab;
} spr[8];
unsigned short color[32];
unsigned short htotal;
unsigned short hsstop;
unsigned short hbstrt;
unsigned short hbstop;
unsigned short vtotal;
unsigned short vsstop;
unsigned short vbstrt;
unsigned short vbstop;
unsigned short sprhstrt;
unsigned short sprhstop;
unsigned short bplhstrt;
unsigned short bplhstop;
unsigned short hhposw;
unsigned short hhposr;
unsigned short beamcon0;
unsigned short hsstrt;
unsigned short vsstrt;
unsigned short hcenter;
unsigned short diwhigh;
unsigned short spare4[11];
unsigned short fmode;
};
/*
* DMA register bits
*/
#define DMAF_SETCLR (0x8000)
#define DMAF_AUD0 (0x0001)
#define DMAF_AUD1 (0x0002)
#define DMAF_AUD2 (0x0004)
#define DMAF_AUD3 (0x0008)
#define DMAF_DISK (0x0010)
#define DMAF_SPRITE (0x0020)
#define DMAF_BLITTER (0x0040)
#define DMAF_COPPER (0x0080)
#define DMAF_RASTER (0x0100)
#define DMAF_MASTER (0x0200)
#define DMAF_BLITHOG (0x0400)
#define DMAF_BLTNZERO (0x2000)
#define DMAF_BLTDONE (0x4000)
#define DMAF_ALL (0x01FF)
struct CIA {
unsigned char pra; char pad0[0xff];
unsigned char prb; char pad1[0xff];
unsigned char ddra; char pad2[0xff];
unsigned char ddrb; char pad3[0xff];
unsigned char talo; char pad4[0xff];
unsigned char tahi; char pad5[0xff];
unsigned char tblo; char pad6[0xff];
unsigned char tbhi; char pad7[0xff];
unsigned char todlo; char pad8[0xff];
unsigned char todmid; char pad9[0xff];
unsigned char todhi; char pada[0x1ff];
unsigned char sdr; char padb[0xff];
unsigned char icr; char padc[0xff];
unsigned char cra; char padd[0xff];
unsigned char crb; char pade[0xff];
};
#define zTwoBase (0x80000000)
#define ZTWO_PADDR(x) (((unsigned long)(x))-zTwoBase)
#define ZTWO_VADDR(x) (((unsigned long)(x))+zTwoBase)
#define CUSTOM_PHYSADDR (0xdff000)
#define amiga_custom ((*(volatile struct CUSTOM *)(zTwoBase+CUSTOM_PHYSADDR)))
#define CIAA_PHYSADDR (0xbfe001)
#define CIAB_PHYSADDR (0xbfd000)
#define ciaa ((*(volatile struct CIA *)(zTwoBase + CIAA_PHYSADDR)))
#define ciab ((*(volatile struct CIA *)(zTwoBase + CIAB_PHYSADDR)))
#define CHIP_PHYSADDR (0x000000)
void amiga_chip_init (void);
void *amiga_chip_alloc(unsigned long size, const char *name);
void *amiga_chip_alloc_res(unsigned long size, struct resource *res);
void amiga_chip_free(void *ptr);
unsigned long amiga_chip_avail( void ); /*MILAN*/
extern volatile unsigned short amiga_audio_min_period;
static inline void amifb_video_off(void)
{
if (amiga_chipset == CS_ECS || amiga_chipset == CS_AGA) {
/* program Denise/Lisa for a higher maximum play rate */
amiga_custom.htotal = 113; /* 31 kHz */
amiga_custom.vtotal = 223; /* 70 Hz */
amiga_custom.beamcon0 = 0x4390; /* HARDDIS, VAR{BEAM,VSY,HSY,CSY}EN */
/* suspend the monitor */
amiga_custom.hsstrt = amiga_custom.hsstop = 116;
amiga_custom.vsstrt = amiga_custom.vsstop = 226;
amiga_audio_min_period = 57;
}
}
struct tod3000 {
unsigned int :28, second2:4; /* lower digit */
unsigned int :28, second1:4; /* upper digit */
unsigned int :28, minute2:4; /* lower digit */
unsigned int :28, minute1:4; /* upper digit */
unsigned int :28, hour2:4; /* lower digit */
unsigned int :28, hour1:4; /* upper digit */
unsigned int :28, weekday:4;
unsigned int :28, day2:4; /* lower digit */
unsigned int :28, day1:4; /* upper digit */
unsigned int :28, month2:4; /* lower digit */
unsigned int :28, month1:4; /* upper digit */
unsigned int :28, year2:4; /* lower digit */
unsigned int :28, year1:4; /* upper digit */
unsigned int :28, cntrl1:4; /* control-byte 1 */
unsigned int :28, cntrl2:4; /* control-byte 2 */
unsigned int :28, cntrl3:4; /* control-byte 3 */
};
#define TOD3000_CNTRL1_HOLD 0
#define TOD3000_CNTRL1_FREE 9
#define tod_3000 ((*(volatile struct tod3000 *)(zTwoBase+0xDC0000)))
struct tod2000 {
unsigned int :28, second2:4; /* lower digit */
unsigned int :28, second1:4; /* upper digit */
unsigned int :28, minute2:4; /* lower digit */
unsigned int :28, minute1:4; /* upper digit */
unsigned int :28, hour2:4; /* lower digit */
unsigned int :28, hour1:4; /* upper digit */
unsigned int :28, day2:4; /* lower digit */
unsigned int :28, day1:4; /* upper digit */
unsigned int :28, month2:4; /* lower digit */
unsigned int :28, month1:4; /* upper digit */
unsigned int :28, year2:4; /* lower digit */
unsigned int :28, year1:4; /* upper digit */
unsigned int :28, weekday:4;
unsigned int :28, cntrl1:4; /* control-byte 1 */
unsigned int :28, cntrl2:4; /* control-byte 2 */
unsigned int :28, cntrl3:4; /* control-byte 3 */
};
#define TOD2000_CNTRL1_HOLD (1<<0)
#define TOD2000_CNTRL1_BUSY (1<<1)
#define TOD2000_CNTRL3_24HMODE (1<<2)
#define TOD2000_HOUR1_PM (1<<2)
#define tod_2000 ((*(volatile struct tod2000 *)(zTwoBase+0xDC0000)))
#endif /* _M68K_AMIGAHW_H */

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/*
** amigaints.h -- Amiga Linux interrupt handling structs and prototypes
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created 10/2/92 by Greg Harp
*/
#ifndef _ASMm68k_AMIGAINTS_H_
#define _ASMm68k_AMIGAINTS_H_
#include <asm/irq.h>
/*
** Amiga Interrupt sources.
**
*/
#define AUTO_IRQS (8)
#define AMI_STD_IRQS (14)
#define CIA_IRQS (5)
#define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */
/* builtin serial port interrupts */
#define IRQ_AMIGA_TBE (IRQ_USER+0)
#define IRQ_AMIGA_RBF (IRQ_USER+11)
/* floppy disk interrupts */
#define IRQ_AMIGA_DSKBLK (IRQ_USER+1)
#define IRQ_AMIGA_DSKSYN (IRQ_USER+12)
/* software interrupts */
#define IRQ_AMIGA_SOFT (IRQ_USER+2)
/* interrupts from external hardware */
#define IRQ_AMIGA_PORTS IRQ_AUTO_2
#define IRQ_AMIGA_EXTER IRQ_AUTO_6
/* copper interrupt */
#define IRQ_AMIGA_COPPER (IRQ_USER+4)
/* vertical blanking interrupt */
#define IRQ_AMIGA_VERTB (IRQ_USER+5)
/* Blitter done interrupt */
#define IRQ_AMIGA_BLIT (IRQ_USER+6)
/* Audio interrupts */
#define IRQ_AMIGA_AUD0 (IRQ_USER+7)
#define IRQ_AMIGA_AUD1 (IRQ_USER+8)
#define IRQ_AMIGA_AUD2 (IRQ_USER+9)
#define IRQ_AMIGA_AUD3 (IRQ_USER+10)
/* CIA interrupt sources */
#define IRQ_AMIGA_CIAA (IRQ_USER+14)
#define IRQ_AMIGA_CIAA_TA (IRQ_USER+14)
#define IRQ_AMIGA_CIAA_TB (IRQ_USER+15)
#define IRQ_AMIGA_CIAA_ALRM (IRQ_USER+16)
#define IRQ_AMIGA_CIAA_SP (IRQ_USER+17)
#define IRQ_AMIGA_CIAA_FLG (IRQ_USER+18)
#define IRQ_AMIGA_CIAB (IRQ_USER+19)
#define IRQ_AMIGA_CIAB_TA (IRQ_USER+19)
#define IRQ_AMIGA_CIAB_TB (IRQ_USER+20)
#define IRQ_AMIGA_CIAB_ALRM (IRQ_USER+21)
#define IRQ_AMIGA_CIAB_SP (IRQ_USER+22)
#define IRQ_AMIGA_CIAB_FLG (IRQ_USER+23)
/* INTREQR masks */
#define IF_SETCLR 0x8000 /* set/clr bit */
#define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */
#define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */
#define IF_DSKSYN 0x1000 /* disk sync interrupt */
#define IF_RBF 0x0800 /* serial receive buffer full interrupt */
#define IF_AUD3 0x0400 /* audio channel 3 done interrupt */
#define IF_AUD2 0x0200 /* audio channel 2 done interrupt */
#define IF_AUD1 0x0100 /* audio channel 1 done interrupt */
#define IF_AUD0 0x0080 /* audio channel 0 done interrupt */
#define IF_BLIT 0x0040 /* blitter done interrupt */
#define IF_VERTB 0x0020 /* vertical blanking interrupt */
#define IF_COPER 0x0010 /* copper interrupt */
#define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */
#define IF_SOFT 0x0004 /* software initiated interrupt */
#define IF_DSKBLK 0x0002 /* diskblock DMA finished */
#define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */
/* CIA interrupt control register bits */
#define CIA_ICR_TA 0x01
#define CIA_ICR_TB 0x02
#define CIA_ICR_ALRM 0x04
#define CIA_ICR_SP 0x08
#define CIA_ICR_FLG 0x10
#define CIA_ICR_ALL 0x1f
#define CIA_ICR_SETCLR 0x80
extern void amiga_init_IRQ(void);
/* to access the interrupt control registers of CIA's use only
** these functions, they behave exactly like the amiga os routines
*/
extern struct ciabase ciaa_base, ciab_base;
extern void cia_init_IRQ(struct ciabase *base);
extern unsigned char cia_set_irq(struct ciabase *base, unsigned char mask);
extern unsigned char cia_able_irq(struct ciabase *base, unsigned char mask);
#endif /* asm-m68k/amigaints.h */

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/*
** asm-m68k/amigayle.h -- This header defines the registers of the gayle chip
** found on the Amiga 1200
** This information was found by disassembling card.resource,
** so the definitions may not be 100% correct
** anyone has an official doc ?
**
** Copyright 1997 by Alain Malek
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 11/28/97 by Alain Malek
*/
#ifndef _M68K_AMIGAYLE_H_
#define _M68K_AMIGAYLE_H_
#include <linux/types.h>
#include <asm/amigahw.h>
/* memory layout */
#define GAYLE_RAM (0x600000+zTwoBase)
#define GAYLE_RAMSIZE (0x400000)
#define GAYLE_ATTRIBUTE (0xa00000+zTwoBase)
#define GAYLE_ATTRIBUTESIZE (0x020000)
#define GAYLE_IO (0xa20000+zTwoBase) /* 16bit and even 8bit registers */
#define GAYLE_IOSIZE (0x010000)
#define GAYLE_IO_8BITODD (0xa30000+zTwoBase) /* odd 8bit registers */
/* offset for accessing odd IO registers */
#define GAYLE_ODD (GAYLE_IO_8BITODD-GAYLE_IO-1)
/* GAYLE registers */
struct GAYLE {
u_char cardstatus;
u_char pad0[0x1000-1];
u_char intreq;
u_char pad1[0x1000-1];
u_char inten;
u_char pad2[0x1000-1];
u_char config;
u_char pad3[0x1000-1];
};
#define GAYLE_ADDRESS (0xda8000) /* gayle main registers base address */
#define GAYLE_RESET (0xa40000) /* write 0x00 to start reset,
read 1 byte to stop reset */
#define gayle (*(volatile struct GAYLE *)(zTwoBase+GAYLE_ADDRESS))
#define gayle_reset (*(volatile u_char *)(zTwoBase+GAYLE_RESET))
#define gayle_attribute ((volatile u_char *)(GAYLE_ATTRIBUTE))
#if 0
#define gayle_inb(a) readb( GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
#define gayle_outb(v,a) writeb( v, GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
#define gayle_inw(a) readw( GAYLE_IO+(a) )
#define gayle_outw(v,a) writew( v, GAYLE_IO+(a) )
#endif
/* GAYLE_CARDSTATUS bit def */
#define GAYLE_CS_CCDET 0x40 /* credit card detect */
#define GAYLE_CS_BVD1 0x20 /* battery voltage detect 1 */
#define GAYLE_CS_SC 0x20 /* credit card status change */
#define GAYLE_CS_BVD2 0x10 /* battery voltage detect 2 */
#define GAYLE_CS_DA 0x10 /* digital audio */
#define GAYLE_CS_WR 0x08 /* write enable (1 == enabled) */
#define GAYLE_CS_BSY 0x04 /* credit card busy */
#define GAYLE_CS_IRQ 0x04 /* interrupt request */
/* GAYLE_IRQ bit def */
#define GAYLE_IRQ_IDE 0x80
#define GAYLE_IRQ_CCDET 0x40
#define GAYLE_IRQ_BVD1 0x20
#define GAYLE_IRQ_SC 0x20
#define GAYLE_IRQ_BVD2 0x10
#define GAYLE_IRQ_DA 0x10
#define GAYLE_IRQ_WR 0x08
#define GAYLE_IRQ_BSY 0x04
#define GAYLE_IRQ_IRQ 0x04
#define GAYLE_IRQ_IDEACK1 0x02
#define GAYLE_IRQ_IDEACK0 0x01
/* GAYLE_CONFIG bit def
(bit 0-1 for program voltage, bit 2-3 for access speed */
#define GAYLE_CFG_0V 0x00
#define GAYLE_CFG_5V 0x01
#define GAYLE_CFG_12V 0x02
#define GAYLE_CFG_100NS 0x08
#define GAYLE_CFG_150NS 0x04
#define GAYLE_CFG_250NS 0x00
#define GAYLE_CFG_720NS 0x0c
#endif /* asm-m68k/amigayle.h */

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arch/m68k/include/asm/amipcmcia.h Normal file
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/*
** asm-m68k/pcmcia.h -- Amiga Linux PCMCIA Definitions
**
** Copyright 1997 by Alain Malek
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 12/10/97 by Alain Malek
*/
#ifndef __AMIGA_PCMCIA_H__
#define __AMIGA_PCMCIA_H__
#include <asm/amigayle.h>
/* prototypes */
void pcmcia_reset(void);
int pcmcia_copy_tuple(unsigned char tuple_id, void *tuple, int max_len);
void pcmcia_program_voltage(int voltage);
void pcmcia_access_speed(int speed);
void pcmcia_write_enable(void);
void pcmcia_write_disable(void);
static inline u_char pcmcia_read_status(void)
{
return (gayle.cardstatus & 0x7c);
}
static inline u_char pcmcia_get_intreq(void)
{
return (gayle.intreq);
}
static inline void pcmcia_ack_int(u_char intreq)
{
gayle.intreq = 0xf8;
}
static inline void pcmcia_enable_irq(void)
{
gayle.inten |= GAYLE_IRQ_IRQ;
}
static inline void pcmcia_disable_irq(void)
{
gayle.inten &= ~GAYLE_IRQ_IRQ;
}
#define PCMCIA_INSERTED (gayle.cardstatus & GAYLE_CS_CCDET)
/* valid voltages for pcmcia_ProgramVoltage */
#define PCMCIA_0V 0
#define PCMCIA_5V 5
#define PCMCIA_12V 12
/* valid speeds for pcmcia_AccessSpeed */
#define PCMCIA_SPEED_100NS 100
#define PCMCIA_SPEED_150NS 150
#define PCMCIA_SPEED_250NS 250
#define PCMCIA_SPEED_720NS 720
/* PCMCIA Tuple codes */
#define CISTPL_NULL 0x00
#define CISTPL_DEVICE 0x01
#define CISTPL_LONGLINK_CB 0x02
#define CISTPL_CONFIG_CB 0x04
#define CISTPL_CFTABLE_ENTRY_CB 0x05
#define CISTPL_LONGLINK_MFC 0x06
#define CISTPL_BAR 0x07
#define CISTPL_CHECKSUM 0x10
#define CISTPL_LONGLINK_A 0x11
#define CISTPL_LONGLINK_C 0x12
#define CISTPL_LINKTARGET 0x13
#define CISTPL_NO_LINK 0x14
#define CISTPL_VERS_1 0x15
#define CISTPL_ALTSTR 0x16
#define CISTPL_DEVICE_A 0x17
#define CISTPL_JEDEC_C 0x18
#define CISTPL_JEDEC_A 0x19
#define CISTPL_CONFIG 0x1a
#define CISTPL_CFTABLE_ENTRY 0x1b
#define CISTPL_DEVICE_OC 0x1c
#define CISTPL_DEVICE_OA 0x1d
#define CISTPL_DEVICE_GEO 0x1e
#define CISTPL_DEVICE_GEO_A 0x1f
#define CISTPL_MANFID 0x20
#define CISTPL_FUNCID 0x21
#define CISTPL_FUNCE 0x22
#define CISTPL_SWIL 0x23
#define CISTPL_END 0xff
/* FUNCID */
#define CISTPL_FUNCID_MULTI 0x00
#define CISTPL_FUNCID_MEMORY 0x01
#define CISTPL_FUNCID_SERIAL 0x02
#define CISTPL_FUNCID_PARALLEL 0x03
#define CISTPL_FUNCID_FIXED 0x04
#define CISTPL_FUNCID_VIDEO 0x05
#define CISTPL_FUNCID_NETWORK 0x06
#define CISTPL_FUNCID_AIMS 0x07
#define CISTPL_FUNCID_SCSI 0x08
#endif

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/****************************************************************************/
/*
* anchor.h -- Anchor CO-MEM Lite PCI host bridge part.
*
* (C) Copyright 2000, Moreton Bay (www.moreton.com.au)
*/
/****************************************************************************/
#ifndef anchor_h
#define anchor_h
/****************************************************************************/
/*
* Define basic addressing info.
*/
#if defined(CONFIG_M5407C3)
#define COMEM_BASE 0xFFFF0000 /* Base of CO-MEM address space */
#define COMEM_IRQ 25 /* IRQ of anchor part */
#else
#define COMEM_BASE 0x80000000 /* Base of CO-MEM address space */
#define COMEM_IRQ 25 /* IRQ of anchor part */
#endif
/****************************************************************************/
/*
* 4-byte registers of CO-MEM, so adjust register addresses for
* easy access. Handy macro for word access too.
*/
#define LREG(a) ((a) >> 2)
#define WREG(a) ((a) >> 1)
/*
* Define base addresses within CO-MEM Lite register address space.
*/
#define COMEM_I2O 0x0000 /* I2O registers */
#define COMEM_OPREGS 0x0400 /* Operation registers */
#define COMEM_PCIBUS 0x2000 /* Direct access to PCI bus */
#define COMEM_SHMEM 0x4000 /* Shared memory region */
#define COMEM_SHMEMSIZE 0x4000 /* Size of shared memory */
/*
* Define CO-MEM Registers.
*/
#define COMEM_I2OHISR 0x0030 /* I2O host interrupt status */
#define COMEM_I2OHIMR 0x0034 /* I2O host interrupt mask */
#define COMEM_I2OLISR 0x0038 /* I2O local interrupt status */
#define COMEM_I2OLIMR 0x003c /* I2O local interrupt mask */
#define COMEM_IBFPFIFO 0x0040 /* I2O inbound free/post FIFO */
#define COMEM_OBPFFIFO 0x0044 /* I2O outbound post/free FIFO */
#define COMEM_IBPFFIFO 0x0048 /* I2O inbound post/free FIFO */
#define COMEM_OBFPFIFO 0x004c /* I2O outbound free/post FIFO */
#define COMEM_DAHBASE 0x0460 /* Direct access base address */
#define COMEM_NVCMD 0x04a0 /* I2C serial command */
#define COMEM_NVREAD 0x04a4 /* I2C serial read */
#define COMEM_NVSTAT 0x04a8 /* I2C status */
#define COMEM_DMALBASE 0x04b0 /* DMA local base address */
#define COMEM_DMAHBASE 0x04b4 /* DMA host base address */
#define COMEM_DMASIZE 0x04b8 /* DMA size */
#define COMEM_DMACTL 0x04bc /* DMA control */
#define COMEM_HCTL 0x04e0 /* Host control */
#define COMEM_HINT 0x04e4 /* Host interrupt control/status */
#define COMEM_HLDATA 0x04e8 /* Host to local data mailbox */
#define COMEM_LINT 0x04f4 /* Local interrupt contole status */
#define COMEM_LHDATA 0x04f8 /* Local to host data mailbox */
#define COMEM_LBUSCFG 0x04fc /* Local bus configuration */
/*
* Commands and flags for use with Direct Access Register.
*/
#define COMEM_DA_IACK 0x00000000 /* Interrupt acknowledge (read) */
#define COMEM_DA_SPCL 0x00000010 /* Special cycle (write) */
#define COMEM_DA_MEMRD 0x00000004 /* Memory read cycle */
#define COMEM_DA_MEMWR 0x00000004 /* Memory write cycle */
#define COMEM_DA_IORD 0x00000002 /* I/O read cycle */
#define COMEM_DA_IOWR 0x00000002 /* I/O write cycle */
#define COMEM_DA_CFGRD 0x00000006 /* Configuration read cycle */
#define COMEM_DA_CFGWR 0x00000006 /* Configuration write cycle */
#define COMEM_DA_ADDR(a) ((a) & 0xffffe000)
#define COMEM_DA_OFFSET(a) ((a) & 0x00001fff)
/*
* The PCI bus will be limited in what slots will actually be used.
* Define valid device numbers for different boards.
*/
#if defined(CONFIG_M5407C3)
#define COMEM_MINDEV 14 /* Minimum valid DEVICE */
#define COMEM_MAXDEV 14 /* Maximum valid DEVICE */
#define COMEM_BRIDGEDEV 15 /* Slot bridge is in */
#else
#define COMEM_MINDEV 0 /* Minimum valid DEVICE */
#define COMEM_MAXDEV 3 /* Maximum valid DEVICE */
#endif
#define COMEM_MAXPCI (COMEM_MAXDEV+1) /* Maximum PCI devices */
/****************************************************************************/
#endif /* anchor_h */

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/*
* linux/include/asm/dma.h: Defines for using and allocating dma channels.
* Written by Hennus Bergman, 1992.
* High DMA channel support & info by Hannu Savolainen
* and John Boyd, Nov. 1992.
*/
#ifndef _ASM_APOLLO_DMA_H
#define _ASM_APOLLO_DMA_H
#include <asm/apollohw.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val))
#define dma_inb(addr) (*((volatile unsigned char *)(addr+IO_BASE)))
/*
* NOTES about DMA transfers:
*
* controller 1: channels 0-3, byte operations, ports 00-1F
* controller 2: channels 4-7, word operations, ports C0-DF
*
* - ALL registers are 8 bits only, regardless of transfer size
* - channel 4 is not used - cascades 1 into 2.
* - channels 0-3 are byte - addresses/counts are for physical bytes
* - channels 5-7 are word - addresses/counts are for physical words
* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
* - transfer count loaded to registers is 1 less than actual count
* - controller 2 offsets are all even (2x offsets for controller 1)
* - page registers for 5-7 don't use data bit 0, represent 128K pages
* - page registers for 0-3 use bit 0, represent 64K pages
*
* DMA transfers are limited to the lower 16MB of _physical_ memory.
* Note that addresses loaded into registers must be _physical_ addresses,
* not logical addresses (which may differ if paging is active).
*
* Address mapping for channels 0-3:
*
* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* P7 ... P0 A7 ... A0 A7 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Address mapping for channels 5-7:
*
* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
* | ... | \ \ ... \ \ \ ... \ \
* | ... | \ \ ... \ \ \ ... \ (not used)
* | ... | \ \ ... \ \ \ ... \
* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
* the hardware level, so odd-byte transfers aren't possible).
*
* Transfer count (_not # bytes_) is limited to 64K, represented as actual
* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
* and up to 128K bytes may be transferred on channels 5-7 in one operation.
*
*/
#define MAX_DMA_CHANNELS 8
/* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000)
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x10C00 /* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE 0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */
/* DMA controller registers */
#define DMA1_CMD_REG (IO_DMA1_BASE+0x08) /* command register (w) */
#define DMA1_STAT_REG (IO_DMA1_BASE+0x08) /* status register (r) */
#define DMA1_REQ_REG (IO_DMA1_BASE+0x09) /* request register (w) */
#define DMA1_MASK_REG (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */
#define DMA1_MODE_REG (IO_DMA1_BASE+0x0B) /* mode register (w) */
#define DMA1_CLEAR_FF_REG (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */
#define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */
#define DMA1_CLR_MASK_REG (IO_DMA1_BASE+0x0E) /* Clear Mask */
#define DMA1_MASK_ALL_REG (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */
#define DMA2_CMD_REG (IO_DMA2_BASE+0x10) /* command register (w) */
#define DMA2_STAT_REG (IO_DMA2_BASE+0x10) /* status register (r) */
#define DMA2_REQ_REG (IO_DMA2_BASE+0x12) /* request register (w) */
#define DMA2_MASK_REG (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
#define DMA2_MODE_REG (IO_DMA2_BASE+0x16) /* mode register (w) */
#define DMA2_CLEAR_FF_REG (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
#define DMA2_RESET_REG (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
#define DMA2_CLR_MASK_REG (IO_DMA2_BASE+0x1C) /* Clear Mask */
#define DMA2_MASK_ALL_REG (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */
#define DMA_ADDR_0 (IO_DMA1_BASE+0x00) /* DMA address registers */
#define DMA_ADDR_1 (IO_DMA1_BASE+0x02)
#define DMA_ADDR_2 (IO_DMA1_BASE+0x04)
#define DMA_ADDR_3 (IO_DMA1_BASE+0x06)
#define DMA_ADDR_4 (IO_DMA2_BASE+0x00)
#define DMA_ADDR_5 (IO_DMA2_BASE+0x04)
#define DMA_ADDR_6 (IO_DMA2_BASE+0x08)
#define DMA_ADDR_7 (IO_DMA2_BASE+0x0C)
#define DMA_CNT_0 (IO_DMA1_BASE+0x01) /* DMA count registers */
#define DMA_CNT_1 (IO_DMA1_BASE+0x03)
#define DMA_CNT_2 (IO_DMA1_BASE+0x05)
#define DMA_CNT_3 (IO_DMA1_BASE+0x07)
#define DMA_CNT_4 (IO_DMA2_BASE+0x02)
#define DMA_CNT_5 (IO_DMA2_BASE+0x06)
#define DMA_CNT_6 (IO_DMA2_BASE+0x0A)
#define DMA_CNT_7 (IO_DMA2_BASE+0x0E)
#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_AUTOINIT 0x10
#define DMA_8BIT 0
#define DMA_16BIT 1
#define DMA_BUSMASTER 2
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr, DMA1_MASK_REG);
else
dma_outb(dmanr & 3, DMA2_MASK_REG);
}
static __inline__ void disable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr | 4, DMA1_MASK_REG);
else
dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
}
/* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while holding the DMA lock ! ---
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(0, DMA1_CLEAR_FF_REG);
else
dma_outb(0, DMA2_CLEAR_FF_REG);
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
if (dmanr<=3)
dma_outb(mode | dmanr, DMA1_MODE_REG);
else
dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
}
/* Set transfer address & page bits for specific DMA channel.
* Assumes dma flipflop is clear.
*/
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
if (dmanr <= 3) {
dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
} else {
dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
}
}
/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
* a specific DMA channel.
* You must ensure the parameters are valid.
* NOTE: from a manual: "the number of transfers is one more
* than the initial word count"! This is taken into account.
* Assumes dma flip-flop is clear.
* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
count--;
if (dmanr <= 3) {
dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
} else {
dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
}
}
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* If called before the channel has been used, it may return 1.
* Otherwise, it returns the number of _bytes_ left to transfer.
*
* Assumes DMA flip-flop is clear.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/* using short to get 16-bit wrap around */
unsigned short count;
count = 1 + dma_inb(io_port);
count += dma_inb(io_port) << 8;
return (dmanr<=3)? count : (count<<1);
}
/* These are in kernel/dma.c: */
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
/* These are in arch/m68k/apollo/dma.c: */
extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type);
extern void dma_unmap_page(unsigned short dma_addr);
#endif /* _ASM_APOLLO_DMA_H */

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/* apollohw.h : some structures to access apollo HW */
#ifndef _ASMm68k_APOLLOHW_H_
#define _ASMm68k_APOLLOHW_H_
#include <linux/types.h>
/*
apollo models
*/
extern u_long apollo_model;
#define APOLLO_UNKNOWN (0)
#define APOLLO_DN3000 (1)
#define APOLLO_DN3010 (2)
#define APOLLO_DN3500 (3)
#define APOLLO_DN4000 (4)
#define APOLLO_DN4500 (5)
/*
see scn2681 data sheet for more info.
member names are read_write.
*/
#define DECLARE_2681_FIELD(x) unsigned char x; unsigned char dummy##x
struct SCN2681 {
DECLARE_2681_FIELD(mra);
DECLARE_2681_FIELD(sra_csra);
DECLARE_2681_FIELD(BRGtest_cra);
DECLARE_2681_FIELD(rhra_thra);
DECLARE_2681_FIELD(ipcr_acr);
DECLARE_2681_FIELD(isr_imr);
DECLARE_2681_FIELD(ctu_ctur);
DECLARE_2681_FIELD(ctl_ctlr);
DECLARE_2681_FIELD(mrb);
DECLARE_2681_FIELD(srb_csrb);
DECLARE_2681_FIELD(tst_crb);
DECLARE_2681_FIELD(rhrb_thrb);
DECLARE_2681_FIELD(reserved);
DECLARE_2681_FIELD(ip_opcr);
DECLARE_2681_FIELD(startCnt_setOutBit);
DECLARE_2681_FIELD(stopCnt_resetOutBit);
};
#if 0
struct mc146818 {
unsigned int second1:4, second2:4, alarm_second1:4, alarm_second2:4,
minute1:4, minute2:4, alarm_minute1:4, alarm_minute2:4;
unsigned int hours1:4, hours2:4, alarm_hours1:4, alarm_hours2:4,
day_of_week1:4, day_of_week2:4, day_of_month1:4, day_of_month2:4;
unsigned int month1:4, month2:4, year1:4, year2:4, :16;
};
#endif
struct mc146818 {
unsigned char second, alarm_second;
unsigned char minute, alarm_minute;
unsigned char hours, alarm_hours;
unsigned char day_of_week, day_of_month;
unsigned char month, year;
};
#define IO_BASE 0x80000000
extern u_long sio01_physaddr;
extern u_long sio23_physaddr;
extern u_long rtc_physaddr;
extern u_long pica_physaddr;
extern u_long picb_physaddr;
extern u_long cpuctrl_physaddr;
extern u_long timer_physaddr;
#define SAU7_SIO01_PHYSADDR 0x10400
#define SAU7_SIO23_PHYSADDR 0x10500
#define SAU7_RTC_PHYSADDR 0x10900
#define SAU7_PICA 0x11000
#define SAU7_PICB 0x11100
#define SAU7_CPUCTRL 0x10100
#define SAU7_TIMER 0x010800
#define SAU8_SIO01_PHYSADDR 0x8400
#define SAU8_RTC_PHYSADDR 0x8900
#define SAU8_PICA 0x9400
#define SAU8_PICB 0x9500
#define SAU8_CPUCTRL 0x8100
#define SAU8_TIMER 0x8800
#define sio01 ((*(volatile struct SCN2681 *)(IO_BASE + sio01_physaddr)))
#define sio23 ((*(volatile struct SCN2681 *)(IO_BASE + sio23_physaddr)))
#define rtc (((volatile struct mc146818 *)(IO_BASE + rtc_physaddr)))
#define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
#define pica (IO_BASE + pica_physaddr)
#define picb (IO_BASE + picb_physaddr)
#define timer (IO_BASE + timer_physaddr)
#define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
#define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
#define IRQ_APOLLO IRQ_USER
#endif

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#ifndef _ASM_M68K_FD_H
#define _ASM_M68K_FD_H
/* Definitions for the Atari Floppy driver */
struct atari_format_descr {
int track; /* to be formatted */
int head; /* "" "" */
int sect_offset; /* offset of first sector */
};
#endif

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#ifndef _LINUX_FDREG_H
#define _LINUX_FDREG_H
/*
** WD1772 stuff
*/
/* register codes */
#define FDCSELREG_STP (0x80) /* command/status register */
#define FDCSELREG_TRA (0x82) /* track register */
#define FDCSELREG_SEC (0x84) /* sector register */
#define FDCSELREG_DTA (0x86) /* data register */
/* register names for FDC_READ/WRITE macros */
#define FDCREG_CMD 0
#define FDCREG_STATUS 0
#define FDCREG_TRACK 2
#define FDCREG_SECTOR 4
#define FDCREG_DATA 6
/* command opcodes */
#define FDCCMD_RESTORE (0x00) /* - */
#define FDCCMD_SEEK (0x10) /* | */
#define FDCCMD_STEP (0x20) /* | TYP 1 Commands */
#define FDCCMD_STIN (0x40) /* | */
#define FDCCMD_STOT (0x60) /* - */
#define FDCCMD_RDSEC (0x80) /* - TYP 2 Commands */
#define FDCCMD_WRSEC (0xa0) /* - " */
#define FDCCMD_RDADR (0xc0) /* - */
#define FDCCMD_RDTRA (0xe0) /* | TYP 3 Commands */
#define FDCCMD_WRTRA (0xf0) /* - */
#define FDCCMD_FORCI (0xd0) /* - TYP 4 Command */
/* command modifier bits */
#define FDCCMDADD_SR6 (0x00) /* step rate settings */
#define FDCCMDADD_SR12 (0x01)
#define FDCCMDADD_SR2 (0x02)
#define FDCCMDADD_SR3 (0x03)
#define FDCCMDADD_V (0x04) /* verify */
#define FDCCMDADD_H (0x08) /* wait for spin-up */
#define FDCCMDADD_U (0x10) /* update track register */
#define FDCCMDADD_M (0x10) /* multiple sector access */
#define FDCCMDADD_E (0x04) /* head settling flag */
#define FDCCMDADD_P (0x02) /* precompensation off */
#define FDCCMDADD_A0 (0x01) /* DAM flag */
/* status register bits */
#define FDCSTAT_MOTORON (0x80) /* motor on */
#define FDCSTAT_WPROT (0x40) /* write protected (FDCCMD_WR*) */
#define FDCSTAT_SPINUP (0x20) /* motor speed stable (Type I) */
#define FDCSTAT_DELDAM (0x20) /* sector has deleted DAM (Type II+III) */
#define FDCSTAT_RECNF (0x10) /* record not found */
#define FDCSTAT_CRC (0x08) /* CRC error */
#define FDCSTAT_TR00 (0x04) /* Track 00 flag (Type I) */
#define FDCSTAT_LOST (0x04) /* Lost Data (Type II+III) */
#define FDCSTAT_IDX (0x02) /* Index status (Type I) */
#define FDCSTAT_DRQ (0x02) /* DRQ status (Type II+III) */
#define FDCSTAT_BUSY (0x01) /* FDC is busy */
/* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1 1 -> Side 2 */
#define DSKSIDE (0x01)
#define DSKDRVNONE (0x06)
#define DSKDRV0 (0x02)
#define DSKDRV1 (0x04)
/* step rates */
#define FDCSTEP_6 0x00
#define FDCSTEP_12 0x01
#define FDCSTEP_2 0x02
#define FDCSTEP_3 0x03
#endif

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arch/m68k/include/asm/atari_joystick.h Normal file
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#ifndef _LINUX_ATARI_JOYSTICK_H
#define _LINUX_ATARI_JOYSTICK_H
/*
* linux/include/linux/atari_joystick.h
* header file for Atari Joystick driver
* by Robert de Vries (robert@and.nl) on 19Jul93
*/
void atari_joystick_interrupt(char*);
int atari_joystick_init(void);
extern int atari_mouse_buttons;
struct joystick_status {
char fire;
char dir;
int ready;
int active;
wait_queue_head_t wait;
};
#endif

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arch/m68k/include/asm/atari_stdma.h Normal file
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#ifndef _atari_stdma_h
#define _atari_stdma_h
#include <linux/interrupt.h>
/***************************** Prototypes *****************************/
void stdma_lock(irq_handler_t handler, void *data);
void stdma_release( void );
int stdma_others_waiting( void );
int stdma_islocked( void );
void *stdma_locked_by( void );
void stdma_init( void );
/************************* End of Prototypes **************************/
#endif /* _atari_stdma_h */

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#ifndef _M68K_ATARI_STRAM_H
#define _M68K_ATARI_STRAM_H
/*
* Functions for Atari ST-RAM management
*/
/* public interface */
void *atari_stram_alloc(long size, const char *owner);
void atari_stram_free(void *);
/* functions called internally by other parts of the kernel */
void atari_stram_init(void);
void atari_stram_reserve_pages(void *start_mem);
void atari_stram_mem_init_hook (void);
#endif /*_M68K_ATARI_STRAM_H */

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arch/m68k/include/asm/atarihw.h Normal file
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/*
** linux/atarihw.h -- This header defines some macros and pointers for
** the various Atari custom hardware registers.
**
** Copyright 1994 by Björn Brauel
**
** 5/1/94 Roman Hodek:
** Added definitions for TT specific chips.
**
** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>:
** Finally added definitions for the matrix/codec and the DSP56001 host
** interface.
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _LINUX_ATARIHW_H_
#define _LINUX_ATARIHW_H_
#include <linux/types.h>
#include <asm/bootinfo.h>
#include <asm/raw_io.h>
extern u_long atari_mch_cookie;
extern u_long atari_mch_type;
extern u_long atari_switches;
extern int atari_rtc_year_offset;
extern int atari_dont_touch_floppy_select;
/* convenience macros for testing machine type */
#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST)
#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
(atari_mch_cookie & 0xffff) == 0)
#define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
(atari_mch_cookie & 0xffff) == 0x10)
#define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
#define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
#define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA)
#define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40)
/* values for atari_switches */
#define ATARI_SWITCH_IKBD 0x01
#define ATARI_SWITCH_MIDI 0x02
#define ATARI_SWITCH_SND6 0x04
#define ATARI_SWITCH_SND7 0x08
#define ATARI_SWITCH_OVSC_SHIFT 16
#define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_MASK 0xffff0000
/*
* Define several Hardware-Chips for indication so that for the ATARI we do
* no longer decide whether it is a Falcon or other machine . It's just
* important what hardware the machine uses
*/
/* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */
#define ATARIHW_DECLARE(name) unsigned name : 1
#define ATARIHW_SET(name) (atari_hw_present.name = 1)
#define ATARIHW_PRESENT(name) (atari_hw_present.name)
struct atari_hw_present {
/* video hardware */
ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
/* sound hardware */
ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */
ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */
ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */
/* disk storage interfaces */
ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */
ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */
ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */
ATARIHW_DECLARE(IDE); /* IDE Interface */
ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */
/* other I/O hardware */
ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari
without it... but who knows?) */
ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */
ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe
and Falcon */
ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */
/* DMA */
ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */
ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */
ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
/* real time clocks */
ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */
ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */
/* supporting hardware */
ATARIHW_DECLARE(SCU); /* System Control Unit */
ATARIHW_DECLARE(BLITTER); /* Blitter */
ATARIHW_DECLARE(VME); /* VME Bus */
ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */
};
extern struct atari_hw_present atari_hw_present;
/* Reading the MFP port register gives a machine independent delay, since the
* MFP always has a 8 MHz clock. This avoids problems with the varying length
* of nops on various machines. Somebody claimed that the tstb takes 600 ns.
*/
#define MFPDELAY() \
__asm__ __volatile__ ( "tstb %0" : : "m" (mfp.par_dt_reg) : "cc" );
/* Do cache push/invalidate for DMA read/write. This function obeys the
* snooping on some machines (Medusa) and processors: The Medusa itself can
* snoop, but only the '040 can source data from its cache to DMA writes i.e.,
* reads from memory). Both '040 and '060 invalidate cache entries on snooped
* DMA reads (i.e., writes to memory).
*/
#define atari_readb raw_inb
#define atari_writeb raw_outb
#define atari_inb_p raw_inb
#define atari_outb_p raw_outb
#include <linux/mm.h>
#include <asm/cacheflush.h>
static inline void dma_cache_maintenance( unsigned long paddr,
unsigned long len,
int writeflag )
{
if (writeflag) {
if (!MACH_IS_MEDUSA || CPU_IS_060)
cache_push( paddr, len );
}
else {
if (!MACH_IS_MEDUSA)
cache_clear( paddr, len );
}
}
/*
** Shifter
*/
#define ST_LOW 0
#define ST_MID 1
#define ST_HIGH 2
#define TT_LOW 7
#define TT_MID 4
#define TT_HIGH 6
#define SHF_BAS (0xffff8200)
struct SHIFTER
{
u_char pad1;
u_char bas_hi;
u_char pad2;
u_char bas_md;
u_char pad3;
u_char volatile vcounthi;
u_char pad4;
u_char volatile vcountmid;
u_char pad5;
u_char volatile vcountlow;
u_char volatile syncmode;
u_char pad6;
u_char pad7;
u_char bas_lo;
};
# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
#define SHF_FBAS (0xffff820e)
struct SHIFTER_F030
{
u_short off_next;
u_short scn_width;
};
# define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
#define SHF_TBAS (0xffff8200)
struct SHIFTER_TT {
u_char char_dummy0;
u_char bas_hi; /* video mem base addr, high and mid byte */
u_char char_dummy1;
u_char bas_md;
u_char char_dummy2;
u_char vcount_hi; /* pointer to currently displayed byte */
u_char char_dummy3;
u_char vcount_md;
u_char char_dummy4;
u_char vcount_lo;
u_short st_sync; /* ST compatible sync mode register, unused */
u_char char_dummy5;
u_char bas_lo; /* video mem addr, low byte */
u_char char_dummy6[2+3*16];
/* $ffff8240: */
u_short color_reg[16]; /* 16 color registers */
u_char st_shiftmode; /* ST compatible shift mode register, unused */
u_char char_dummy7;
u_short tt_shiftmode; /* TT shift mode register */
};
#define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS))
/* values for shifter_tt->tt_shiftmode */
#define TT_SHIFTER_STLOW 0x0000
#define TT_SHIFTER_STMID 0x0100
#define TT_SHIFTER_STHIGH 0x0200
#define TT_SHIFTER_TTLOW 0x0700
#define TT_SHIFTER_TTMID 0x0400
#define TT_SHIFTER_TTHIGH 0x0600
#define TT_SHIFTER_MODEMASK 0x0700
#define TT_SHIFTER_NUMMODE 0x0008
#define TT_SHIFTER_PALETTE_MASK 0x000f
#define TT_SHIFTER_GRAYMODE 0x1000
/* 256 TT palette registers */
#define TT_PALETTE_BASE (0xffff8400)
#define tt_palette ((volatile u_short *)TT_PALETTE_BASE)
#define TT_PALETTE_RED_MASK 0x0f00
#define TT_PALETTE_GREEN_MASK 0x00f0
#define TT_PALETTE_BLUE_MASK 0x000f
/*
** Falcon030 VIDEL Video Controller
** for description see File 'linux\tools\atari\hardware.txt
*/
#define f030_col ((u_long *) 0xffff9800)
#define f030_xreg ((u_short*) 0xffff8282)
#define f030_yreg ((u_short*) 0xffff82a2)
#define f030_creg ((u_short*) 0xffff82c0)
#define f030_sreg ((u_short*) 0xffff8260)
#define f030_mreg ((u_short*) 0xffff820a)
#define f030_linewidth ((u_short*) 0xffff820e)
#define f030_hscroll ((u_char*) 0xffff8265)
#define VIDEL_BAS (0xffff8260)
struct VIDEL {
u_short st_shift;
u_short pad1;
u_char xoffset_s;
u_char xoffset;
u_short f_shift;
u_char pad2[0x1a];
u_short hht;
u_short hbb;
u_short hbe;
u_short hdb;
u_short hde;
u_short hss;
u_char pad3[0x14];
u_short vft;
u_short vbb;
u_short vbe;
u_short vdb;
u_short vde;
u_short vss;
u_char pad4[0x12];
u_short control;
u_short mode;
};
#define videl ((*(volatile struct VIDEL *)VIDEL_BAS))
/*
** DMA/WD1772 Disk Controller
*/
#define FWD_BAS (0xffff8604)
struct DMA_WD
{
u_short fdc_acces_seccount;
u_short dma_mode_status;
u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */
u_char dma_hi;
u_char char_dummy2;
u_char dma_md;
u_char char_dummy3;
u_char dma_lo;
u_short fdc_speed;
};
# define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS))
/* alias */
#define st_dma dma_wd
/* The two highest bytes of an extended DMA as a short; this is a must
* for the Medusa.
*/
#define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608))
/*
** YM2149 Sound Chip
** access in bytes
*/
#define YM_BAS (0xffff8800)
struct SOUND_YM
{
u_char rd_data_reg_sel;
u_char char_dummy1;
u_char wd_data;
};
#define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS))
/* TT SCSI DMA */
#define TT_SCSI_DMA_BAS (0xffff8700)
struct TT_DMA {
u_char char_dummy0;
u_char dma_addr_hi;
u_char char_dummy1;
u_char dma_addr_hmd;
u_char char_dummy2;
u_char dma_addr_lmd;
u_char char_dummy3;
u_char dma_addr_lo;
u_char char_dummy4;
u_char dma_cnt_hi;
u_char char_dummy5;
u_char dma_cnt_hmd;
u_char char_dummy6;
u_char dma_cnt_lmd;
u_char char_dummy7;
u_char dma_cnt_lo;
u_long dma_restdata;
u_short dma_ctrl;
};
#define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS))
/* TT SCSI Controller 5380 */
#define TT_5380_BAS (0xffff8781)
struct TT_5380 {
u_char scsi_data;
u_char char_dummy1;
u_char scsi_icr;
u_char char_dummy2;
u_char scsi_mode;
u_char char_dummy3;
u_char scsi_tcr;
u_char char_dummy4;
u_char scsi_idstat;
u_char char_dummy5;
u_char scsi_dmastat;
u_char char_dummy6;
u_char scsi_targrcv;
u_char char_dummy7;
u_char scsi_inircv;
};
#define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS))
#define tt_scsi_regp ((volatile char *)TT_5380_BAS)
/*
** Falcon DMA Sound Subsystem
*/
#define MATRIX_BASE (0xffff8930)
struct MATRIX
{
u_short source;
u_short destination;
u_char external_frequency_divider;
u_char internal_frequency_divider;
};
#define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE)
#define CODEC_BASE (0xffff8936)
struct CODEC
{
u_char tracks;
u_char input_source;
#define CODEC_SOURCE_ADC 1
#define CODEC_SOURCE_MATRIX 2
u_char adc_source;
#define ADC_SOURCE_RIGHT_PSG 1
#define ADC_SOURCE_LEFT_PSG 2
u_char gain;
#define CODEC_GAIN_RIGHT 0x0f
#define CODEC_GAIN_LEFT 0xf0
u_char attenuation;
#define CODEC_ATTENUATION_RIGHT 0x0f
#define CODEC_ATTENUATION_LEFT 0xf0
u_char unused1;
u_char status;
#define CODEC_OVERFLOW_RIGHT 1
#define CODEC_OVERFLOW_LEFT 2
u_char unused2, unused3, unused4, unused5;
u_char gpio_directions;
#define GPIO_IN 0
#define GPIO_OUT 1
u_char unused6;
u_char gpio_data;
};
#define falcon_codec (*(volatile struct CODEC *)CODEC_BASE)
/*
** Falcon Blitter
*/
#define BLT_BAS (0xffff8a00)
struct BLITTER
{
u_short halftone[16];
u_short src_x_inc;
u_short src_y_inc;
u_long src_address;
u_short endmask1;
u_short endmask2;
u_short endmask3;
u_short dst_x_inc;
u_short dst_y_inc;
u_long dst_address;
u_short wd_per_line;
u_short ln_per_bb;
u_short hlf_op_reg;
u_short log_op_reg;
u_short lin_nm_reg;
u_short skew_reg;
};
# define blitter ((*(volatile struct BLITTER *)BLT_BAS))
/*
** SCC Z8530
*/
#define SCC_BAS (0xffff8c81)
struct SCC
{
u_char cha_a_ctrl;
u_char char_dummy1;
u_char cha_a_data;
u_char char_dummy2;
u_char cha_b_ctrl;
u_char char_dummy3;
u_char cha_b_data;
};
# define scc ((*(volatile struct SCC*)SCC_BAS))
/* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
# define st_escc ((*(volatile struct SCC*)0xfffffa31))
# define st_escc_dsr ((*(volatile char *)0xfffffa39))
/* TT SCC DMA Controller (same chip as SCSI DMA) */
#define TT_SCC_DMA_BAS (0xffff8c00)
#define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
/*
** VIDEL Palette Register
*/
#define FPL_BAS (0xffff9800)
struct VIDEL_PALETTE
{
u_long reg[256];
};
# define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS))
/*
** Falcon DSP Host Interface
*/
#define DSP56K_HOST_INTERFACE_BASE (0xffffa200)
struct DSP56K_HOST_INTERFACE {
u_char icr;
#define DSP56K_ICR_RREQ 0x01
#define DSP56K_ICR_TREQ 0x02
#define DSP56K_ICR_HF0 0x08
#define DSP56K_ICR_HF1 0x10
#define DSP56K_ICR_HM0 0x20
#define DSP56K_ICR_HM1 0x40
#define DSP56K_ICR_INIT 0x80
u_char cvr;
#define DSP56K_CVR_HV_MASK 0x1f
#define DSP56K_CVR_HC 0x80
u_char isr;
#define DSP56K_ISR_RXDF 0x01
#define DSP56K_ISR_TXDE 0x02
#define DSP56K_ISR_TRDY 0x04
#define DSP56K_ISR_HF2 0x08
#define DSP56K_ISR_HF3 0x10
#define DSP56K_ISR_DMA 0x40
#define DSP56K_ISR_HREQ 0x80
u_char ivr;
union {
u_char b[4];
u_short w[2];
u_long l;
} data;
};
#define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE))
/*
** MFP 68901
*/
#define MFP_BAS (0xfffffa01)
struct MFP
{
u_char par_dt_reg;
u_char char_dummy1;
u_char active_edge;
u_char char_dummy2;
u_char data_dir;
u_char char_dummy3;
u_char int_en_a;
u_char char_dummy4;
u_char int_en_b;
u_char char_dummy5;
u_char int_pn_a;
u_char char_dummy6;
u_char int_pn_b;
u_char char_dummy7;
u_char int_sv_a;
u_char char_dummy8;
u_char int_sv_b;
u_char char_dummy9;
u_char int_mk_a;
u_char char_dummy10;
u_char int_mk_b;
u_char char_dummy11;
u_char vec_adr;
u_char char_dummy12;
u_char tim_ct_a;
u_char char_dummy13;
u_char tim_ct_b;
u_char char_dummy14;
u_char tim_ct_cd;
u_char char_dummy15;
u_char tim_dt_a;
u_char char_dummy16;
u_char tim_dt_b;
u_char char_dummy17;
u_char tim_dt_c;
u_char char_dummy18;
u_char tim_dt_d;
u_char char_dummy19;
u_char sync_char;
u_char char_dummy20;
u_char usart_ctr;
u_char char_dummy21;
u_char rcv_stat;
u_char char_dummy22;
u_char trn_stat;
u_char char_dummy23;
u_char usart_dta;
};
# define mfp ((*(volatile struct MFP*)MFP_BAS))
/* TT's second MFP */
#define TT_MFP_BAS (0xfffffa81)
# define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS))
/* TT System Control Unit */
#define TT_SCU_BAS (0xffff8e01)
struct TT_SCU {
u_char sys_mask;
u_char char_dummy1;
u_char sys_stat;
u_char char_dummy2;
u_char softint;
u_char char_dummy3;
u_char vmeint;
u_char char_dummy4;
u_char gp_reg1;
u_char char_dummy5;
u_char gp_reg2;
u_char char_dummy6;
u_char vme_mask;
u_char char_dummy7;
u_char vme_stat;
};
#define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS))
/* TT real time clock */
#define TT_RTC_BAS (0xffff8961)
struct TT_RTC {
u_char regsel;
u_char dummy;
u_char data;
};
#define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS))
/*
** ACIA 6850
*/
/* constants for the ACIA registers */
/* baudrate selection and reset (Baudrate = clock/factor) */
#define ACIA_DIV1 0
#define ACIA_DIV16 1
#define ACIA_DIV64 2
#define ACIA_RESET 3
/* character format */
#define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */
#define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */
#define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */
#define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */
#define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */
#define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */
#define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */
#define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */
/* transmit control */
#define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */
#define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */
#define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */
#define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */
/* receive control */
#define ACIA_RID (0<<7) /* RxINT disabled */
#define ACIA_RIE (1<<7) /* RxINT enabled */
/* status fields of the ACIA */
#define ACIA_RDRF 1 /* Receive Data Register Full */
#define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */
#define ACIA_DCD (1<<2) /* Data Carrier Detect */
#define ACIA_CTS (1<<3) /* Clear To Send */
#define ACIA_FE (1<<4) /* Framing Error */
#define ACIA_OVRN (1<<5) /* Receiver Overrun */
#define ACIA_PE (1<<6) /* Parity Error */
#define ACIA_IRQ (1<<7) /* Interrupt Request */
#define ACIA_BAS (0xfffffc00)
struct ACIA
{
u_char key_ctrl;
u_char char_dummy1;
u_char key_data;
u_char char_dummy2;
u_char mid_ctrl;
u_char char_dummy3;
u_char mid_data;
};
# define acia ((*(volatile struct ACIA*)ACIA_BAS))
#define TT_DMASND_BAS (0xffff8900)
struct TT_DMASND {
u_char int_ctrl; /* Falcon: Interrupt control */
u_char ctrl;
u_char pad2;
u_char bas_hi;
u_char pad3;
u_char bas_mid;
u_char pad4;
u_char bas_low;
u_char pad5;
u_char addr_hi;
u_char pad6;
u_char addr_mid;
u_char pad7;
u_char addr_low;
u_char pad8;
u_char end_hi;
u_char pad9;
u_char end_mid;
u_char pad10;
u_char end_low;
u_char pad11[12];
u_char track_select; /* Falcon */
u_char mode;
u_char pad12[14];
/* Falcon only: */
u_short cbar_src;
u_short cbar_dst;
u_char ext_div;
u_char int_div;
u_char rec_track_select;
u_char dac_src;
u_char adc_src;
u_char input_gain;
u_short output_atten;
};
# define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
#define DMASND_MFP_INT_REPLAY 0x01
#define DMASND_MFP_INT_RECORD 0x02
#define DMASND_TIMERA_INT_REPLAY 0x04
#define DMASND_TIMERA_INT_RECORD 0x08
#define DMASND_CTRL_OFF 0x00
#define DMASND_CTRL_ON 0x01
#define DMASND_CTRL_REPEAT 0x02
#define DMASND_CTRL_RECORD_ON 0x10
#define DMASND_CTRL_RECORD_OFF 0x00
#define DMASND_CTRL_RECORD_REPEAT 0x20
#define DMASND_CTRL_SELECT_REPLAY 0x00
#define DMASND_CTRL_SELECT_RECORD 0x80
#define DMASND_MODE_MONO 0x80
#define DMASND_MODE_STEREO 0x00
#define DMASND_MODE_8BIT 0x00
#define DMASND_MODE_16BIT 0x40 /* Falcon only */
#define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */
#define DMASND_MODE_12KHZ 0x01
#define DMASND_MODE_25KHZ 0x02
#define DMASND_MODE_50KHZ 0x03
#define DMASNDSetBase(bufstart) \
do { \
tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \
tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \
tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \
} while( 0 )
#define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \
(tt_dmasnd.addr_mid << 8) + \
(tt_dmasnd.addr_low))
#define DMASNDSetEnd(bufend) \
do { \
tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \
tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \
tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \
} while( 0 )
#define TT_MICROWIRE_BAS (0xffff8922)
struct TT_MICROWIRE {
u_short data;
u_short mask;
};
# define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS))
#define MW_LM1992_ADDR 0x0400
#define MW_LM1992_VOLUME(dB) \
(0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2)))
#define MW_LM1992_BALLEFT(dB) \
(0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
#define MW_LM1992_BALRIGHT(dB) \
(0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
#define MW_LM1992_TREBLE(dB) \
(0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
#define MW_LM1992_BASS(dB) \
(0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
#define MW_LM1992_PSG_LOW 0x000
#define MW_LM1992_PSG_HIGH 0x001
#define MW_LM1992_PSG_OFF 0x002
#define MSTE_RTC_BAS (0xfffffc21)
struct MSTE_RTC {
u_char sec_ones;
u_char dummy1;
u_char sec_tens;
u_char dummy2;
u_char min_ones;
u_char dummy3;
u_char min_tens;
u_char dummy4;
u_char hr_ones;
u_char dummy5;
u_char hr_tens;
u_char dummy6;
u_char weekday;
u_char dummy7;
u_char day_ones;
u_char dummy8;
u_char day_tens;
u_char dummy9;
u_char mon_ones;
u_char dummy10;
u_char mon_tens;
u_char dummy11;
u_char year_ones;
u_char dummy12;
u_char year_tens;
u_char dummy13;
u_char mode;
u_char dummy14;
u_char test;
u_char dummy15;
u_char reset;
};
#define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
#endif /* linux/atarihw.h */

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/*
** atariints.h -- Atari Linux interrupt handling structs and prototypes
**
** Copyright 1994 by Björn Brauel
**
** 5/2/94 Roman Hodek:
** TT interrupt definitions added.
**
** 12/02/96: (Roman)
** Adapted to new int handling scheme (see ataints.c); revised numbering
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _LINUX_ATARIINTS_H_
#define _LINUX_ATARIINTS_H_
#include <asm/irq.h>
#include <asm/atarihw.h>
/*
** Atari Interrupt sources.
**
*/
#define STMFP_SOURCE_BASE 8
#define TTMFP_SOURCE_BASE 24
#define SCC_SOURCE_BASE 40
#define VME_SOURCE_BASE 56
#define VME_MAX_SOURCES 16
#define NUM_ATARI_SOURCES (VME_SOURCE_BASE+VME_MAX_SOURCES-STMFP_SOURCE_BASE)
/* convert vector number to int source number */
#define IRQ_VECTOR_TO_SOURCE(v) ((v) - ((v) < 0x20 ? 0x18 : (0x40-8)))
/* convert irq_handler index to vector number */
#define IRQ_SOURCE_TO_VECTOR(i) ((i) + ((i) < 8 ? 0x18 : (0x40-8)))
/* interrupt service types */
#define IRQ_TYPE_SLOW 0
#define IRQ_TYPE_FAST 1
#define IRQ_TYPE_PRIO 2
/* ST-MFP interrupts */
#define IRQ_MFP_BUSY (8)
#define IRQ_MFP_DCD (9)
#define IRQ_MFP_CTS (10)
#define IRQ_MFP_GPU (11)
#define IRQ_MFP_TIMD (12)
#define IRQ_MFP_TIMC (13)
#define IRQ_MFP_ACIA (14)
#define IRQ_MFP_FDC (15)
#define IRQ_MFP_ACSI IRQ_MFP_FDC
#define IRQ_MFP_FSCSI IRQ_MFP_FDC
#define IRQ_MFP_IDE IRQ_MFP_FDC
#define IRQ_MFP_TIMB (16)
#define IRQ_MFP_SERERR (17)
#define IRQ_MFP_SEREMPT (18)
#define IRQ_MFP_RECERR (19)
#define IRQ_MFP_RECFULL (20)
#define IRQ_MFP_TIMA (21)
#define IRQ_MFP_RI (22)
#define IRQ_MFP_MMD (23)
/* TT-MFP interrupts */
#define IRQ_TT_MFP_IO0 (24)
#define IRQ_TT_MFP_IO1 (25)
#define IRQ_TT_MFP_SCC (26)
#define IRQ_TT_MFP_RI (27)
#define IRQ_TT_MFP_TIMD (28)
#define IRQ_TT_MFP_TIMC (29)
#define IRQ_TT_MFP_DRVRDY (30)
#define IRQ_TT_MFP_SCSIDMA (31)
#define IRQ_TT_MFP_TIMB (32)
#define IRQ_TT_MFP_SERERR (33)
#define IRQ_TT_MFP_SEREMPT (34)
#define IRQ_TT_MFP_RECERR (35)
#define IRQ_TT_MFP_RECFULL (36)
#define IRQ_TT_MFP_TIMA (37)
#define IRQ_TT_MFP_RTC (38)
#define IRQ_TT_MFP_SCSI (39)
/* SCC interrupts */
#define IRQ_SCCB_TX (40)
#define IRQ_SCCB_STAT (42)
#define IRQ_SCCB_RX (44)
#define IRQ_SCCB_SPCOND (46)
#define IRQ_SCCA_TX (48)
#define IRQ_SCCA_STAT (50)
#define IRQ_SCCA_RX (52)
#define IRQ_SCCA_SPCOND (54)
#define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
#define INT_TICKS 246 /* to make sched_time = 99.902... HZ */
#define MFP_ENABLE 0
#define MFP_PENDING 1
#define MFP_SERVICE 2
#define MFP_MASK 3
/* Utility functions for setting/clearing bits in the interrupt registers of
* the MFP. 'type' should be constant, if 'irq' is constant, too, code size is
* reduced. set_mfp_bit() is nonsense for PENDING and SERVICE registers. */
static inline int get_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
mask = 1 << (irq & 7);
reg = (unsigned char *)&mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
return( *reg & mask );
}
static inline void set_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
mask = 1 << (irq & 7);
reg = (unsigned char *)&mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
__asm__ __volatile__ ( "orb %0,%1"
: : "di" (mask), "m" (*reg) : "memory" );
}
static inline void clear_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
mask = ~(1 << (irq & 7));
reg = (unsigned char *)&mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
if (type == MFP_PENDING || type == MFP_SERVICE)
__asm__ __volatile__ ( "moveb %0,%1"
: : "di" (mask), "m" (*reg) : "memory" );
else
__asm__ __volatile__ ( "andb %0,%1"
: : "di" (mask), "m" (*reg) : "memory" );
}
/*
* {en,dis}able_irq have the usual semantics of temporary blocking the
* interrupt, but not loosing requests that happen between disabling and
* enabling. This is done with the MFP mask registers.
*/
static inline void atari_enable_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
set_mfp_bit( irq, MFP_MASK );
}
static inline void atari_disable_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
clear_mfp_bit( irq, MFP_MASK );
}
/*
* In opposite to {en,dis}able_irq, requests between turn{off,on}_irq are not
* "stored"
*/
static inline void atari_turnon_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
set_mfp_bit( irq, MFP_ENABLE );
}
static inline void atari_turnoff_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
clear_mfp_bit( irq, MFP_ENABLE );
clear_mfp_bit( irq, MFP_PENDING );
}
static inline void atari_clear_pending_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
clear_mfp_bit( irq, MFP_PENDING );
}
static inline int atari_irq_pending( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return( 0 );
return( get_mfp_bit( irq, MFP_PENDING ) );
}
unsigned long atari_register_vme_int( void );
void atari_unregister_vme_int( unsigned long );
#endif /* linux/atariints.h */

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/*
** atarikb.h -- This header contains the prototypes of functions of
** the intelligent keyboard of the Atari needed by the
** mouse and joystick drivers.
**
** Copyright 1994 by Robert de Vries
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 20 Feb 1994 by Robert de Vries
*/
#ifndef _LINUX_ATARIKB_H
#define _LINUX_ATARIKB_H
void ikbd_write(const char *, int);
void ikbd_mouse_button_action(int mode);
void ikbd_mouse_rel_pos(void);
void ikbd_mouse_abs_pos(int xmax, int ymax);
void ikbd_mouse_kbd_mode(int dx, int dy);
void ikbd_mouse_thresh(int x, int y);
void ikbd_mouse_scale(int x, int y);
void ikbd_mouse_pos_get(int *x, int *y);
void ikbd_mouse_pos_set(int x, int y);
void ikbd_mouse_y0_bot(void);
void ikbd_mouse_y0_top(void);
void ikbd_mouse_disable(void);
void ikbd_joystick_event_on(void);
void ikbd_joystick_event_off(void);
void ikbd_joystick_get_state(void);
void ikbd_joystick_disable(void);
/* Hook for MIDI serial driver */
extern void (*atari_MIDI_interrupt_hook) (void);
/* Hook for mouse driver */
extern void (*atari_mouse_interrupt_hook) (char *);
/* Hook for keyboard inputdev driver */
extern void (*atari_input_keyboard_interrupt_hook) (unsigned char, char);
/* Hook for mouse inputdev driver */
extern void (*atari_input_mouse_interrupt_hook) (char *);
int atari_keyb_init(void);
#endif /* _LINUX_ATARIKB_H */

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#ifdef __uClinux__
#include "atomic_no.h"
#else
#include "atomic_mm.h"
#endif

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#ifndef __ARCH_M68K_ATOMIC__
#define __ARCH_M68K_ATOMIC__
#include <linux/types.h>
#include <asm/system.h>
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*/
/*
* We do not have SMP m68k systems, so we don't have to deal with that.
*/
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) ((v)->counter)
#define atomic_set(v, i) (((v)->counter) = i)
static inline void atomic_add(int i, atomic_t *v)
{
__asm__ __volatile__("addl %1,%0" : "+m" (*v) : "id" (i));
}
static inline void atomic_sub(int i, atomic_t *v)
{
__asm__ __volatile__("subl %1,%0" : "+m" (*v) : "id" (i));
}
static inline void atomic_inc(atomic_t *v)
{
__asm__ __volatile__("addql #1,%0" : "+m" (*v));
}
static inline void atomic_dec(atomic_t *v)
{
__asm__ __volatile__("subql #1,%0" : "+m" (*v));
}
static inline int atomic_dec_and_test(atomic_t *v)
{
char c;
__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
return c != 0;
}
static inline int atomic_inc_and_test(atomic_t *v)
{
char c;
__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
return c != 0;
}
#ifdef CONFIG_RMW_INSNS
static inline int atomic_add_return(int i, atomic_t *v)
{
int t, tmp;
__asm__ __volatile__(
"1: movel %2,%1\n"
" addl %3,%1\n"
" casl %2,%1,%0\n"
" jne 1b"
: "+m" (*v), "=&d" (t), "=&d" (tmp)
: "g" (i), "2" (atomic_read(v)));
return t;
}
static inline int atomic_sub_return(int i, atomic_t *v)
{
int t, tmp;
__asm__ __volatile__(
"1: movel %2,%1\n"
" subl %3,%1\n"
" casl %2,%1,%0\n"
" jne 1b"
: "+m" (*v), "=&d" (t), "=&d" (tmp)
: "g" (i), "2" (atomic_read(v)));
return t;
}
#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
#else /* !CONFIG_RMW_INSNS */
static inline int atomic_add_return(int i, atomic_t * v)
{
unsigned long flags;
int t;
local_irq_save(flags);
t = atomic_read(v);
t += i;
atomic_set(v, t);
local_irq_restore(flags);
return t;
}
static inline int atomic_sub_return(int i, atomic_t * v)
{
unsigned long flags;
int t;
local_irq_save(flags);
t = atomic_read(v);
t -= i;
atomic_set(v, t);
local_irq_restore(flags);
return t;
}
static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
{
unsigned long flags;
int prev;
local_irq_save(flags);
prev = atomic_read(v);
if (prev == old)
atomic_set(v, new);
local_irq_restore(flags);
return prev;
}
static inline int atomic_xchg(atomic_t *v, int new)
{
unsigned long flags;
int prev;
local_irq_save(flags);
prev = atomic_read(v);
atomic_set(v, new);
local_irq_restore(flags);
return prev;
}
#endif /* !CONFIG_RMW_INSNS */
#define atomic_dec_return(v) atomic_sub_return(1, (v))
#define atomic_inc_return(v) atomic_add_return(1, (v))
static inline int atomic_sub_and_test(int i, atomic_t *v)
{
char c;
__asm__ __volatile__("subl %2,%1; seq %0" : "=d" (c), "+m" (*v): "g" (i));
return c != 0;
}
static inline int atomic_add_negative(int i, atomic_t *v)
{
char c;
__asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "+m" (*v): "g" (i));
return c != 0;
}
static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
{
__asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask)));
}
static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
{
__asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask));
}
static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
{
int c, old;
c = atomic_read(v);
for (;;) {
if (unlikely(c == (u)))
break;
old = atomic_cmpxchg((v), c, c + (a));
if (likely(old == c))
break;
c = old;
}
return c != (u);
}
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
/* Atomic operations are already serializing */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_dec() barrier()
#define smp_mb__before_atomic_inc() barrier()
#define smp_mb__after_atomic_inc() barrier()
#include <asm-generic/atomic.h>
#endif /* __ARCH_M68K_ATOMIC __ */

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#ifndef __ARCH_M68KNOMMU_ATOMIC__
#define __ARCH_M68KNOMMU_ATOMIC__
#include <linux/types.h>
#include <asm/system.h>
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*/
/*
* We do not have SMP m68k systems, so we don't have to deal with that.
*/
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) ((v)->counter)
#define atomic_set(v, i) (((v)->counter) = i)
static __inline__ void atomic_add(int i, atomic_t *v)
{
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__("addl %1,%0" : "+m" (*v) : "d" (i));
#else
__asm__ __volatile__("addl %1,%0" : "+m" (*v) : "di" (i));
#endif
}
static __inline__ void atomic_sub(int i, atomic_t *v)
{
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__("subl %1,%0" : "+m" (*v) : "d" (i));
#else
__asm__ __volatile__("subl %1,%0" : "+m" (*v) : "di" (i));
#endif
}
static __inline__ int atomic_sub_and_test(int i, atomic_t * v)
{
char c;
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__("subl %2,%1; seq %0"
: "=d" (c), "+m" (*v)
: "d" (i));
#else
__asm__ __volatile__("subl %2,%1; seq %0"
: "=d" (c), "+m" (*v)
: "di" (i));
#endif
return c != 0;
}
static __inline__ void atomic_inc(volatile atomic_t *v)
{
__asm__ __volatile__("addql #1,%0" : "+m" (*v));
}
/*
* atomic_inc_and_test - increment and test
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1
* and returns true if the result is zero, or false for all
* other cases.
*/
static __inline__ int atomic_inc_and_test(volatile atomic_t *v)
{
char c;
__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
return c != 0;
}
static __inline__ void atomic_dec(volatile atomic_t *v)
{
__asm__ __volatile__("subql #1,%0" : "+m" (*v));
}
static __inline__ int atomic_dec_and_test(volatile atomic_t *v)
{
char c;
__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
return c != 0;
}
static __inline__ void atomic_clear_mask(unsigned long mask, unsigned long *v)
{
__asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask)));
}
static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v)
{
__asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask));
}
/* Atomic operations are already serializing */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_dec() barrier()
#define smp_mb__before_atomic_inc() barrier()
#define smp_mb__after_atomic_inc() barrier()
static inline int atomic_add_return(int i, atomic_t * v)
{
unsigned long temp, flags;
local_irq_save(flags);
temp = *(long *)v;
temp += i;
*(long *)v = temp;
local_irq_restore(flags);
return temp;
}
#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
static inline int atomic_sub_return(int i, atomic_t * v)
{
unsigned long temp, flags;
local_irq_save(flags);
temp = *(long *)v;
temp -= i;
*(long *)v = temp;
local_irq_restore(flags);
return temp;
}
#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
{
int c, old;
c = atomic_read(v);
for (;;) {
if (unlikely(c == (u)))
break;
old = atomic_cmpxchg((v), c, c + (a));
if (likely(old == c))
break;
c = old;
}
return c != (u);
}
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
#define atomic_dec_return(v) atomic_sub_return(1,(v))
#define atomic_inc_return(v) atomic_add_return(1,(v))
#include <asm-generic/atomic.h>
#endif /* __ARCH_M68KNOMMU_ATOMIC __ */

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#ifndef __ASMm68k_AUXVEC_H
#define __ASMm68k_AUXVEC_H
#endif

5
arch/m68k/include/asm/bitops.h Normal file
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#ifdef __uClinux__
#include "bitops_no.h"
#else
#include "bitops_mm.h"
#endif

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#ifndef _M68K_BITOPS_H
#define _M68K_BITOPS_H
/*
* Copyright 1992, Linus Torvalds.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
#include <linux/compiler.h>
/*
* Require 68020 or better.
*
* They use the standard big-endian m680x0 bit ordering.
*/
#define test_and_set_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_test_and_set_bit(nr, vaddr) : \
__generic_test_and_set_bit(nr, vaddr))
#define __test_and_set_bit(nr,vaddr) test_and_set_bit(nr,vaddr)
static inline int __constant_test_and_set_bit(int nr, unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bset %2,%1; sne %0"
: "=d" (retval), "+m" (*p)
: "di" (nr & 7));
return retval;
}
static inline int __generic_test_and_set_bit(int nr, unsigned long *vaddr)
{
char retval;
__asm__ __volatile__ ("bfset %2{%1:#1}; sne %0"
: "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory");
return retval;
}
#define set_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_set_bit(nr, vaddr) : \
__generic_set_bit(nr, vaddr))
#define __set_bit(nr,vaddr) set_bit(nr,vaddr)
static inline void __constant_set_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bset %1,%0"
: "+m" (*p) : "di" (nr & 7));
}
static inline void __generic_set_bit(int nr, volatile unsigned long *vaddr)
{
__asm__ __volatile__ ("bfset %1{%0:#1}"
: : "d" (nr^31), "o" (*vaddr) : "memory");
}
#define test_and_clear_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_test_and_clear_bit(nr, vaddr) : \
__generic_test_and_clear_bit(nr, vaddr))
#define __test_and_clear_bit(nr,vaddr) test_and_clear_bit(nr,vaddr)
static inline int __constant_test_and_clear_bit(int nr, unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bclr %2,%1; sne %0"
: "=d" (retval), "+m" (*p)
: "di" (nr & 7));
return retval;
}
static inline int __generic_test_and_clear_bit(int nr, unsigned long *vaddr)
{
char retval;
__asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0"
: "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory");
return retval;
}
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
#define clear_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_clear_bit(nr, vaddr) : \
__generic_clear_bit(nr, vaddr))
#define __clear_bit(nr,vaddr) clear_bit(nr,vaddr)
static inline void __constant_clear_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bclr %1,%0"
: "+m" (*p) : "di" (nr & 7));
}
static inline void __generic_clear_bit(int nr, volatile unsigned long *vaddr)
{
__asm__ __volatile__ ("bfclr %1{%0:#1}"
: : "d" (nr^31), "o" (*vaddr) : "memory");
}
#define test_and_change_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_test_and_change_bit(nr, vaddr) : \
__generic_test_and_change_bit(nr, vaddr))
#define __test_and_change_bit(nr,vaddr) test_and_change_bit(nr,vaddr)
#define __change_bit(nr,vaddr) change_bit(nr,vaddr)
static inline int __constant_test_and_change_bit(int nr, unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bchg %2,%1; sne %0"
: "=d" (retval), "+m" (*p)
: "di" (nr & 7));
return retval;
}
static inline int __generic_test_and_change_bit(int nr, unsigned long *vaddr)
{
char retval;
__asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0"
: "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory");
return retval;
}
#define change_bit(nr,vaddr) \
(__builtin_constant_p(nr) ? \
__constant_change_bit(nr, vaddr) : \
__generic_change_bit(nr, vaddr))
static inline void __constant_change_bit(int nr, unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bchg %1,%0"
: "+m" (*p) : "di" (nr & 7));
}
static inline void __generic_change_bit(int nr, unsigned long *vaddr)
{
__asm__ __volatile__ ("bfchg %1{%0:#1}"
: : "d" (nr^31), "o" (*vaddr) : "memory");
}
static inline int test_bit(int nr, const unsigned long *vaddr)
{
return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
}
static inline int find_first_zero_bit(const unsigned long *vaddr,
unsigned size)
{
const unsigned long *p = vaddr;
int res = 32;
unsigned long num;
if (!size)
return 0;
size = (size + 31) >> 5;
while (!(num = ~*p++)) {
if (!--size)
goto out;
}
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
res ^= 31;
out:
return ((long)p - (long)vaddr - 4) * 8 + res;
}
static inline int find_next_zero_bit(const unsigned long *vaddr, int size,
int offset)
{
const unsigned long *p = vaddr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
unsigned long num = ~*p++ & (~0UL << bit);
offset -= bit;
/* Look for zero in first longword */
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
if (res < 32)
return offset + (res ^ 31);
offset += 32;
}
/* No zero yet, search remaining full bytes for a zero */
res = find_first_zero_bit(p, size - ((long)p - (long)vaddr) * 8);
return offset + res;
}
static inline int find_first_bit(const unsigned long *vaddr, unsigned size)
{
const unsigned long *p = vaddr;
int res = 32;
unsigned long num;
if (!size)
return 0;
size = (size + 31) >> 5;
while (!(num = *p++)) {
if (!--size)
goto out;
}
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
res ^= 31;
out:
return ((long)p - (long)vaddr - 4) * 8 + res;
}
static inline int find_next_bit(const unsigned long *vaddr, int size,
int offset)
{
const unsigned long *p = vaddr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
unsigned long num = *p++ & (~0UL << bit);
offset -= bit;
/* Look for one in first longword */
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
if (res < 32)
return offset + (res ^ 31);
offset += 32;
}
/* No one yet, search remaining full bytes for a one */
res = find_first_bit(p, size - ((long)p - (long)vaddr) * 8);
return offset + res;
}
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
*/
static inline unsigned long ffz(unsigned long word)
{
int res;
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (~word & -~word));
return res ^ 31;
}
#ifdef __KERNEL__
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
static inline int ffs(int x)
{
int cnt;
asm ("bfffo %1{#0:#0},%0" : "=d" (cnt) : "dm" (x & -x));
return 32 - cnt;
}
#define __ffs(x) (ffs(x) - 1)
/*
* fls: find last bit set.
*/
static inline int fls(int x)
{
int cnt;
asm ("bfffo %1{#0,#0},%0" : "=d" (cnt) : "dm" (x));
return 32 - cnt;
}
static inline int __fls(int x)
{
return fls(x) - 1;
}
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
/* Bitmap functions for the minix filesystem */
static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size)
{
const unsigned short *p = vaddr, *addr = vaddr;
int res;
unsigned short num;
if (!size)
return 0;
size = (size >> 4) + ((size & 15) > 0);
while (*p++ == 0xffff)
{
if (--size == 0)
return (p - addr) << 4;
}
num = ~*--p;
__asm__ __volatile__ ("bfffo %1{#16,#16},%0"
: "=d" (res) : "d" (num & -num));
return ((p - addr) << 4) + (res ^ 31);
}
#define minix_test_and_set_bit(nr, addr) __test_and_set_bit((nr) ^ 16, (unsigned long *)(addr))
#define minix_set_bit(nr,addr) __set_bit((nr) ^ 16, (unsigned long *)(addr))
#define minix_test_and_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr))
static inline int minix_test_bit(int nr, const void *vaddr)
{
const unsigned short *p = vaddr;
return (p[nr >> 4] & (1U << (nr & 15))) != 0;
}
/* Bitmap functions for the ext2 filesystem. */
#define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 24, (unsigned long *)(addr))
#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, (unsigned long *)(addr))
#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr))
#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr))
static inline int ext2_test_bit(int nr, const void *vaddr)
{
const unsigned char *p = vaddr;
return (p[nr >> 3] & (1U << (nr & 7))) != 0;
}
static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size)
{
const unsigned long *p = vaddr, *addr = vaddr;
int res;
if (!size)
return 0;
size = (size >> 5) + ((size & 31) > 0);
while (*p++ == ~0UL)
{
if (--size == 0)
return (p - addr) << 5;
}
--p;
for (res = 0; res < 32; res++)
if (!ext2_test_bit (res, p))
break;
return (p - addr) * 32 + res;
}
static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size,
unsigned offset)
{
const unsigned long *addr = vaddr;
const unsigned long *p = addr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
/* Look for zero in first longword */
for (res = bit; res < 32; res++)
if (!ext2_test_bit (res, p))
return (p - addr) * 32 + res;
p++;
}
/* No zero yet, search remaining full bytes for a zero */
res = ext2_find_first_zero_bit (p, size - 32 * (p - addr));
return (p - addr) * 32 + res;
}
static inline int ext2_find_first_bit(const void *vaddr, unsigned size)
{
const unsigned long *p = vaddr, *addr = vaddr;
int res;
if (!size)
return 0;
size = (size >> 5) + ((size & 31) > 0);
while (*p++ == 0UL) {
if (--size == 0)
return (p - addr) << 5;
}
--p;
for (res = 0; res < 32; res++)
if (ext2_test_bit(res, p))
break;
return (p - addr) * 32 + res;
}
static inline int ext2_find_next_bit(const void *vaddr, unsigned size,
unsigned offset)
{
const unsigned long *addr = vaddr;
const unsigned long *p = addr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
/* Look for one in first longword */
for (res = bit; res < 32; res++)
if (ext2_test_bit(res, p))
return (p - addr) * 32 + res;
p++;
}
/* No set bit yet, search remaining full bytes for a set bit */
res = ext2_find_first_bit(p, size - 32 * (p - addr));
return (p - addr) * 32 + res;
}
#endif /* __KERNEL__ */
#endif /* _M68K_BITOPS_H */

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#ifndef _M68KNOMMU_BITOPS_H
#define _M68KNOMMU_BITOPS_H
/*
* Copyright 1992, Linus Torvalds.
*/
#include <linux/compiler.h>
#include <asm/byteorder.h> /* swab32 */
#ifdef __KERNEL__
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
#if defined (__mcfisaaplus__) || defined (__mcfisac__)
static inline int ffs(unsigned int val)
{
if (!val)
return 0;
asm volatile(
"bitrev %0\n\t"
"ff1 %0\n\t"
: "=d" (val)
: "0" (val)
);
val++;
return val;
}
static inline int __ffs(unsigned int val)
{
asm volatile(
"bitrev %0\n\t"
"ff1 %0\n\t"
: "=d" (val)
: "0" (val)
);
return val;
}
#else
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/__ffs.h>
#endif
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/ffz.h>
static __inline__ void set_bit(int nr, volatile unsigned long * addr)
{
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__ ("lea %0,%%a0; bset %1,(%%a0)"
: "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "d" (nr)
: "%a0", "cc");
#else
__asm__ __volatile__ ("bset %1,%0"
: "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "di" (nr)
: "cc");
#endif
}
#define __set_bit(nr, addr) set_bit(nr, addr)
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
{
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__ ("lea %0,%%a0; bclr %1,(%%a0)"
: "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "d" (nr)
: "%a0", "cc");
#else
__asm__ __volatile__ ("bclr %1,%0"
: "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "di" (nr)
: "cc");
#endif
}
#define __clear_bit(nr, addr) clear_bit(nr, addr)
static __inline__ void change_bit(int nr, volatile unsigned long * addr)
{
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__ ("lea %0,%%a0; bchg %1,(%%a0)"
: "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "d" (nr)
: "%a0", "cc");
#else
__asm__ __volatile__ ("bchg %1,%0"
: "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "di" (nr)
: "cc");
#endif
}
#define __change_bit(nr, addr) change_bit(nr, addr)
static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
{
char retval;
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "d" (nr)
: "%a0");
#else
__asm__ __volatile__ ("bset %2,%1; sne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "di" (nr)
/* No clobber */);
#endif
return retval;
}
#define __test_and_set_bit(nr, addr) test_and_set_bit(nr, addr)
static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
{
char retval;
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "d" (nr)
: "%a0");
#else
__asm__ __volatile__ ("bclr %2,%1; sne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "di" (nr)
/* No clobber */);
#endif
return retval;
}
#define __test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr)
static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
{
char retval;
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__ ("lea %1,%%a0\n\tbchg %2,(%%a0)\n\tsne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "d" (nr)
: "%a0");
#else
__asm__ __volatile__ ("bchg %2,%1; sne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
: "di" (nr)
/* No clobber */);
#endif
return retval;
}
#define __test_and_change_bit(nr, addr) test_and_change_bit(nr, addr)
/*
* This routine doesn't need to be atomic.
*/
static __inline__ int __constant_test_bit(int nr, const volatile unsigned long * addr)
{
return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
}
static __inline__ int __test_bit(int nr, const volatile unsigned long * addr)
{
int * a = (int *) addr;
int mask;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
return ((mask & *a) != 0);
}
#define test_bit(nr,addr) \
(__builtin_constant_p(nr) ? \
__constant_test_bit((nr),(addr)) : \
__test_bit((nr),(addr)))
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
static __inline__ int ext2_set_bit(int nr, volatile void * addr)
{
char retval;
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
: "d" (nr)
: "%a0");
#else
__asm__ __volatile__ ("bset %2,%1; sne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
: "di" (nr)
/* No clobber */);
#endif
return retval;
}
static __inline__ int ext2_clear_bit(int nr, volatile void * addr)
{
char retval;
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
: "d" (nr)
: "%a0");
#else
__asm__ __volatile__ ("bclr %2,%1; sne %0"
: "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
: "di" (nr)
/* No clobber */);
#endif
return retval;
}
#define ext2_set_bit_atomic(lock, nr, addr) \
({ \
int ret; \
spin_lock(lock); \
ret = ext2_set_bit((nr), (addr)); \
spin_unlock(lock); \
ret; \
})
#define ext2_clear_bit_atomic(lock, nr, addr) \
({ \
int ret; \
spin_lock(lock); \
ret = ext2_clear_bit((nr), (addr)); \
spin_unlock(lock); \
ret; \
})
static __inline__ int ext2_test_bit(int nr, const volatile void * addr)
{
char retval;
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__ ("lea %1,%%a0; btst %2,(%%a0); sne %0"
: "=d" (retval)
: "m" (((const volatile char *)addr)[nr >> 3]), "d" (nr)
: "%a0");
#else
__asm__ __volatile__ ("btst %2,%1; sne %0"
: "=d" (retval)
: "m" (((const volatile char *)addr)[nr >> 3]), "di" (nr)
/* No clobber */);
#endif
return retval;
}
#define ext2_find_first_zero_bit(addr, size) \
ext2_find_next_zero_bit((addr), (size), 0)
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if(offset) {
/* We hold the little endian value in tmp, but then the
* shift is illegal. So we could keep a big endian value
* in tmp, like this:
*
* tmp = __swab32(*(p++));
* tmp |= ~0UL >> (32-offset);
*
* but this would decrease performance, so we change the
* shift:
*/
tmp = *(p++);
tmp |= __swab32(~0UL >> (32-offset));
if(size < 32)
goto found_first;
if(~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while(size & ~31UL) {
if(~(tmp = *(p++)))
goto found_middle;
result += 32;
size -= 32;
}
if(!size)
return result;
tmp = *p;
found_first:
/* tmp is little endian, so we would have to swab the shift,
* see above. But then we have to swab tmp below for ffz, so
* we might as well do this here.
*/
return result + ffz(__swab32(tmp) | (~0UL << size));
found_middle:
return result + ffz(__swab32(tmp));
}
#define ext2_find_next_bit(addr, size, off) \
generic_find_next_le_bit((unsigned long *)(addr), (size), (off))
#include <asm-generic/bitops/minix.h>
#endif /* __KERNEL__ */
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls64.h>
#endif /* _M68KNOMMU_BITOPS_H */

32
arch/m68k/include/asm/blinken.h Normal file
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/*
** asm/blinken.h -- m68k blinkenlights support (currently hp300 only)
**
** (c) 1998 Phil Blundell <philb@gnu.org>
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _M68K_BLINKEN_H
#define _M68K_BLINKEN_H
#include <asm/setup.h>
#include <asm/io.h>
#define HP300_LEDS 0xf001ffff
extern unsigned char ledstate;
static __inline__ void blinken_leds(int on, int off)
{
if (MACH_IS_HP300)
{
ledstate |= on;
ledstate &= ~off;
out_8(HP300_LEDS, ~ledstate);
}
}
#endif

5
arch/m68k/include/asm/bootinfo.h Normal file
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#ifdef __uClinux__
#include "bootinfo_no.h"
#else
#include "bootinfo_mm.h"
#endif

378
arch/m68k/include/asm/bootinfo_mm.h Normal file
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/*
** asm/bootinfo.h -- Definition of the Linux/m68k boot information structure
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created 09/29/92 by Greg Harp
**
** 5/2/94 Roman Hodek:
** Added bi_atari part of the machine dependent union bi_un; for now it
** contains just a model field to distinguish between TT and Falcon.
** 26/7/96 Roman Zippel:
** Renamed to setup.h; added some useful macros to allow gcc some
** optimizations if possible.
** 5/10/96 Geert Uytterhoeven:
** Redesign of the boot information structure; renamed to bootinfo.h again
** 27/11/96 Geert Uytterhoeven:
** Backwards compatibility with bootinfo interface version 1.0
*/
#ifndef _M68K_BOOTINFO_H
#define _M68K_BOOTINFO_H
/*
* Bootinfo definitions
*
* This is an easily parsable and extendable structure containing all
* information to be passed from the bootstrap to the kernel.
*
* This way I hope to keep all future changes back/forewards compatible.
* Thus, keep your fingers crossed...
*
* This structure is copied right after the kernel bss by the bootstrap
* routine.
*/
#ifndef __ASSEMBLY__
struct bi_record {
unsigned short tag; /* tag ID */
unsigned short size; /* size of record (in bytes) */
unsigned long data[0]; /* data */
};
#endif /* __ASSEMBLY__ */
/*
* Tag Definitions
*
* Machine independent tags start counting from 0x0000
* Machine dependent tags start counting from 0x8000
*/
#define BI_LAST 0x0000 /* last record (sentinel) */
#define BI_MACHTYPE 0x0001 /* machine type (u_long) */
#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */
#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */
#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */
#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */
/* (struct mem_info) */
#define BI_RAMDISK 0x0006 /* ramdisk address and size */
/* (struct mem_info) */
#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */
/* (string) */
/*
* Amiga-specific tags
*/
#define BI_AMIGA_MODEL 0x8000 /* model (u_long) */
#define BI_AMIGA_AUTOCON 0x8001 /* AutoConfig device */
/* (struct ConfigDev) */
#define BI_AMIGA_CHIP_SIZE 0x8002 /* size of Chip RAM (u_long) */
#define BI_AMIGA_VBLANK 0x8003 /* VBLANK frequency (u_char) */
#define BI_AMIGA_PSFREQ 0x8004 /* power supply frequency (u_char) */
#define BI_AMIGA_ECLOCK 0x8005 /* EClock frequency (u_long) */
#define BI_AMIGA_CHIPSET 0x8006 /* native chipset present (u_long) */
#define BI_AMIGA_SERPER 0x8007 /* serial port period (u_short) */
/*
* Atari-specific tags
*/
#define BI_ATARI_MCH_COOKIE 0x8000 /* _MCH cookie from TOS (u_long) */
#define BI_ATARI_MCH_TYPE 0x8001 /* special machine type (u_long) */
/* (values are ATARI_MACH_* defines */
/* mch_cookie values (upper word) */
#define ATARI_MCH_ST 0
#define ATARI_MCH_STE 1
#define ATARI_MCH_TT 2
#define ATARI_MCH_FALCON 3
/* mch_type values */
#define ATARI_MACH_NORMAL 0 /* no special machine type */
#define ATARI_MACH_MEDUSA 1 /* Medusa 040 */
#define ATARI_MACH_HADES 2 /* Hades 040 or 060 */
#define ATARI_MACH_AB40 3 /* Afterburner040 on Falcon */
/*
* VME-specific tags
*/
#define BI_VME_TYPE 0x8000 /* VME sub-architecture (u_long) */
#define BI_VME_BRDINFO 0x8001 /* VME board information (struct) */
/* BI_VME_TYPE codes */
#define VME_TYPE_TP34V 0x0034 /* Tadpole TP34V */
#define VME_TYPE_MVME147 0x0147 /* Motorola MVME147 */
#define VME_TYPE_MVME162 0x0162 /* Motorola MVME162 */
#define VME_TYPE_MVME166 0x0166 /* Motorola MVME166 */
#define VME_TYPE_MVME167 0x0167 /* Motorola MVME167 */
#define VME_TYPE_MVME172 0x0172 /* Motorola MVME172 */
#define VME_TYPE_MVME177 0x0177 /* Motorola MVME177 */
#define VME_TYPE_BVME4000 0x4000 /* BVM Ltd. BVME4000 */
#define VME_TYPE_BVME6000 0x6000 /* BVM Ltd. BVME6000 */
/* BI_VME_BRDINFO is a 32 byte struct as returned by the Bug code on
* Motorola VME boards. Contains board number, Bug version, board
* configuration options, etc. See include/asm/mvme16xhw.h for details.
*/
/*
* Macintosh-specific tags (all u_long)
*/
#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
#define BI_MAC_VADDR 0x8001 /* Mac video base address */
#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
#define BI_MAC_BTIME 0x8007 /* Mac boot time */
#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */
#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */
#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */
#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */
/*
* Macintosh hardware profile data - unused, see macintosh.h for
* resonable type values
*/
#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */
#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */
#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */
#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */
#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */
#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */
#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */
#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */
#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */
#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */
#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */
#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */
#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */
#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */
#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */
#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */
#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */
#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */
/*
* Mac: compatibility with old booter data format (temporarily)
* Fields unused with the new bootinfo can be deleted now; instead of
* adding new fields the struct might be splitted into a hardware address
* part and a hardware type part
*/
#ifndef __ASSEMBLY__
struct mac_booter_data
{
unsigned long videoaddr;
unsigned long videorow;
unsigned long videodepth;
unsigned long dimensions;
unsigned long args;
unsigned long boottime;
unsigned long gmtbias;
unsigned long bootver;
unsigned long videological;
unsigned long sccbase;
unsigned long id;
unsigned long memsize;
unsigned long serialmf;
unsigned long serialhsk;
unsigned long serialgpi;
unsigned long printmf;
unsigned long printhsk;
unsigned long printgpi;
unsigned long cpuid;
unsigned long rombase;
unsigned long adbdelay;
unsigned long timedbra;
};
extern struct mac_booter_data
mac_bi_data;
#endif
/*
* Apollo-specific tags
*/
#define BI_APOLLO_MODEL 0x8000 /* model (u_long) */
/*
* HP300-specific tags
*/
#define BI_HP300_MODEL 0x8000 /* model (u_long) */
#define BI_HP300_UART_SCODE 0x8001 /* UART select code (u_long) */
#define BI_HP300_UART_ADDR 0x8002 /* phys. addr of UART (u_long) */
/*
* Stuff for bootinfo interface versioning
*
* At the start of kernel code, a 'struct bootversion' is located.
* bootstrap checks for a matching version of the interface before booting
* a kernel, to avoid user confusion if kernel and bootstrap don't work
* together :-)
*
* If incompatible changes are made to the bootinfo interface, the major
* number below should be stepped (and the minor reset to 0) for the
* appropriate machine. If a change is backward-compatible, the minor
* should be stepped. "Backwards-compatible" means that booting will work,
* but certain features may not.
*/
#define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */
#define MK_BI_VERSION(major,minor) (((major)<<16)+(minor))
#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff)
#define BI_VERSION_MINOR(v) ((v) & 0xffff)
#ifndef __ASSEMBLY__
struct bootversion {
unsigned short branch;
unsigned long magic;
struct {
unsigned long machtype;
unsigned long version;
} machversions[0];
};
#endif /* __ASSEMBLY__ */
#define AMIGA_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define ATARI_BOOTI_VERSION MK_BI_VERSION( 2, 1 )
#define MAC_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define MVME147_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define MVME16x_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define BVME6000_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define Q40_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#define HP300_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
#ifdef BOOTINFO_COMPAT_1_0
/*
* Backwards compatibility with bootinfo interface version 1.0
*/
#define COMPAT_AMIGA_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#define COMPAT_ATARI_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#define COMPAT_MAC_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#include <linux/zorro.h>
#define COMPAT_NUM_AUTO 16
struct compat_bi_Amiga {
int model;
int num_autocon;
struct ConfigDev autocon[COMPAT_NUM_AUTO];
unsigned long chip_size;
unsigned char vblank;
unsigned char psfreq;
unsigned long eclock;
unsigned long chipset;
unsigned long hw_present;
};
struct compat_bi_Atari {
unsigned long hw_present;
unsigned long mch_cookie;
};
#ifndef __ASSEMBLY__
struct compat_bi_Macintosh
{
unsigned long videoaddr;
unsigned long videorow;
unsigned long videodepth;
unsigned long dimensions;
unsigned long args;
unsigned long boottime;
unsigned long gmtbias;
unsigned long bootver;
unsigned long videological;
unsigned long sccbase;
unsigned long id;
unsigned long memsize;
unsigned long serialmf;
unsigned long serialhsk;
unsigned long serialgpi;
unsigned long printmf;
unsigned long printhsk;
unsigned long printgpi;
unsigned long cpuid;
unsigned long rombase;
unsigned long adbdelay;
unsigned long timedbra;
};
#endif
struct compat_mem_info {
unsigned long addr;
unsigned long size;
};
#define COMPAT_NUM_MEMINFO 4
#define COMPAT_CPUB_68020 0
#define COMPAT_CPUB_68030 1
#define COMPAT_CPUB_68040 2
#define COMPAT_CPUB_68060 3
#define COMPAT_FPUB_68881 5
#define COMPAT_FPUB_68882 6
#define COMPAT_FPUB_68040 7
#define COMPAT_FPUB_68060 8
#define COMPAT_CPU_68020 (1<<COMPAT_CPUB_68020)
#define COMPAT_CPU_68030 (1<<COMPAT_CPUB_68030)
#define COMPAT_CPU_68040 (1<<COMPAT_CPUB_68040)
#define COMPAT_CPU_68060 (1<<COMPAT_CPUB_68060)
#define COMPAT_CPU_MASK (31)
#define COMPAT_FPU_68881 (1<<COMPAT_FPUB_68881)
#define COMPAT_FPU_68882 (1<<COMPAT_FPUB_68882)
#define COMPAT_FPU_68040 (1<<COMPAT_FPUB_68040)
#define COMPAT_FPU_68060 (1<<COMPAT_FPUB_68060)
#define COMPAT_FPU_MASK (0xfe0)
#define COMPAT_CL_SIZE (256)
struct compat_bootinfo {
unsigned long machtype;
unsigned long cputype;
struct compat_mem_info memory[COMPAT_NUM_MEMINFO];
int num_memory;
unsigned long ramdisk_size;
unsigned long ramdisk_addr;
char command_line[COMPAT_CL_SIZE];
union {
struct compat_bi_Amiga bi_ami;
struct compat_bi_Atari bi_ata;
struct compat_bi_Macintosh bi_mac;
} bi_un;
};
#define bi_amiga bi_un.bi_ami
#define bi_atari bi_un.bi_ata
#define bi_mac bi_un.bi_mac
#endif /* BOOTINFO_COMPAT_1_0 */
#endif /* _M68K_BOOTINFO_H */

2
arch/m68k/include/asm/bootinfo_no.h Normal file
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/* Nothing for m68knommu */

132
arch/m68k/include/asm/bootstd.h Normal file
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/* bootstd.h: Bootloader system call interface
*
* (c) 1999, Rt-Control, Inc.
*/
#ifndef __BOOTSTD_H__
#define __BOOTSTD_H__
#define NR_BSC 21 /* last used bootloader system call */
#define __BN_reset 0 /* reset and start the bootloader */
#define __BN_test 1 /* tests the system call interface */
#define __BN_exec 2 /* executes a bootloader image */
#define __BN_exit 3 /* terminates a bootloader image */
#define __BN_program 4 /* program FLASH from a chain */
#define __BN_erase 5 /* erase sector(s) of FLASH */
#define __BN_open 6
#define __BN_write 7
#define __BN_read 8
#define __BN_close 9
#define __BN_mmap 10 /* map a file descriptor into memory */
#define __BN_munmap 11 /* remove a file to memory mapping */
#define __BN_gethwaddr 12 /* get the hardware address of my interfaces */
#define __BN_getserialnum 13 /* get the serial number of this board */
#define __BN_getbenv 14 /* get a bootloader envvar */
#define __BN_setbenv 15 /* get a bootloader envvar */
#define __BN_setpmask 16 /* set the protection mask */
#define __BN_readenv 17 /* read environment variables */
#define __BN_flash_chattr_range 18
#define __BN_flash_erase_range 19
#define __BN_flash_write_range 20
/* Calling conventions compatible to (uC)linux/68k
* We use simmilar macros to call into the bootloader as for uClinux
*/
#define __bsc_return(type, res) \
do { \
if ((unsigned long)(res) >= (unsigned long)(-64)) { \
/* let errno be a function, preserve res in %d0 */ \
int __err = -(res); \
errno = __err; \
res = -1; \
} \
return (type)(res); \
} while (0)
#define _bsc0(type,name) \
type name(void) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res) \
); \
__bsc_return(type,__res); \
}
#define _bsc1(type,name,atype,a) \
type name(atype a) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a) \
); \
__bsc_return(type,__res); \
}
#define _bsc2(type,name,atype,a,btype,b) \
type name(atype a, btype b) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
register long __b __asm__ ("%d2") = (long)b; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a), "d" (__b) \
); \
__bsc_return(type,__res); \
}
#define _bsc3(type,name,atype,a,btype,b,ctype,c) \
type name(atype a, btype b, ctype c) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
register long __b __asm__ ("%d2") = (long)b; \
register long __c __asm__ ("%d3") = (long)c; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a), "d" (__b), \
"d" (__c) \
); \
__bsc_return(type,__res); \
}
#define _bsc4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
type name(atype a, btype b, ctype c, dtype d) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
register long __b __asm__ ("%d2") = (long)b; \
register long __c __asm__ ("%d3") = (long)c; \
register long __d __asm__ ("%d4") = (long)d; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a), "d" (__b), \
"d" (__c), "d" (__d) \
); \
__bsc_return(type,__res); \
}
#define _bsc5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
type name(atype a, btype b, ctype c, dtype d, etype e) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
register long __b __asm__ ("%d2") = (long)b; \
register long __c __asm__ ("%d3") = (long)c; \
register long __d __asm__ ("%d4") = (long)d; \
register long __e __asm__ ("%d5") = (long)e; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a), "d" (__b), \
"d" (__c), "d" (__d), "d" (__e) \
); \
__bsc_return(type,__res); \
}
#endif /* __BOOTSTD_H__ */

5
arch/m68k/include/asm/bug.h Normal file
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@@ -0,0 +1,5 @@
#ifdef __uClinux__
#include "bug_no.h"
#else
#include "bug_mm.h"
#endif

29
arch/m68k/include/asm/bug_mm.h Normal file
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@@ -0,0 +1,29 @@
#ifndef _M68K_BUG_H
#define _M68K_BUG_H
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
#ifndef CONFIG_SUN3
#define BUG() do { \
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
__builtin_trap(); \
} while (0)
#else
#define BUG() do { \
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
panic("BUG!"); \
} while (0)
#endif
#else
#define BUG() do { \
__builtin_trap(); \
} while (0)
#endif
#define HAVE_ARCH_BUG
#endif
#include <asm-generic/bug.h>
#endif

4
arch/m68k/include/asm/bug_no.h Normal file
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@@ -0,0 +1,4 @@
#ifndef _M68KNOMMU_BUG_H
#define _M68KNOMMU_BUG_H
#include <asm-generic/bug.h>
#endif

5
arch/m68k/include/asm/bugs.h Normal file
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@@ -0,0 +1,5 @@
#ifdef __uClinux__
#include "bugs_no.h"
#else
#include "bugs_mm.h"
#endif

14
arch/m68k/include/asm/bugs_mm.h Normal file
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@@ -0,0 +1,14 @@
/*
* include/asm-m68k/bugs.h
*
* Copyright (C) 1994 Linus Torvalds
*/
/*
* This is included by init/main.c to check for architecture-dependent bugs.
*
* Needs:
* void check_bugs(void);
*/
extern void check_bugs(void); /* in arch/m68k/kernel/setup.c */

16
arch/m68k/include/asm/bugs_no.h Normal file
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@@ -0,0 +1,16 @@
/*
* include/asm-m68k/bugs.h
*
* Copyright (C) 1994 Linus Torvalds
*/
/*
* This is included by init/main.c to check for architecture-dependent bugs.
*
* Needs:
* void check_bugs(void);
*/
static void check_bugs(void)
{
}

150
arch/m68k/include/asm/bvme6000hw.h Normal file
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#ifndef _M68K_BVME6000HW_H_
#define _M68K_BVME6000HW_H_
#include <asm/irq.h>
/*
* PIT structure
*/
#define BVME_PIT_BASE 0xffa00000
typedef struct {
unsigned char
pad_a[3], pgcr,
pad_b[3], psrr,
pad_c[3], paddr,
pad_d[3], pbddr,
pad_e[3], pcddr,
pad_f[3], pivr,
pad_g[3], pacr,
pad_h[3], pbcr,
pad_i[3], padr,
pad_j[3], pbdr,
pad_k[3], paar,
pad_l[3], pbar,
pad_m[3], pcdr,
pad_n[3], psr,
pad_o[3], res1,
pad_p[3], res2,
pad_q[3], tcr,
pad_r[3], tivr,
pad_s[3], res3,
pad_t[3], cprh,
pad_u[3], cprm,
pad_v[3], cprl,
pad_w[3], res4,
pad_x[3], crh,
pad_y[3], crm,
pad_z[3], crl,
pad_A[3], tsr,
pad_B[3], res5;
} PitRegs_t, *PitRegsPtr;
#define bvmepit ((*(volatile PitRegsPtr)(BVME_PIT_BASE)))
#define BVME_RTC_BASE 0xff900000
typedef struct {
unsigned char
pad_a[3], msr,
pad_b[3], t0cr_rtmr,
pad_c[3], t1cr_omr,
pad_d[3], pfr_icr0,
pad_e[3], irr_icr1,
pad_f[3], bcd_tenms,
pad_g[3], bcd_sec,
pad_h[3], bcd_min,
pad_i[3], bcd_hr,
pad_j[3], bcd_dom,
pad_k[3], bcd_mth,
pad_l[3], bcd_year,
pad_m[3], bcd_ujcc,
pad_n[3], bcd_hjcc,
pad_o[3], bcd_dow,
pad_p[3], t0lsb,
pad_q[3], t0msb,
pad_r[3], t1lsb,
pad_s[3], t1msb,
pad_t[3], cmp_sec,
pad_u[3], cmp_min,
pad_v[3], cmp_hr,
pad_w[3], cmp_dom,
pad_x[3], cmp_mth,
pad_y[3], cmp_dow,
pad_z[3], sav_sec,
pad_A[3], sav_min,
pad_B[3], sav_hr,
pad_C[3], sav_dom,
pad_D[3], sav_mth,
pad_E[3], ram,
pad_F[3], test;
} RtcRegs_t, *RtcPtr_t;
#define BVME_I596_BASE 0xff100000
#define BVME_ETHIRQ_REG 0xff20000b
#define BVME_LOCAL_IRQ_STAT 0xff20000f
#define BVME_ETHERR 0x02
#define BVME_ABORT_STATUS 0x08
#define BVME_NCR53C710_BASE 0xff000000
#define BVME_SCC_A_ADDR 0xffb0000b
#define BVME_SCC_B_ADDR 0xffb00003
#define BVME_SCC_RTxC 7372800
#define BVME_CONFIG_REG 0xff500003
#define config_reg_ptr (volatile unsigned char *)BVME_CONFIG_REG
#define BVME_CONFIG_SW1 0x08
#define BVME_CONFIG_SW2 0x04
#define BVME_CONFIG_SW3 0x02
#define BVME_CONFIG_SW4 0x01
#define BVME_IRQ_TYPE_PRIO 0
#define BVME_IRQ_PRN (IRQ_USER+20)
#define BVME_IRQ_TIMER (IRQ_USER+25)
#define BVME_IRQ_I596 IRQ_AUTO_2
#define BVME_IRQ_SCSI IRQ_AUTO_3
#define BVME_IRQ_RTC IRQ_AUTO_6
#define BVME_IRQ_ABORT IRQ_AUTO_7
/* SCC interrupts */
#define BVME_IRQ_SCC_BASE IRQ_USER
#define BVME_IRQ_SCCB_TX IRQ_USER
#define BVME_IRQ_SCCB_STAT (IRQ_USER+2)
#define BVME_IRQ_SCCB_RX (IRQ_USER+4)
#define BVME_IRQ_SCCB_SPCOND (IRQ_USER+6)
#define BVME_IRQ_SCCA_TX (IRQ_USER+8)
#define BVME_IRQ_SCCA_STAT (IRQ_USER+10)
#define BVME_IRQ_SCCA_RX (IRQ_USER+12)
#define BVME_IRQ_SCCA_SPCOND (IRQ_USER+14)
/* Address control registers */
#define BVME_ACR_A32VBA 0xff400003
#define BVME_ACR_A32MSK 0xff410003
#define BVME_ACR_A24VBA 0xff420003
#define BVME_ACR_A24MSK 0xff430003
#define BVME_ACR_A16VBA 0xff440003
#define BVME_ACR_A32LBA 0xff450003
#define BVME_ACR_A24LBA 0xff460003
#define BVME_ACR_ADDRCTL 0xff470003
#define bvme_acr_a32vba *(volatile unsigned char *)BVME_ACR_A32VBA
#define bvme_acr_a32msk *(volatile unsigned char *)BVME_ACR_A32MSK
#define bvme_acr_a24vba *(volatile unsigned char *)BVME_ACR_A24VBA
#define bvme_acr_a24msk *(volatile unsigned char *)BVME_ACR_A24MSK
#define bvme_acr_a16vba *(volatile unsigned char *)BVME_ACR_A16VBA
#define bvme_acr_a32lba *(volatile unsigned char *)BVME_ACR_A32LBA
#define bvme_acr_a24lba *(volatile unsigned char *)BVME_ACR_A24LBA
#define bvme_acr_addrctl *(volatile unsigned char *)BVME_ACR_ADDRCTL
#endif

5
arch/m68k/include/asm/byteorder.h Normal file
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@@ -0,0 +1,5 @@
#ifdef __uClinux__
#include "byteorder_no.h"
#else
#include "byteorder_mm.h"
#endif

6
arch/m68k/include/asm/byteorder_mm.h Normal file
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@@ -0,0 +1,6 @@
#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
#include <linux/byteorder/big_endian.h>
#endif /* _M68K_BYTEORDER_H */

6
arch/m68k/include/asm/byteorder_no.h Normal file
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@@ -0,0 +1,6 @@
#ifndef _M68KNOMMU_BYTEORDER_H
#define _M68KNOMMU_BYTEORDER_H
#include <linux/byteorder/big_endian.h>
#endif /* _M68KNOMMU_BYTEORDER_H */

5
arch/m68k/include/asm/cache.h Normal file
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@@ -0,0 +1,5 @@
#ifdef __uClinux__
#include "cache_no.h"
#else
#include "cache_mm.h"
#endif

11
arch/m68k/include/asm/cache_mm.h Normal file
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@@ -0,0 +1,11 @@
/*
* include/asm-m68k/cache.h
*/
#ifndef __ARCH_M68K_CACHE_H
#define __ARCH_M68K_CACHE_H
/* bytes per L1 cache line */
#define L1_CACHE_SHIFT 4
#define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT)
#endif

12
arch/m68k/include/asm/cache_no.h Normal file
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@@ -0,0 +1,12 @@
#ifndef __ARCH_M68KNOMMU_CACHE_H
#define __ARCH_M68KNOMMU_CACHE_H
/* bytes per L1 cache line */
#define L1_CACHE_BYTES 16 /* this need to be at least 1 */
/* m68k-elf-gcc 2.95.2 doesn't like these */
#define __cacheline_aligned
#define ____cacheline_aligned
#endif

14
arch/m68k/include/asm/cachectl.h Normal file
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@@ -0,0 +1,14 @@
#ifndef _M68K_CACHECTL_H
#define _M68K_CACHECTL_H
/* Definitions for the cacheflush system call. */
#define FLUSH_SCOPE_LINE 1 /* Flush a cache line */
#define FLUSH_SCOPE_PAGE 2 /* Flush a page */
#define FLUSH_SCOPE_ALL 3 /* Flush the whole cache -- superuser only */
#define FLUSH_CACHE_DATA 1 /* Writeback and flush data cache */
#define FLUSH_CACHE_INSN 2 /* Flush instruction cache */
#define FLUSH_CACHE_BOTH 3 /* Flush both caches */
#endif /* _M68K_CACHECTL_H */

5
arch/m68k/include/asm/cacheflush.h Normal file
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@@ -0,0 +1,5 @@
#ifdef __uClinux__
#include "cacheflush_no.h"
#else
#include "cacheflush_mm.h"
#endif

156
arch/m68k/include/asm/cacheflush_mm.h Normal file
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@@ -0,0 +1,156 @@
#ifndef _M68K_CACHEFLUSH_H
#define _M68K_CACHEFLUSH_H
#include <linux/mm.h>
/* cache code */
#define FLUSH_I_AND_D (0x00000808)
#define FLUSH_I (0x00000008)
/*
* Cache handling functions
*/
static inline void flush_icache(void)
{
if (CPU_IS_040_OR_060)
asm volatile ( "nop\n"
" .chip 68040\n"
" cpusha %bc\n"
" .chip 68k");
else {
unsigned long tmp;
asm volatile ( "movec %%cacr,%0\n"
" or.w %1,%0\n"
" movec %0,%%cacr"
: "=&d" (tmp)
: "id" (FLUSH_I));
}
}
/*
* invalidate the cache for the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_clear(unsigned long paddr, int len);
/*
* push any dirty cache in the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_push(unsigned long paddr, int len);
/*
* push and invalidate pages in the specified user virtual
* memory range.
*/
extern void cache_push_v(unsigned long vaddr, int len);
/* This is needed whenever the virtual mapping of the current
process changes. */
#define __flush_cache_all() \
({ \
if (CPU_IS_040_OR_060) \
__asm__ __volatile__("nop\n\t" \
".chip 68040\n\t" \
"cpusha %dc\n\t" \
".chip 68k"); \
else { \
unsigned long _tmp; \
__asm__ __volatile__("movec %%cacr,%0\n\t" \
"orw %1,%0\n\t" \
"movec %0,%%cacr" \
: "=&d" (_tmp) \
: "di" (FLUSH_I_AND_D)); \
} \
})
#define __flush_cache_030() \
({ \
if (CPU_IS_020_OR_030) { \
unsigned long _tmp; \
__asm__ __volatile__("movec %%cacr,%0\n\t" \
"orw %1,%0\n\t" \
"movec %0,%%cacr" \
: "=&d" (_tmp) \
: "di" (FLUSH_I_AND_D)); \
} \
})
#define flush_cache_all() __flush_cache_all()
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
static inline void flush_cache_mm(struct mm_struct *mm)
{
if (mm == current->mm)
__flush_cache_030();
}
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
/* flush_cache_range/flush_cache_page must be macros to avoid
a dependency on linux/mm.h, which includes this file... */
static inline void flush_cache_range(struct vm_area_struct *vma,
unsigned long start,
unsigned long end)
{
if (vma->vm_mm == current->mm)
__flush_cache_030();
}
static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
{
if (vma->vm_mm == current->mm)
__flush_cache_030();
}
/* Push the page at kernel virtual address and clear the icache */
/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
static inline void __flush_page_to_ram(void *vaddr)
{
if (CPU_IS_040_OR_060) {
__asm__ __volatile__("nop\n\t"
".chip 68040\n\t"
"cpushp %%bc,(%0)\n\t"
".chip 68k"
: : "a" (__pa(vaddr)));
} else {
unsigned long _tmp;
__asm__ __volatile__("movec %%cacr,%0\n\t"
"orw %1,%0\n\t"
"movec %0,%%cacr"
: "=&d" (_tmp)
: "di" (FLUSH_I));
}
}
#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
unsigned long addr, int len);
extern void flush_icache_range(unsigned long address, unsigned long endaddr);
static inline void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr,
void *dst, void *src, int len)
{
flush_cache_page(vma, vaddr, page_to_pfn(page));
memcpy(dst, src, len);
flush_icache_user_range(vma, page, vaddr, len);
}
static inline void copy_from_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr,
void *dst, void *src, int len)
{
flush_cache_page(vma, vaddr, page_to_pfn(page));
memcpy(dst, src, len);
}
#endif /* _M68K_CACHEFLUSH_H */

84
arch/m68k/include/asm/cacheflush_no.h Normal file
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#ifndef _M68KNOMMU_CACHEFLUSH_H
#define _M68KNOMMU_CACHEFLUSH_H
/*
* (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
*/
#include <linux/mm.h>
#define flush_cache_all() __flush_cache_all()
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_dup_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) __flush_cache_all()
#define flush_cache_page(vma, vmaddr) do { } while (0)
#define flush_dcache_range(start,len) __flush_cache_all()
#define flush_dcache_page(page) do { } while (0)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_range(start,len) __flush_cache_all()
#define flush_icache_page(vma,pg) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define flush_cache_vmap(start, end) do { } while (0)
#define flush_cache_vunmap(start, end) do { } while (0)
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
static inline void __flush_cache_all(void)
{
#ifdef CONFIG_M5407
/*
* Use cpushl to push and invalidate all cache lines.
* Gas doesn't seem to know how to generate the ColdFire
* cpushl instruction... Oh well, bit stuff it for now.
*/
__asm__ __volatile__ (
"nop\n\t"
"clrl %%d0\n\t"
"1:\n\t"
"movel %%d0,%%a0\n\t"
"2:\n\t"
".word 0xf468\n\t"
"addl #0x10,%%a0\n\t"
"cmpl #0x00000800,%%a0\n\t"
"blt 2b\n\t"
"addql #1,%%d0\n\t"
"cmpil #4,%%d0\n\t"
"bne 1b\n\t"
"movel #0xb6088500,%%d0\n\t"
"movec %%d0,%%CACR\n\t"
: : : "d0", "a0" );
#endif /* CONFIG_M5407 */
#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
__asm__ __volatile__ (
"movel #0x81000200, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M527x || CONFIG_M528x */
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
__asm__ __volatile__ (
"movel #0x81000100, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
#ifdef CONFIG_M5249
__asm__ __volatile__ (
"movel #0xa1000200, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M532x
__asm__ __volatile__ (
"movel #0x81000200, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M532x */
}
#endif /* _M68KNOMMU_CACHEFLUSH_H */

5
arch/m68k/include/asm/checksum.h Normal file
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@@ -0,0 +1,5 @@
#ifdef __uClinux__
#include "checksum_no.h"
#else
#include "checksum_mm.h"
#endif

148
arch/m68k/include/asm/checksum_mm.h Normal file
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#ifndef _M68K_CHECKSUM_H
#define _M68K_CHECKSUM_H
#include <linux/in6.h>
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
__wsum csum_partial(const void *buff, int len, __wsum sum);
/*
* the same as csum_partial, but copies from src while it
* checksums
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
extern __wsum csum_partial_copy_from_user(const void __user *src,
void *dst,
int len, __wsum sum,
int *csum_err);
extern __wsum csum_partial_copy_nocheck(const void *src,
void *dst, int len,
__wsum sum);
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries.
*
*/
static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
{
unsigned int sum = 0;
unsigned long tmp;
__asm__ ("subqw #1,%2\n"
"1:\t"
"movel %1@+,%3\n\t"
"addxl %3,%0\n\t"
"dbra %2,1b\n\t"
"movel %0,%3\n\t"
"swap %3\n\t"
"addxw %3,%0\n\t"
"clrw %3\n\t"
"addxw %3,%0\n\t"
: "=d" (sum), "=&a" (iph), "=&d" (ihl), "=&d" (tmp)
: "0" (sum), "1" (iph), "2" (ihl)
: "memory");
return (__force __sum16)~sum;
}
/*
* Fold a partial checksum
*/
static inline __sum16 csum_fold(__wsum sum)
{
unsigned int tmp = (__force u32)sum;
__asm__("swap %1\n\t"
"addw %1, %0\n\t"
"clrw %1\n\t"
"addxw %1, %0"
: "=&d" (sum), "=&d" (tmp)
: "0" (sum), "1" (tmp));
return (__force __sum16)~sum;
}
static inline __wsum
csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
__asm__ ("addl %2,%0\n\t"
"addxl %3,%0\n\t"
"addxl %4,%0\n\t"
"clrl %1\n\t"
"addxl %1,%0"
: "=&d" (sum), "=d" (saddr)
: "g" (daddr), "1" (saddr), "d" (len + proto),
"0" (sum));
return sum;
}
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static inline __sum16
csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline __sum16 ip_compute_csum(const void *buff, int len)
{
return csum_fold (csum_partial(buff, len, 0));
}
#define _HAVE_ARCH_IPV6_CSUM
static __inline__ __sum16
csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
__u32 len, unsigned short proto, __wsum sum)
{
register unsigned long tmp;
__asm__("addl %2@,%0\n\t"
"movel %2@(4),%1\n\t"
"addxl %1,%0\n\t"
"movel %2@(8),%1\n\t"
"addxl %1,%0\n\t"
"movel %2@(12),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@,%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(4),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(8),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(12),%1\n\t"
"addxl %1,%0\n\t"
"addxl %4,%0\n\t"
"clrl %1\n\t"
"addxl %1,%0"
: "=&d" (sum), "=&d" (tmp)
: "a" (saddr), "a" (daddr), "d" (len + proto),
"0" (sum));
return csum_fold(sum);
}
#endif /* _M68K_CHECKSUM_H */

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#ifndef _M68K_CHECKSUM_H
#define _M68K_CHECKSUM_H
#include <linux/in6.h>
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
__wsum csum_partial(const void *buff, int len, __wsum sum);
/*
* the same as csum_partial, but copies from src while it
* checksums
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
__wsum csum_partial_copy_nocheck(const void *src, void *dst,
int len, __wsum sum);
/*
* the same as csum_partial_copy, but copies from user space.
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
extern __wsum csum_partial_copy_from_user(const void __user *src,
void *dst, int len, __wsum sum, int *csum_err);
__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
/*
* Fold a partial checksum
*/
static inline __sum16 csum_fold(__wsum sum)
{
unsigned int tmp = (__force u32)sum;
#ifdef CONFIG_COLDFIRE
tmp = (tmp & 0xffff) + (tmp >> 16);
tmp = (tmp & 0xffff) + (tmp >> 16);
return (__force __sum16)~tmp;
#else
__asm__("swap %1\n\t"
"addw %1, %0\n\t"
"clrw %1\n\t"
"addxw %1, %0"
: "=&d" (sum), "=&d" (tmp)
: "0" (sum), "1" (sum));
return (__force __sum16)~sum;
#endif
}
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static inline __wsum
csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
__asm__ ("addl %1,%0\n\t"
"addxl %4,%0\n\t"
"addxl %5,%0\n\t"
"clrl %1\n\t"
"addxl %1,%0"
: "=&d" (sum), "=&d" (saddr)
: "0" (daddr), "1" (saddr), "d" (len + proto),
"d"(sum));
return sum;
}
static inline __sum16
csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
extern __sum16 ip_compute_csum(const void *buff, int len);
#define _HAVE_ARCH_IPV6_CSUM
static __inline__ __sum16
csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
__u32 len, unsigned short proto, __wsum sum)
{
register unsigned long tmp;
__asm__("addl %2@,%0\n\t"
"movel %2@(4),%1\n\t"
"addxl %1,%0\n\t"
"movel %2@(8),%1\n\t"
"addxl %1,%0\n\t"
"movel %2@(12),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@,%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(4),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(8),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(12),%1\n\t"
"addxl %1,%0\n\t"
"addxl %4,%0\n\t"
"clrl %1\n\t"
"addxl %1,%0"
: "=&d" (sum), "=&d" (tmp)
: "a" (saddr), "a" (daddr), "d" (len + proto),
"0" (sum));
return csum_fold(sum);
}
#endif /* _M68K_CHECKSUM_H */

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/****************************************************************************/
/*
* coldfire.h -- Motorola ColdFire CPU sepecific defines
*
* (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo (www.lineo.com)
*/
/****************************************************************************/
#ifndef coldfire_h
#define coldfire_h
/****************************************************************************/
/*
* Define master clock frequency. This is essentially done at config
* time now. No point enumerating dozens of possible clock options
* here. Also the peripheral clock (bus clock) divide ratio is set
* at config time too.
*/
#ifdef CONFIG_CLOCK_SET
#define MCF_CLK CONFIG_CLOCK_FREQ
#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
#else
#error "Don't know what your ColdFire CPU clock frequency is??"
#endif
/*
* Define the processor support peripherals base address.
* This is generally setup by the boards start up code.
*/
#define MCF_MBAR 0x10000000
#define MCF_MBAR2 0x80000000
#if defined(CONFIG_M520x)
#define MCF_IPSBAR 0xFC000000
#else
#define MCF_IPSBAR 0x40000000
#endif
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M520x)
#undef MCF_MBAR
#define MCF_MBAR MCF_IPSBAR
#elif defined(CONFIG_M532x)
#undef MCF_MBAR
#define MCF_MBAR 0x00000000
#endif
/****************************************************************************/
#endif /* coldfire_h */

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/*
* 68360 Communication Processor Module.
* Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after:
* Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx)
*
* This file contains structures and information for the communication
* processor channels. Some CPM control and status is available
* through the 68360 internal memory map. See include/asm/360_immap.h for details.
* This file is not a complete map of all of the 360 QUICC's capabilities
*
* On the MBX board, EPPC-Bug loads CPM microcode into the first 512
* bytes of the DP RAM and relocates the I2C parameter area to the
* IDMA1 space. The remaining DP RAM is available for buffer descriptors
* or other use.
*/
#ifndef __CPM_360__
#define __CPM_360__
/* CPM Command register masks: */
#define CPM_CR_RST ((ushort)0x8000)
#define CPM_CR_OPCODE ((ushort)0x0f00)
#define CPM_CR_CHAN ((ushort)0x00f0)
#define CPM_CR_FLG ((ushort)0x0001)
/* CPM Command set (opcodes): */
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_GRSTOP_TX ((ushort)0x0005)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009)
#define CPM_CR_GCI_ABORT ((ushort)0x000a)
#define CPM_CR_RESET_BCS ((ushort)0x000a)
/* CPM Channel numbers. */
#define CPM_CR_CH_SCC1 ((ushort)0x0000)
#define CPM_CR_CH_SCC2 ((ushort)0x0004)
#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */
#define CPM_CR_CH_TMR ((ushort)0x0005)
#define CPM_CR_CH_SCC3 ((ushort)0x0008)
#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */
#define CPM_CR_CH_IDMA1 ((ushort)0x0009)
#define CPM_CR_CH_SCC4 ((ushort)0x000c)
#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */
#define CPM_CR_CH_IDMA2 ((ushort)0x000d)
#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
#if 1 /* mleslie: I dinna think we have any such restrictions on
* DP RAM aboard the 360 board - see the MC68360UM p.3-3 */
/* The dual ported RAM is multi-functional. Some areas can be (and are
* being) used for microcode. There is an area that can only be used
* as data ram for buffer descriptors, which is all we use right now.
* Currently the first 512 and last 256 bytes are used for microcode.
*/
/* mleslie: The uCquicc board is using no extra microcode in DPRAM */
#define CPM_DATAONLY_BASE ((uint)0x0000)
#define CPM_DATAONLY_SIZE ((uint)0x0800)
#define CPM_DP_NOSPACE ((uint)0x7fffffff)
#endif
/* Export the base address of the communication processor registers
* and dual port ram. */
/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */
extern QUICC *pquicc;
uint m360_cpm_dpalloc(uint size);
/* void *m360_cpm_hostalloc(uint size); */
void m360_cpm_setbrg(uint brg, uint rate);
#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */
/* Buffer descriptors used by many of the CPM protocols. */
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#endif
/* rx bd status/control bits */
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
/* tx bd status/control bits (as differ from rx bd) */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_UN ((ushort)0x0002) /* Underrun */
/* Parameter RAM offsets. */
/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM.
* In 2.0, we use a more structured C struct map of DPRAM, and so
* instead, we need only a parameter ram `slot' */
#define PRSLOT_SCC1 0
#define PRSLOT_SCC2 1
#define PRSLOT_SCC3 2
#define PRSLOT_SMC1 2
#define PRSLOT_SCC4 3
#define PRSLOT_SMC2 3
/* #define PROFF_SCC1 ((uint)0x0000) */
/* #define PROFF_SCC2 ((uint)0x0100) */
/* #define PROFF_SCC3 ((uint)0x0200) */
/* #define PROFF_SMC1 ((uint)0x0280) */
/* #define PROFF_SCC4 ((uint)0x0300) */
/* #define PROFF_SMC2 ((uint)0x0380) */
/* Define enough so I can at least use the serial port as a UART.
* The MBX uses SMC1 as the host serial port.
*/
typedef struct smc_uart {
ushort smc_rbase; /* Rx Buffer descriptor base address */
ushort smc_tbase; /* Tx Buffer descriptor base address */
u_char smc_rfcr; /* Rx function code */
u_char smc_tfcr; /* Tx function code */
ushort smc_mrblr; /* Max receive buffer length */
uint smc_rstate; /* Internal */
uint smc_idp; /* Internal */
ushort smc_rbptr; /* Internal */
ushort smc_ibc; /* Internal */
uint smc_rxtmp; /* Internal */
uint smc_tstate; /* Internal */
uint smc_tdp; /* Internal */
ushort smc_tbptr; /* Internal */
ushort smc_tbc; /* Internal */
uint smc_txtmp; /* Internal */
ushort smc_maxidl; /* Maximum idle characters */
ushort smc_tmpidl; /* Temporary idle counter */
ushort smc_brklen; /* Last received break length */
ushort smc_brkec; /* rcv'd break condition counter */
ushort smc_brkcr; /* xmt break count register */
ushort smc_rmask; /* Temporary bit mask */
} smc_uart_t;
/* Function code bits.
*/
#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
/* SMC uart mode register.
*/
#define SMCMR_REN ((ushort)0x0001)
#define SMCMR_TEN ((ushort)0x0002)
#define SMCMR_DM ((ushort)0x000c)
#define SMCMR_SM_GCI ((ushort)0x0000)
#define SMCMR_SM_UART ((ushort)0x0020)
#define SMCMR_SM_TRANS ((ushort)0x0030)
#define SMCMR_SM_MASK ((ushort)0x0030)
#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
#define SMCMR_REVD SMCMR_PM_EVEN
#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
#define SMCMR_BS SMCMR_PEN
#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
/* SMC2 as Centronics parallel printer. It is half duplex, in that
* it can only receive or transmit. The parameter ram values for
* each direction are either unique or properly overlap, so we can
* include them in one structure.
*/
typedef struct smc_centronics {
ushort scent_rbase;
ushort scent_tbase;
u_char scent_cfcr;
u_char scent_smask;
ushort scent_mrblr;
uint scent_rstate;
uint scent_r_ptr;
ushort scent_rbptr;
ushort scent_r_cnt;
uint scent_rtemp;
uint scent_tstate;
uint scent_t_ptr;
ushort scent_tbptr;
ushort scent_t_cnt;
uint scent_ttemp;
ushort scent_max_sl;
ushort scent_sl_cnt;
ushort scent_character1;
ushort scent_character2;
ushort scent_character3;
ushort scent_character4;
ushort scent_character5;
ushort scent_character6;
ushort scent_character7;
ushort scent_character8;
ushort scent_rccm;
ushort scent_rccr;
} smc_cent_t;
/* Centronics Status Mask Register.
*/
#define SMC_CENT_F ((u_char)0x08)
#define SMC_CENT_PE ((u_char)0x04)
#define SMC_CENT_S ((u_char)0x02)
/* SMC Event and Mask register.
*/
#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
#define SMCM_BSY ((unsigned char)0x04)
#define SMCM_TX ((unsigned char)0x02)
#define SMCM_RX ((unsigned char)0x01)
/* Baud rate generators.
*/
#define CPM_BRG_RST ((uint)0x00020000)
#define CPM_BRG_EN ((uint)0x00010000)
#define CPM_BRG_EXTC_INT ((uint)0x00000000)
#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
#define CPM_BRG_ATB ((uint)0x00002000)
#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
#define CPM_BRG_DIV16 ((uint)0x00000001)
/* SCCs.
*/
#define SCC_GSMRH_IRP ((uint)0x00040000)
#define SCC_GSMRH_GDE ((uint)0x00010000)
#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
#define SCC_GSMRH_REVD ((uint)0x00002000)
#define SCC_GSMRH_TRX ((uint)0x00001000)
#define SCC_GSMRH_TTX ((uint)0x00000800)
#define SCC_GSMRH_CDP ((uint)0x00000400)
#define SCC_GSMRH_CTSP ((uint)0x00000200)
#define SCC_GSMRH_CDS ((uint)0x00000100)
#define SCC_GSMRH_CTSS ((uint)0x00000080)
#define SCC_GSMRH_TFL ((uint)0x00000040)
#define SCC_GSMRH_RFW ((uint)0x00000020)
#define SCC_GSMRH_TXSY ((uint)0x00000010)
#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
#define SCC_GSMRH_RTSM ((uint)0x00000002)
#define SCC_GSMRH_RSYN ((uint)0x00000001)
#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
#define SCC_GSMRL_TCI ((uint)0x10000000)
#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
#define SCC_GSMRL_RINV ((uint)0x02000000)
#define SCC_GSMRL_TINV ((uint)0x01000000)
#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
#define SCC_GSMRL_TEND ((uint)0x00040000)
#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
#define SCC_GSMRL_ENR ((uint)0x00000020)
#define SCC_GSMRL_ENT ((uint)0x00000010)
#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
#define SCC_TODR_TOD ((ushort)0x8000)
/* SCC Event and Mask register.
*/
#define SCCM_TXE ((unsigned char)0x10)
#define SCCM_BSY ((unsigned char)0x04)
#define SCCM_TX ((unsigned char)0x02)
#define SCCM_RX ((unsigned char)0x01)
typedef struct scc_param {
ushort scc_rbase; /* Rx Buffer descriptor base address */
ushort scc_tbase; /* Tx Buffer descriptor base address */
u_char scc_rfcr; /* Rx function code */
u_char scc_tfcr; /* Tx function code */
ushort scc_mrblr; /* Max receive buffer length */
uint scc_rstate; /* Internal */
uint scc_idp; /* Internal */
ushort scc_rbptr; /* Internal */
ushort scc_ibc; /* Internal */
uint scc_rxtmp; /* Internal */
uint scc_tstate; /* Internal */
uint scc_tdp; /* Internal */
ushort scc_tbptr; /* Internal */
ushort scc_tbc; /* Internal */
uint scc_txtmp; /* Internal */
uint scc_rcrc; /* Internal */
uint scc_tcrc; /* Internal */
} sccp_t;
/* Function code bits.
*/
#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */
/* CPM Ethernet through SCC1.
*/
typedef struct scc_enet {
sccp_t sen_genscc;
uint sen_cpres; /* Preset CRC */
uint sen_cmask; /* Constant mask for CRC */
uint sen_crcec; /* CRC Error counter */
uint sen_alec; /* alignment error counter */
uint sen_disfc; /* discard frame counter */
ushort sen_pads; /* Tx short frame pad character */
ushort sen_retlim; /* Retry limit threshold */
ushort sen_retcnt; /* Retry limit counter */
ushort sen_maxflr; /* maximum frame length register */
ushort sen_minflr; /* minimum frame length register */
ushort sen_maxd1; /* maximum DMA1 length */
ushort sen_maxd2; /* maximum DMA2 length */
ushort sen_maxd; /* Rx max DMA */
ushort sen_dmacnt; /* Rx DMA counter */
ushort sen_maxb; /* Max BD byte count */
ushort sen_gaddr1; /* Group address filter */
ushort sen_gaddr2;
ushort sen_gaddr3;
ushort sen_gaddr4;
uint sen_tbuf0data0; /* Save area 0 - current frame */
uint sen_tbuf0data1; /* Save area 1 - current frame */
uint sen_tbuf0rba; /* Internal */
uint sen_tbuf0crc; /* Internal */
ushort sen_tbuf0bcnt; /* Internal */
ushort sen_paddrh; /* physical address (MSB) */
ushort sen_paddrm;
ushort sen_paddrl; /* physical address (LSB) */
ushort sen_pper; /* persistence */
ushort sen_rfbdptr; /* Rx first BD pointer */
ushort sen_tfbdptr; /* Tx first BD pointer */
ushort sen_tlbdptr; /* Tx last BD pointer */
uint sen_tbuf1data0; /* Save area 0 - current frame */
uint sen_tbuf1data1; /* Save area 1 - current frame */
uint sen_tbuf1rba; /* Internal */
uint sen_tbuf1crc; /* Internal */
ushort sen_tbuf1bcnt; /* Internal */
ushort sen_txlen; /* Tx Frame length counter */
ushort sen_iaddr1; /* Individual address filter */
ushort sen_iaddr2;
ushort sen_iaddr3;
ushort sen_iaddr4;
ushort sen_boffcnt; /* Backoff counter */
/* NOTE: Some versions of the manual have the following items
* incorrectly documented. Below is the proper order.
*/
ushort sen_taddrh; /* temp address (MSB) */
ushort sen_taddrm;
ushort sen_taddrl; /* temp address (LSB) */
} scc_enet_t;
#if defined (CONFIG_UCQUICC)
/* uCquicc has the following signals connected to Ethernet:
* 68360 - lxt905
* PA0/RXD1 - rxd
* PA1/TXD1 - txd
* PA8/CLK1 - tclk
* PA9/CLK2 - rclk
* PC0/!RTS1 - t_en
* PC1/!CTS1 - col
* PC5/!CD1 - cd
*/
#define PA_ENET_RXD PA_RXD1
#define PA_ENET_TXD PA_TXD1
#define PA_ENET_TCLK PA_CLK1
#define PA_ENET_RCLK PA_CLK2
#define PC_ENET_TENA PC_RTS1
#define PC_ENET_CLSN PC_CTS1
#define PC_ENET_RENA PC_CD1
/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
* SCC1.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000002c)
#endif /* config_ucquicc */
#ifdef MBX
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use. The TCLK and RCLK seem unique
* to the MBX860 board. Any two of the four available clocks could be
* used, and the MPC860 cookbook manual has an example using different
* clock pins.
*/
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PC_ENET_TENA ((ushort)0x0001)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000003d)
#endif
#ifdef CONFIG_RPXLITE
/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
* this may be unique to the RPX-Lite configuration.
* Note TENA is on Port B.
*/
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00003d00)
#endif
#ifdef CONFIG_BSEIP
/* This ENET stuff is for the MPC823 with ethernet on SCC2.
* This is unique to the BSE ip-Engine board.
*/
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0100)
#define PA_ENET_RCLK ((ushort)0x0200)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
/* BSE uses port B and C bits for PHY control also.
*/
#define PB_BSE_POWERUP ((uint)0x00000004)
#define PB_BSE_FDXDIS ((uint)0x00008000)
#define PC_BSE_LOOPBACK ((ushort)0x0800)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002c00)
#endif
/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* SCC Mode Register (PMSR) as used by Ethernet.
*/
#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
#define BD_ENET_TX_UN ((ushort)0x0002)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
/* SCC as UART
*/
typedef struct scc_uart {
sccp_t scc_genscc;
uint scc_res1; /* Reserved */
uint scc_res2; /* Reserved */
ushort scc_maxidl; /* Maximum idle chars */
ushort scc_idlc; /* temp idle counter */
ushort scc_brkcr; /* Break count register */
ushort scc_parec; /* receive parity error counter */
ushort scc_frmec; /* receive framing error counter */
ushort scc_nosec; /* receive noise counter */
ushort scc_brkec; /* receive break condition counter */
ushort scc_brkln; /* last received break length */
ushort scc_uaddr1; /* UART address character 1 */
ushort scc_uaddr2; /* UART address character 2 */
ushort scc_rtemp; /* Temp storage */
ushort scc_toseq; /* Transmit out of sequence char */
ushort scc_char1; /* control character 1 */
ushort scc_char2; /* control character 2 */
ushort scc_char3; /* control character 3 */
ushort scc_char4; /* control character 4 */
ushort scc_char5; /* control character 5 */
ushort scc_char6; /* control character 6 */
ushort scc_char7; /* control character 7 */
ushort scc_char8; /* control character 8 */
ushort scc_rccm; /* receive control character mask */
ushort scc_rccr; /* receive control character register */
ushort scc_rlbc; /* receive last break character */
} scc_uart_t;
/* SCC Event and Mask registers when it is used as a UART.
*/
#define UART_SCCM_GLR ((ushort)0x1000)
#define UART_SCCM_GLT ((ushort)0x0800)
#define UART_SCCM_AB ((ushort)0x0200)
#define UART_SCCM_IDL ((ushort)0x0100)
#define UART_SCCM_GRA ((ushort)0x0080)
#define UART_SCCM_BRKE ((ushort)0x0040)
#define UART_SCCM_BRKS ((ushort)0x0020)
#define UART_SCCM_CCR ((ushort)0x0008)
#define UART_SCCM_BSY ((ushort)0x0004)
#define UART_SCCM_TX ((ushort)0x0002)
#define UART_SCCM_RX ((ushort)0x0001)
/* The SCC PMSR when used as a UART.
*/
#define SCU_PMSR_FLC ((ushort)0x8000)
#define SCU_PMSR_SL ((ushort)0x4000)
#define SCU_PMSR_CL ((ushort)0x3000)
#define SCU_PMSR_UM ((ushort)0x0c00)
#define SCU_PMSR_FRZ ((ushort)0x0200)
#define SCU_PMSR_RZS ((ushort)0x0100)
#define SCU_PMSR_SYN ((ushort)0x0080)
#define SCU_PMSR_DRT ((ushort)0x0040)
#define SCU_PMSR_PEN ((ushort)0x0010)
#define SCU_PMSR_RPM ((ushort)0x000c)
#define SCU_PMSR_REVP ((ushort)0x0008)
#define SCU_PMSR_TPM ((ushort)0x0003)
#define SCU_PMSR_TEVP ((ushort)0x0003)
/* CPM Transparent mode SCC.
*/
typedef struct scc_trans {
sccp_t st_genscc;
uint st_cpres; /* Preset CRC */
uint st_cmask; /* Constant mask for CRC */
} scc_trans_t;
#define BD_SCC_TX_LAST ((ushort)0x0800)
/* CPM interrupts. There are nearly 32 interrupts generated by CPM
* channels or devices. All of these are presented to the PPC core
* as a single interrupt. The CPM interrupt handler dispatches its
* own handlers, in a similar fashion to the PPC core handler. We
* use the table as defined in the manuals (i.e. no special high
* priority and SCC1 == SCCa, etc...).
*/
/* #define CPMVEC_NR 32 */
/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */
/* #define CPMVEC_SCC1 ((ushort)0x1e) */
/* #define CPMVEC_SCC2 ((ushort)0x1d) */
/* #define CPMVEC_SCC3 ((ushort)0x1c) */
/* #define CPMVEC_SCC4 ((ushort)0x1b) */
/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */
/* #define CPMVEC_TIMER1 ((ushort)0x19) */
/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */
/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */
/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
/* #define CPMVEC_IDMA1 ((ushort)0x15) */
/* #define CPMVEC_IDMA2 ((ushort)0x14) */
/* #define CPMVEC_TIMER2 ((ushort)0x12) */
/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
/* #define CPMVEC_I2C ((ushort)0x10) */
/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */
/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */
/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */
/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */
/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */
/* #define CPMVEC_TIMER4 ((ushort)0x07) */
/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */
/* #define CPMVEC_SPI ((ushort)0x05) */
/* #define CPMVEC_SMC1 ((ushort)0x04) */
/* #define CPMVEC_SMC2 ((ushort)0x03) */
/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */
/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */
/* #define CPMVEC_ERROR ((ushort)0x00) */
extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
/* CPM interrupt configuration vector.
*/
#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
#define CICR_IEN ((uint)0x00000080) /* Int. enable */
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
#endif /* __CPM_360__ */

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arch/m68k/include/asm/contregs.h Normal file
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#ifndef _M68K_CONTREGS_H
#define _M68K_CONTREGS_H
/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
* space. These are for the mmu's context register, etc.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
/* 3=sun3
4=sun4 (as in sun4 sysmaint student book)
c=sun4c (according to davem) */
#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
#define AC_SYNC_ERR 0x60000000 /* c fault type */
#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
#define AC_M_CXR 0x0200 /* shv Context Register */
#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
#define AC_M_RESET 0x0700 /* hv Reset Reg */
#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
#define AC_M_ITR 0x1300 /* hv Index Tag Register */
#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
#endif /* _M68K_CONTREGS_H */

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arch/m68k/include/asm/cputime.h Normal file
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#ifndef __M68K_CPUTIME_H
#define __M68K_CPUTIME_H
#include <asm-generic/cputime.h>
#endif /* __M68K_CPUTIME_H */

5
arch/m68k/include/asm/current.h Normal file
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#ifdef __uClinux__
#include "current_no.h"
#else
#include "current_mm.h"
#endif

6
arch/m68k/include/asm/current_mm.h Normal file
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#ifndef _M68K_CURRENT_H
#define _M68K_CURRENT_H
register struct task_struct *current __asm__("%a2");
#endif /* !(_M68K_CURRENT_H) */

24
arch/m68k/include/asm/current_no.h Normal file
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#ifndef _M68KNOMMU_CURRENT_H
#define _M68KNOMMU_CURRENT_H
/*
* current.h
* (C) Copyright 2000, Lineo, David McCullough <davidm@uclinux.org>
* (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
*
* rather than dedicate a register (as the m68k source does), we
* just keep a global, we should probably just change it all to be
* current and lose _current_task.
*/
#include <linux/thread_info.h>
struct task_struct;
static inline struct task_struct *get_current(void)
{
return(current_thread_info()->task);
}
#define current get_current()
#endif /* _M68KNOMMU_CURRENT_H */

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arch/m68k/include/asm/dbg.h Normal file
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#define DEBUG 1
#ifdef CONFIG_COLDFIRE
#define BREAK asm volatile ("halt")
#else
#define BREAK *(volatile unsigned char *)0xdeadbee0 = 0
#endif

5
arch/m68k/include/asm/delay.h Normal file
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#ifdef __uClinux__
#include "delay_no.h"
#else
#include "delay_mm.h"
#endif

57
arch/m68k/include/asm/delay_mm.h Normal file
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#ifndef _M68K_DELAY_H
#define _M68K_DELAY_H
#include <asm/param.h>
/*
* Copyright (C) 1994 Hamish Macdonald
*
* Delay routines, using a pre-computed "loops_per_jiffy" value.
*/
static inline void __delay(unsigned long loops)
{
__asm__ __volatile__ ("1: subql #1,%0; jcc 1b"
: "=d" (loops) : "0" (loops));
}
extern void __bad_udelay(void);
/*
* Use only for very small delays ( < 1 msec). Should probably use a
* lookup table, really, as the multiplications take much too long with
* short delays. This is a "reasonable" implementation, though (and the
* first constant multiplications gets optimized away if the delay is
* a constant)
*/
static inline void __const_udelay(unsigned long xloops)
{
unsigned long tmp;
__asm__ ("mulul %2,%0:%1"
: "=d" (xloops), "=d" (tmp)
: "d" (xloops), "1" (loops_per_jiffy));
__delay(xloops * HZ);
}
static inline void __udelay(unsigned long usecs)
{
__const_udelay(usecs * 4295); /* 2**32 / 1000000 */
}
#define udelay(n) (__builtin_constant_p(n) ? \
((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 4295)) : \
__udelay(n))
static inline unsigned long muldiv(unsigned long a, unsigned long b,
unsigned long c)
{
unsigned long tmp;
__asm__ ("mulul %2,%0:%1; divul %3,%0:%1"
: "=d" (tmp), "=d" (a)
: "d" (b), "d" (c), "1" (a));
return a;
}
#endif /* defined(_M68K_DELAY_H) */

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arch/m68k/include/asm/delay_no.h Normal file
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#ifndef _M68KNOMMU_DELAY_H
#define _M68KNOMMU_DELAY_H
/*
* Copyright (C) 1994 Hamish Macdonald
* Copyright (C) 2004 Greg Ungerer <gerg@snapgear.com>
*/
#include <asm/param.h>
static inline void __delay(unsigned long loops)
{
#if defined(CONFIG_COLDFIRE)
/* The coldfire runs this loop at significantly different speeds
* depending upon long word alignment or not. We'll pad it to
* long word alignment which is the faster version.
* The 0x4a8e is of course a 'tstl %fp' instruction. This is better
* than using a NOP (0x4e71) instruction because it executes in one
* cycle not three and doesn't allow for an arbitary delay waiting
* for bus cycles to finish. Also fp/a6 isn't likely to cause a
* stall waiting for the register to become valid if such is added
* to the coldfire at some stage.
*/
__asm__ __volatile__ ( ".balignw 4, 0x4a8e\n\t"
"1: subql #1, %0\n\t"
"jcc 1b"
: "=d" (loops) : "0" (loops));
#else
__asm__ __volatile__ ( "1: subql #1, %0\n\t"
"jcc 1b"
: "=d" (loops) : "0" (loops));
#endif
}
/*
* Ideally we use a 32*32->64 multiply to calculate the number of
* loop iterations, but the older standard 68k and ColdFire do not
* have this instruction. So for them we have a clsoe approximation
* loop using 32*32->32 multiplies only. This calculation based on
* the ARM version of delay.
*
* We want to implement:
*
* loops = (usecs * 0x10c6 * HZ * loops_per_jiffy) / 2^32
*/
#define HZSCALE (268435456 / (1000000/HZ))
extern unsigned long loops_per_jiffy;
static inline void _udelay(unsigned long usecs)
{
#if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \
defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \
defined(CONFIG_COLDFIRE)
__delay((((usecs * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6);
#else
unsigned long tmp;
usecs *= 4295; /* 2**32 / 1000000 */
__asm__ ("mulul %2,%0:%1"
: "=d" (usecs), "=d" (tmp)
: "d" (usecs), "1" (loops_per_jiffy*HZ));
__delay(usecs);
#endif
}
/*
* Moved the udelay() function into library code, no longer inlined.
* I had to change the algorithm because we are overflowing now on
* the faster ColdFire parts. The code is a little bigger, so it makes
* sense to library it.
*/
extern void udelay(unsigned long usecs);
#endif /* defined(_M68KNOMMU_DELAY_H) */

7
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/*
* Arch specific extensions to struct device
*
* This file is released under the GPLv2
*/
#include <asm-generic/device.h>

5
arch/m68k/include/asm/div64.h Normal file
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#ifdef __uClinux__
#include "div64_no.h"
#else
#include "div64_mm.h"
#endif

28
arch/m68k/include/asm/div64_mm.h Normal file
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#ifndef _M68K_DIV64_H
#define _M68K_DIV64_H
#include <linux/types.h>
/* n = n / base; return rem; */
#define do_div(n, base) ({ \
union { \
unsigned long n32[2]; \
unsigned long long n64; \
} __n; \
unsigned long __rem, __upper; \
\
__n.n64 = (n); \
if ((__upper = __n.n32[0])) { \
asm ("divul.l %2,%1:%0" \
: "=d" (__n.n32[0]), "=d" (__upper) \
: "d" (base), "0" (__n.n32[0])); \
} \
asm ("divu.l %2,%1:%0" \
: "=d" (__n.n32[1]), "=d" (__rem) \
: "d" (base), "1" (__upper), "0" (__n.n32[1])); \
(n) = __n.n64; \
__rem; \
})
#endif /* _M68K_DIV64_H */

1
arch/m68k/include/asm/div64_no.h Normal file
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@@ -0,0 +1 @@
#include <asm-generic/div64.h>

5
arch/m68k/include/asm/dma-mapping.h Normal file
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#ifdef __uClinux__
#include "dma-mapping_no.h"
#else
#include "dma-mapping_mm.h"
#endif

112
arch/m68k/include/asm/dma-mapping_mm.h Normal file
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#ifndef _M68K_DMA_MAPPING_H
#define _M68K_DMA_MAPPING_H
#include <asm/cache.h>
struct scatterlist;
#ifndef CONFIG_MMU_SUN3
static inline int dma_supported(struct device *dev, u64 mask)
{
return 1;
}
static inline int dma_set_mask(struct device *dev, u64 mask)
{
return 0;
}
static inline int dma_get_cache_alignment(void)
{
return 1 << L1_CACHE_SHIFT;
}
static inline int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return 0;
}
extern void *dma_alloc_coherent(struct device *, size_t,
dma_addr_t *, gfp_t);
extern void dma_free_coherent(struct device *, size_t,
void *, dma_addr_t);
static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
dma_addr_t *handle, gfp_t flag)
{
return dma_alloc_coherent(dev, size, handle, flag);
}
static inline void dma_free_noncoherent(struct device *dev, size_t size,
void *addr, dma_addr_t handle)
{
dma_free_coherent(dev, size, addr, handle);
}
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction dir)
{
/* we use coherent allocation, so not much to do here. */
}
extern dma_addr_t dma_map_single(struct device *, void *, size_t,
enum dma_data_direction);
static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
size_t size, enum dma_data_direction dir)
{
}
extern dma_addr_t dma_map_page(struct device *, struct page *,
unsigned long, size_t size,
enum dma_data_direction);
static inline void dma_unmap_page(struct device *dev, dma_addr_t address,
size_t size, enum dma_data_direction dir)
{
}
extern int dma_map_sg(struct device *, struct scatterlist *, int,
enum dma_data_direction);
static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
int nhwentries, enum dma_data_direction dir)
{
}
extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t,
enum dma_data_direction);
extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
enum dma_data_direction);
static inline void dma_sync_single_range_for_device(struct device *dev,
dma_addr_t dma_handle, unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything for now */
dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
}
static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
size_t size, enum dma_data_direction dir)
{
}
static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir)
{
}
static inline void dma_sync_single_range_for_cpu(struct device *dev,
dma_addr_t dma_handle, unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything for now */
dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
}
static inline int dma_mapping_error(struct device *dev, dma_addr_t handle)
{
return 0;
}
#else
#include <asm-generic/dma-mapping-broken.h>
#endif
#endif /* _M68K_DMA_MAPPING_H */

10
arch/m68k/include/asm/dma-mapping_no.h Normal file
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#ifndef _M68KNOMMU_DMA_MAPPING_H
#define _M68KNOMMU_DMA_MAPPING_H
#ifdef CONFIG_PCI
#include <asm-generic/dma-mapping.h>
#else
#include <asm-generic/dma-mapping-broken.h>
#endif
#endif /* _M68KNOMMU_DMA_MAPPING_H */

5
arch/m68k/include/asm/dma.h Normal file
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#ifdef __uClinux__
#include "dma_no.h"
#else
#include "dma_mm.h"
#endif

16
arch/m68k/include/asm/dma_mm.h Normal file
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#ifndef _M68K_DMA_H
#define _M68K_DMA_H 1
/* it's useless on the m68k, but unfortunately needed by the new
bootmem allocator (but this should do it for this) */
#define MAX_DMA_ADDRESS PAGE_OFFSET
#define MAX_DMA_CHANNELS 8
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
#define isa_dma_bridge_buggy (0)
#endif /* _M68K_DMA_H */

494
arch/m68k/include/asm/dma_no.h Normal file
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#ifndef _M68K_DMA_H
#define _M68K_DMA_H 1
//#define DMA_DEBUG 1
#ifdef CONFIG_COLDFIRE
/*
* ColdFire DMA Model:
* ColdFire DMA supports two forms of DMA: Single and Dual address. Single
* address mode emits a source address, and expects that the device will either
* pick up the data (DMA READ) or source data (DMA WRITE). This implies that
* the device will place data on the correct byte(s) of the data bus, as the
* memory transactions are always 32 bits. This implies that only 32 bit
* devices will find single mode transfers useful. Dual address DMA mode
* performs two cycles: source read and destination write. ColdFire will
* align the data so that the device will always get the correct bytes, thus
* is useful for 8 and 16 bit devices. This is the mode that is supported
* below.
*
* AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
*
* AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
*
* APR/18/2002 : added proper support for MCF5272 DMA controller.
* Arthur Shipkowski (art@videon-central.com)
*/
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfdma.h>
/*
* Set number of channels of DMA on ColdFire for different implementations.
*/
#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
#define MAX_M68K_DMA_CHANNELS 4
#elif defined(CONFIG_M5272)
#define MAX_M68K_DMA_CHANNELS 1
#elif defined(CONFIG_M532x)
#define MAX_M68K_DMA_CHANNELS 0
#else
#define MAX_M68K_DMA_CHANNELS 2
#endif
extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
#if !defined(CONFIG_M5272)
#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
/* I/O to memory, 8 bits, mode */
#define DMA_MODE_READ 0
/* memory to I/O, 8 bits, mode */
#define DMA_MODE_WRITE 1
/* I/O to memory, 16 bits, mode */
#define DMA_MODE_READ_WORD 2
/* memory to I/O, 16 bits, mode */
#define DMA_MODE_WRITE_WORD 3
/* I/O to memory, 32 bits, mode */
#define DMA_MODE_READ_LONG 4
/* memory to I/O, 32 bits, mode */
#define DMA_MODE_WRITE_LONG 5
/* I/O to memory, 8 bits, single-address-mode */
#define DMA_MODE_READ_SINGLE 8
/* memory to I/O, 8 bits, single-address-mode */
#define DMA_MODE_WRITE_SINGLE 9
/* I/O to memory, 16 bits, single-address-mode */
#define DMA_MODE_READ_WORD_SINGLE 10
/* memory to I/O, 16 bits, single-address-mode */
#define DMA_MODE_WRITE_WORD_SINGLE 11
/* I/O to memory, 32 bits, single-address-mode */
#define DMA_MODE_READ_LONG_SINGLE 12
/* memory to I/O, 32 bits, single-address-mode */
#define DMA_MODE_WRITE_LONG_SINGLE 13
#else /* CONFIG_M5272 is defined */
/* Source static-address mode */
#define DMA_MODE_SRC_SA_BIT 0x01
/* Two bits to select between all four modes */
#define DMA_MODE_SSIZE_MASK 0x06
/* Offset to shift bits in */
#define DMA_MODE_SSIZE_OFF 0x01
/* Destination static-address mode */
#define DMA_MODE_DES_SA_BIT 0x10
/* Two bits to select between all four modes */
#define DMA_MODE_DSIZE_MASK 0x60
/* Offset to shift bits in */
#define DMA_MODE_DSIZE_OFF 0x05
/* Size modifiers */
#define DMA_MODE_SIZE_LONG 0x00
#define DMA_MODE_SIZE_BYTE 0x01
#define DMA_MODE_SIZE_WORD 0x02
#define DMA_MODE_SIZE_LINE 0x03
/*
* Aliases to help speed quick ports; these may be suboptimal, however. They
* do not include the SINGLE mode modifiers since the MCF5272 does not have a
* mode where the device is in control of its addressing.
*/
/* I/O to memory, 8 bits, mode */
#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 8 bits, mode */
#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
/* I/O to memory, 16 bits, mode */
#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 16 bits, mode */
#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
/* I/O to memory, 32 bits, mode */
#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 32 bits, mode */
#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
#endif /* !defined(CONFIG_M5272) */
#if !defined(CONFIG_M5272)
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("enable_dma(dmanr=%d)\n", dmanr);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
}
static __inline__ void disable_dma(unsigned int dmanr)
{
volatile unsigned short *dmawp;
volatile unsigned char *dmapb;
#ifdef DMA_DEBUG
printk("disable_dma(dmanr=%d)\n", dmanr);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmapb = (unsigned char *) dma_base_addr[dmanr];
/* Turn off external requests, and stop any DMA in progress */
dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
}
/*
* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while interrupts are disabled! ---
*
* This is a NOP for ColdFire. Provide a stub for compatibility.
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
volatile unsigned char *dmabp;
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
#endif
dmabp = (unsigned char *) dma_base_addr[dmanr];
dmawp = (unsigned short *) dma_base_addr[dmanr];
// Clear config errors
dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
// Set command register
dmawp[MCFDMA_DCR] =
MCFDMA_DCR_INT | // Enable completion irq
MCFDMA_DCR_CS | // Force one xfer per request
MCFDMA_DCR_AA | // Enable auto alignment
// single-address-mode
((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
// sets s_rw (-> r/w) high if Memory to I/0
((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
// Memory to I/O or I/O to Memory
((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
// 32 bit, 16 bit or 8 bit transfers
((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
MCFDMA_DCR_SSIZE_BYTE)) |
((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
MCFDMA_DCR_DSIZE_BYTE));
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
(int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
#endif
}
/* Set transfer address for specific DMA channel */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
volatile unsigned short *dmawp;
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmalp = (unsigned int *) dma_base_addr[dmanr];
// Determine which address registers are used for memory/device accesses
if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
// Source incrementing, must be memory
dmalp[MCFDMA_SAR] = a;
// Set dest address, must be device
dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
} else {
// Destination incrementing, must be memory
dmalp[MCFDMA_DAR] = a;
// Set source address, must be device
dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
}
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
(int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
(int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
#endif
}
/*
* Specific for Coldfire - sets device address.
* Should be called after the mode set call, and before set DMA address.
*/
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
{
#ifdef DMA_DEBUG
printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dma_device_address[dmanr] = a;
}
/*
* NOTE 2: "count" represents _bytes_.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmawp[MCFDMA_BCR] = (unsigned short)count;
}
/*
* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* Otherwise, it returns the number of _bytes_ left to transfer.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
volatile unsigned short *dmawp;
unsigned short count;
#ifdef DMA_DEBUG
printk("get_dma_residue(dmanr=%d)\n", dmanr);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
count = dmawp[MCFDMA_BCR];
return((int) count);
}
#else /* CONFIG_M5272 is defined */
/*
* The MCF5272 DMA controller is very different than the controller defined above
* in terms of register mapping. For instance, with the exception of the 16-bit
* interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
*
* The big difference, however, is the lack of device-requested DMA. All modes
* are dual address transfer, and there is no 'device' setup or direction bit.
* You can DMA between a device and memory, between memory and memory, or even between
* two devices directly, with any combination of incrementing and non-incrementing
* addresses you choose. This puts a crimp in distinguishing between the 'device
* address' set up by set_dma_device_addr.
*
* Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
* which will act exactly as above in -- it will look to see if the source is set to
* autoincrement, and if so it will make the source use the set_dma_addr value and the
* destination the set_dma_device_addr value. Otherwise the source will be set to the
* set_dma_device_addr value and the destination will get the set_dma_addr value.
*
* The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
* and make it explicit. Depending on what you're doing, one of these two should work
* for you, but don't mix them in the same transfer setup.
*/
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("enable_dma(dmanr=%d)\n", dmanr);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
}
static __inline__ void disable_dma(unsigned int dmanr)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("disable_dma(dmanr=%d)\n", dmanr);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
/* Turn off external requests, and stop any DMA in progress */
dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
}
/*
* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while interrupts are disabled! ---
*
* This is a NOP for ColdFire. Provide a stub for compatibility.
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
volatile unsigned int *dmalp;
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
dmawp = (unsigned short *) dma_base_addr[dmanr];
// Clear config errors
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
// Set command register
dmalp[MCFDMA_DMR] =
MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting
MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data.
MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data.
// source static-address-mode
((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
// dest static-address-mode
((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
// burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272
(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR],
(int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
#endif
}
/* Set transfer address for specific DMA channel */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
// Determine which address registers are used for memory/device accesses
if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
// Source incrementing, must be memory
dmalp[MCFDMA_DSAR] = a;
// Set dest address, must be device
dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
} else {
// Destination incrementing, must be memory
dmalp[MCFDMA_DDAR] = a;
// Set source address, must be device
dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
}
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR],
(int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
(int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
#endif
}
/*
* Specific for Coldfire - sets device address.
* Should be called after the mode set call, and before set DMA address.
*/
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
{
#ifdef DMA_DEBUG
printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dma_device_address[dmanr] = a;
}
/*
* NOTE 2: "count" represents _bytes_.
*
* NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
dmalp[MCFDMA_DBCR] = count;
}
/*
* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* Otherwise, it returns the number of _bytes_ left to transfer.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
volatile unsigned int *dmalp;
unsigned int count;
#ifdef DMA_DEBUG
printk("get_dma_residue(dmanr=%d)\n", dmanr);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
count = dmalp[MCFDMA_DBCR];
return(count);
}
#endif /* !defined(CONFIG_M5272) */
#endif /* CONFIG_COLDFIRE */
#define MAX_DMA_CHANNELS 8
/* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any
occurrence should be flagged as an error. */
/* under 2.4 it is actually needed by the new bootmem allocator */
#define MAX_DMA_ADDRESS PAGE_OFFSET
/* These are in kernel/dma.c: */
extern int request_dma(unsigned int dmanr, const char *device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
#endif /* _M68K_DMA_H */

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arch/m68k/include/asm/dsp56k.h Normal file
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/*
* linux/include/asm-m68k/dsp56k.h - defines and declarations for
* DSP56k device driver
*
* Copyright (C) 1996,1997 Fredrik Noring, lars brinkhoff & Tomas Berndtsson
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/* Used for uploading DSP binary code */
struct dsp56k_upload {
int len;
char __user *bin;
};
/* For the DSP host flags */
struct dsp56k_host_flags {
int dir; /* Bit field. 1 = write output bit, 0 = do nothing.
* 0x0000 means reading only, 0x0011 means
* writing the bits stored in `out' on HF0 and HF1.
* Note that HF2 and HF3 can only be read.
*/
int out; /* Bit field like above. */
int status; /* Host register's current state is returned */
};
/* ioctl command codes */
#define DSP56K_UPLOAD 1 /* Upload DSP binary program */
#define DSP56K_SET_TX_WSIZE 2 /* Host transmit word size (1-4) */
#define DSP56K_SET_RX_WSIZE 3 /* Host receive word size (1-4) */
#define DSP56K_HOST_FLAGS 4 /* Host flag registers */
#define DSP56K_HOST_CMD 5 /* Trig Host Command (0-31) */

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/*
* include/asm-m68k/dma.h
*
* Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
*
* Hacked to fit Sun3x needs by Thomas Bogendoerfer
*/
#ifndef __M68K_DVMA_H
#define __M68K_DVMA_H
#define DVMA_PAGE_SHIFT 13
#define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT)
#define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
#define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE)
extern void dvma_init(void);
extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
int len);
#define dvma_malloc(x) dvma_malloc_align(x, 0)
#define dvma_map(x, y) dvma_map_align(x, y, 0)
#define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
#define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
extern unsigned long dvma_map_align(unsigned long kaddr, int len,
int align);
extern void *dvma_malloc_align(unsigned long len, unsigned long align);
extern void dvma_unmap(void *baddr);
extern void dvma_free(void *vaddr);
#ifdef CONFIG_SUN3
/* sun3 dvma page support */
/* memory and pmegs potentially reserved for dvma */
#define DVMA_PMEG_START 10
#define DVMA_PMEG_END 16
#define DVMA_START 0xf00000
#define DVMA_END 0xfe0000
#define DVMA_SIZE (DVMA_END-DVMA_START)
#define IOMMU_TOTAL_ENTRIES 128
#define IOMMU_ENTRIES 120
/* empirical kludge -- dvma regions only seem to work right on 0x10000
byte boundaries */
#define DVMA_REGION_SIZE 0x10000
#define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
~(DVMA_REGION_SIZE-1))
/* virt <-> phys conversions */
#define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
#define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
#define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
#define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
#define dvma_vtob(x) dvma_vtop(x)
#define dvma_btov(x) dvma_ptov(x)
static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
int len)
{
return 0;
}
#else /* Sun3x */
/* sun3x dvma page support */
#define DVMA_START 0x0
#define DVMA_END 0xf00000
#define DVMA_SIZE (DVMA_END-DVMA_START)
#define IOMMU_TOTAL_ENTRIES 2048
/* the prom takes the top meg */
#define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
#define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
#define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
/* everything below this line is specific to dma used for the onboard
ESP scsi on sun3x */
/* Structure to describe the current status of DMA registers on the Sparc */
struct sparc_dma_registers {
__volatile__ unsigned long cond_reg; /* DMA condition register */
__volatile__ unsigned long st_addr; /* Start address of this transfer */
__volatile__ unsigned long cnt; /* How many bytes to transfer */
__volatile__ unsigned long dma_test; /* DMA test register */
};
/* DVMA chip revisions */
enum dvma_rev {
dvmarev0,
dvmaesc1,
dvmarev1,
dvmarev2,
dvmarev3,
dvmarevplus,
dvmahme
};
#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
/* Linux DMA information structure, filled during probe. */
struct Linux_SBus_DMA {
struct Linux_SBus_DMA *next;
struct linux_sbus_device *SBus_dev;
struct sparc_dma_registers *regs;
/* Status, misc info */
int node; /* Prom node for this DMA device */
int running; /* Are we doing DMA now? */
int allocated; /* Are we "owned" by anyone yet? */
/* Transfer information. */
unsigned long addr; /* Start address of current transfer */
int nbytes; /* Size of current transfer */
int realbytes; /* For splitting up large transfers, etc. */
/* DMA revision */
enum dvma_rev revision;
};
extern struct Linux_SBus_DMA *dma_chain;
/* Broken hardware... */
#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
/* Fields in the cond_reg register */
/* First, the version identification bits */
#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
#define DMA_VERS0 0x00000000 /* Sunray DMA version */
#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
#define DMA_VERS1 0x80000000 /* DMA rev 1 */
#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
#define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
/* Values describing the burst-size property from the PROM */
#define DMA_BURST1 0x01
#define DMA_BURST2 0x02
#define DMA_BURST4 0x04
#define DMA_BURST8 0x08
#define DMA_BURST16 0x10
#define DMA_BURST32 0x20
#define DMA_BURST64 0x40
#define DMA_BURSTBITS 0x7f
/* Determine highest possible final transfer address given a base */
#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
/* Yes, I hack a lot of elisp in my spare time... */
#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
#define DMA_BEGINDMA_W(regs) \
((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
#define DMA_BEGINDMA_R(regs) \
((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
/* For certain DMA chips, we need to disable ints upon irq entry
* and turn them back on when we are done. So in any ESP interrupt
* handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
* when leaving the handler. You have been warned...
*/
#define DMA_IRQ_ENTRY(dma, dregs) do { \
if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
} while (0)
#define DMA_IRQ_EXIT(dma, dregs) do { \
if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
} while(0)
/* Reset the friggin' thing... */
#define DMA_RESET(dma) do { \
struct sparc_dma_registers *regs = dma->regs; \
/* Let the current FIFO drain itself */ \
sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
/* Reset the logic */ \
regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
__delay(400); /* let the bits set ;) */ \
regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
/* Enable FAST transfers if available */ \
if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
dma->running = 0; \
} while(0)
#endif /* !CONFIG_SUN3 */
#endif /* !(__M68K_DVMA_H) */

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#ifdef __uClinux__
#include "elf_no.h"
#else
#include "elf_mm.h"
#endif

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arch/m68k/include/asm/elf_mm.h Normal file
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#ifndef __ASMm68k_ELF_H
#define __ASMm68k_ELF_H
/*
* ELF register definitions..
*/
#include <asm/ptrace.h>
#include <asm/user.h>
/*
* 68k ELF relocation types
*/
#define R_68K_NONE 0
#define R_68K_32 1
#define R_68K_16 2
#define R_68K_8 3
#define R_68K_PC32 4
#define R_68K_PC16 5
#define R_68K_PC8 6
#define R_68K_GOT32 7
#define R_68K_GOT16 8
#define R_68K_GOT8 9
#define R_68K_GOT32O 10
#define R_68K_GOT16O 11
#define R_68K_GOT8O 12
#define R_68K_PLT32 13
#define R_68K_PLT16 14
#define R_68K_PLT8 15
#define R_68K_PLT32O 16
#define R_68K_PLT16O 17
#define R_68K_PLT8O 18
#define R_68K_COPY 19
#define R_68K_GLOB_DAT 20
#define R_68K_JMP_SLOT 21
#define R_68K_RELATIVE 22
typedef unsigned long elf_greg_t;
#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_m68kfp_struct elf_fpregset_t;
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ((x)->e_machine == EM_68K)
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2MSB
#define ELF_ARCH EM_68K
/* For SVR4/m68k the function pointer to be registered with `atexit' is
passed in %a1. Although my copy of the ABI has no such statement, it
is actually used on ASV. */
#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
#define USE_ELF_CORE_DUMP
#ifndef CONFIG_SUN3
#define ELF_EXEC_PAGESIZE 4096
#else
#define ELF_EXEC_PAGESIZE 8192
#endif
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#ifndef CONFIG_SUN3
#define ELF_ET_DYN_BASE 0xD0000000UL
#else
#define ELF_ET_DYN_BASE 0x0D800000UL
#endif
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
/* Bleech. */ \
pr_reg[0] = regs->d1; \
pr_reg[1] = regs->d2; \
pr_reg[2] = regs->d3; \
pr_reg[3] = regs->d4; \
pr_reg[4] = regs->d5; \
pr_reg[7] = regs->a0; \
pr_reg[8] = regs->a1; \
pr_reg[9] = regs->a2; \
pr_reg[14] = regs->d0; \
pr_reg[15] = rdusp(); \
pr_reg[16] = regs->orig_d0; \
pr_reg[17] = regs->sr; \
pr_reg[18] = regs->pc; \
pr_reg[19] = (regs->format << 12) | regs->vector; \
{ \
struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
pr_reg[5] = sw->d6; \
pr_reg[6] = sw->d7; \
pr_reg[10] = sw->a3; \
pr_reg[11] = sw->a4; \
pr_reg[12] = sw->a5; \
pr_reg[13] = sw->a6; \
}
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. */
#define ELF_HWCAP (0)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo. */
#define ELF_PLATFORM (NULL)
#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
#endif

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#ifndef __ASMm68k_ELF_H
#define __ASMm68k_ELF_H
/*
* ELF register definitions..
*/
#include <asm/ptrace.h>
#include <asm/user.h>
/*
* 68k ELF relocation types
*/
#define R_68K_NONE 0
#define R_68K_32 1
#define R_68K_16 2
#define R_68K_8 3
#define R_68K_PC32 4
#define R_68K_PC16 5
#define R_68K_PC8 6
#define R_68K_GOT32 7
#define R_68K_GOT16 8
#define R_68K_GOT8 9
#define R_68K_GOT32O 10
#define R_68K_GOT16O 11
#define R_68K_GOT8O 12
#define R_68K_PLT32 13
#define R_68K_PLT16 14
#define R_68K_PLT8 15
#define R_68K_PLT32O 16
#define R_68K_PLT16O 17
#define R_68K_PLT8O 18
#define R_68K_COPY 19
#define R_68K_GLOB_DAT 20
#define R_68K_JMP_SLOT 21
#define R_68K_RELATIVE 22
typedef unsigned long elf_greg_t;
#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_m68kfp_struct elf_fpregset_t;
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ((x)->e_machine == EM_68K)
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2MSB
#define ELF_ARCH EM_68K
/* For SVR4/m68k the function pointer to be registered with `atexit' is
passed in %a1. Although my copy of the ABI has no such statement, it
is actually used on ASV. */
#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#define ELF_ET_DYN_BASE 0xD0000000UL
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
/* Bleech. */ \
pr_reg[0] = regs->d1; \
pr_reg[1] = regs->d2; \
pr_reg[2] = regs->d3; \
pr_reg[3] = regs->d4; \
pr_reg[4] = regs->d5; \
pr_reg[7] = regs->a0; \
pr_reg[8] = regs->a1; \
pr_reg[14] = regs->d0; \
pr_reg[15] = rdusp(); \
pr_reg[16] = 0 /* regs->orig_d0 */; \
pr_reg[17] = regs->sr; \
pr_reg[18] = regs->pc; \
/* pr_reg[19] = (regs->format << 12) | regs->vector; */ \
{ \
struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
pr_reg[5] = sw->d6; \
pr_reg[6] = sw->d7; \
pr_reg[10] = sw->a3; \
pr_reg[11] = sw->a4; \
pr_reg[12] = sw->a5; \
pr_reg[13] = sw->a6; \
}
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. */
#define ELF_HWCAP (0)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo. */
#define ELF_PLATFORM (NULL)
#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
#endif

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arch/m68k/include/asm/elia.h Normal file
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/****************************************************************************/
/*
* elia.h -- Lineo (formerly Moreton Bay) eLIA platform support.
*
* (C) Copyright 1999-2000, Moreton Bay (www.moreton.com.au)
* (C) Copyright 1999-2000, Lineo (www.lineo.com)
*/
/****************************************************************************/
#ifndef elia_h
#define elia_h
/****************************************************************************/
#include <asm/coldfire.h>
#ifdef CONFIG_eLIA
/*
* The serial port DTR and DCD lines are also on the Parallel I/O
* as well, so define those too.
*/
#define eLIA_DCD1 0x0001
#define eLIA_DCD0 0x0002
#define eLIA_DTR1 0x0004
#define eLIA_DTR0 0x0008
#define eLIA_PCIRESET 0x0020
/*
* Kernel macros to set and unset the LEDs.
*/
#ifndef __ASSEMBLY__
extern unsigned short ppdata;
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_eLIA */
/****************************************************************************/
#endif /* elia_h */

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arch/m68k/include/asm/emergency-restart.h Normal file
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#ifndef _ASM_EMERGENCY_RESTART_H
#define _ASM_EMERGENCY_RESTART_H
#include <asm-generic/emergency-restart.h>
#endif /* _ASM_EMERGENCY_RESTART_H */

5
arch/m68k/include/asm/entry.h Normal file
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#ifdef __uClinux__
#include "entry_no.h"
#else
#include "entry_mm.h"
#endif

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#ifndef __M68K_ENTRY_H
#define __M68K_ENTRY_H
#include <asm/setup.h>
#include <asm/page.h>
/*
* Stack layout in 'ret_from_exception':
*
* This allows access to the syscall arguments in registers d1-d5
*
* 0(sp) - d1
* 4(sp) - d2
* 8(sp) - d3
* C(sp) - d4
* 10(sp) - d5
* 14(sp) - a0
* 18(sp) - a1
* 1C(sp) - a2
* 20(sp) - d0
* 24(sp) - orig_d0
* 28(sp) - stack adjustment
* 2C(sp) - sr
* 2E(sp) - pc
* 32(sp) - format & vector
*/
/*
* 97/05/14 Andreas: Register %a2 is now set to the current task throughout
* the whole kernel.
*/
/* the following macro is used when enabling interrupts */
#if defined(MACH_ATARI_ONLY)
/* block out HSYNC on the atari */
#define ALLOWINT (~0x400)
#define MAX_NOINT_IPL 3
#else
/* portable version */
#define ALLOWINT (~0x700)
#define MAX_NOINT_IPL 0
#endif /* machine compilation types */
#ifdef __ASSEMBLY__
#define curptr a2
LFLUSH_I_AND_D = 0x00000808
LSIGTRAP = 5
/* process bits for task_struct.ptrace */
PT_TRACESYS_OFF = 3
PT_TRACESYS_BIT = 1
PT_PTRACED_OFF = 3
PT_PTRACED_BIT = 0
PT_DTRACE_OFF = 3
PT_DTRACE_BIT = 2
#define SAVE_ALL_INT save_all_int
#define SAVE_ALL_SYS save_all_sys
#define RESTORE_ALL restore_all
/*
* This defines the normal kernel pt-regs layout.
*
* regs a3-a6 and d6-d7 are preserved by C code
* the kernel doesn't mess with usp unless it needs to
*/
/*
* a -1 in the orig_d0 field signifies
* that the stack frame is NOT for syscall
*/
.macro save_all_int
clrl %sp@- | stk_adj
pea -1:w | orig d0
movel %d0,%sp@- | d0
moveml %d1-%d5/%a0-%a1/%curptr,%sp@-
.endm
.macro save_all_sys
clrl %sp@- | stk_adj
movel %d0,%sp@- | orig d0
movel %d0,%sp@- | d0
moveml %d1-%d5/%a0-%a1/%curptr,%sp@-
.endm
.macro restore_all
moveml %sp@+,%a0-%a1/%curptr/%d1-%d5
movel %sp@+,%d0
addql #4,%sp | orig d0
addl %sp@+,%sp | stk adj
rte
.endm
#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */
#define SAVE_SWITCH_STACK save_switch_stack
#define RESTORE_SWITCH_STACK restore_switch_stack
#define GET_CURRENT(tmp) get_current tmp
.macro save_switch_stack
moveml %a3-%a6/%d6-%d7,%sp@-
.endm
.macro restore_switch_stack
moveml %sp@+,%a3-%a6/%d6-%d7
.endm
.macro get_current reg=%d0
movel %sp,\reg
andw #-THREAD_SIZE,\reg
movel \reg,%curptr
movel %curptr@,%curptr
.endm
#else /* C source */
#define STR(X) STR1(X)
#define STR1(X) #X
#define PT_OFF_ORIG_D0 0x24
#define PT_OFF_FORMATVEC 0x32
#define PT_OFF_SR 0x2C
#define SAVE_ALL_INT \
"clrl %%sp@-;" /* stk_adj */ \
"pea -1:w;" /* orig d0 = -1 */ \
"movel %%d0,%%sp@-;" /* d0 */ \
"moveml %%d1-%%d5/%%a0-%%a2,%%sp@-"
#define GET_CURRENT(tmp) \
"movel %%sp,"#tmp"\n\t" \
"andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
"movel "#tmp",%%a2\n\t" \
"movel %%a2@,%%a2"
#endif
#endif /* __M68K_ENTRY_H */

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#ifndef __M68KNOMMU_ENTRY_H
#define __M68KNOMMU_ENTRY_H
#include <asm/setup.h>
#include <asm/page.h>
/*
* Stack layout in 'ret_from_exception':
*
* This allows access to the syscall arguments in registers d1-d5
*
* 0(sp) - d1
* 4(sp) - d2
* 8(sp) - d3
* C(sp) - d4
* 10(sp) - d5
* 14(sp) - a0
* 18(sp) - a1
* 1C(sp) - a2
* 20(sp) - d0
* 24(sp) - orig_d0
* 28(sp) - stack adjustment
* 2C(sp) - [ sr ] [ format & vector ]
* 2E(sp) - [ pc-hiword ] [ sr ]
* 30(sp) - [ pc-loword ] [ pc-hiword ]
* 32(sp) - [ format & vector ] [ pc-loword ]
* ^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^
* M68K COLDFIRE
*/
#define ALLOWINT 0xf8ff
#ifdef __ASSEMBLY__
/* process bits for task_struct.flags */
PF_TRACESYS_OFF = 3
PF_TRACESYS_BIT = 5
PF_PTRACED_OFF = 3
PF_PTRACED_BIT = 4
PF_DTRACE_OFF = 1
PF_DTRACE_BIT = 5
LENOSYS = 38
#define SWITCH_STACK_SIZE (6*4+4) /* Includes return address */
/*
* This defines the normal kernel pt-regs layout.
*
* regs are a2-a6 and d6-d7 preserved by C code
* the kernel doesn't mess with usp unless it needs to
*/
#ifdef CONFIG_COLDFIRE
/*
* This is made a little more tricky on the ColdFire. There is no
* separate kernel and user stack pointers. Need to artificially
* construct a usp in software... When doing this we need to disable
* interrupts, otherwise bad things could happen.
*/
.macro SAVE_ALL
move #0x2700,%sr /* disable intrs */
btst #5,%sp@(2) /* from user? */
bnes 6f /* no, skip */
movel %sp,sw_usp /* save user sp */
addql #8,sw_usp /* remove exception */
movel sw_ksp,%sp /* kernel sp */
subql #8,%sp /* room for exception */
clrl %sp@- /* stkadj */
movel %d0,%sp@- /* orig d0 */
movel %d0,%sp@- /* d0 */
lea %sp@(-32),%sp /* space for 8 regs */
moveml %d1-%d5/%a0-%a2,%sp@
movel sw_usp,%a0 /* get usp */
movel %a0@-,%sp@(PT_PC) /* copy exception program counter */
movel %a0@-,%sp@(PT_FORMATVEC)/* copy exception format/vector/sr */
bra 7f
6:
clrl %sp@- /* stkadj */
movel %d0,%sp@- /* orig d0 */
movel %d0,%sp@- /* d0 */
lea %sp@(-32),%sp /* space for 8 regs */
moveml %d1-%d5/%a0-%a2,%sp@
7:
.endm
.macro RESTORE_ALL
btst #5,%sp@(PT_SR) /* going user? */
bnes 8f /* no, skip */
move #0x2700,%sr /* disable intrs */
movel sw_usp,%a0 /* get usp */
movel %sp@(PT_PC),%a0@- /* copy exception program counter */
movel %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */
moveml %sp@,%d1-%d5/%a0-%a2
lea %sp@(32),%sp /* space for 8 regs */
movel %sp@+,%d0
addql #4,%sp /* orig d0 */
addl %sp@+,%sp /* stkadj */
addql #8,%sp /* remove exception */
movel %sp,sw_ksp /* save ksp */
subql #8,sw_usp /* set exception */
movel sw_usp,%sp /* restore usp */
rte
8:
moveml %sp@,%d1-%d5/%a0-%a2
lea %sp@(32),%sp /* space for 8 regs */
movel %sp@+,%d0
addql #4,%sp /* orig d0 */
addl %sp@+,%sp /* stkadj */
rte
.endm
/*
* Quick exception save, use current stack only.
*/
.macro SAVE_LOCAL
move #0x2700,%sr /* disable intrs */
clrl %sp@- /* stkadj */
movel %d0,%sp@- /* orig d0 */
movel %d0,%sp@- /* d0 */
lea %sp@(-32),%sp /* space for 8 regs */
moveml %d1-%d5/%a0-%a2,%sp@
.endm
.macro RESTORE_LOCAL
moveml %sp@,%d1-%d5/%a0-%a2
lea %sp@(32),%sp /* space for 8 regs */
movel %sp@+,%d0
addql #4,%sp /* orig d0 */
addl %sp@+,%sp /* stkadj */
rte
.endm
.macro SAVE_SWITCH_STACK
lea %sp@(-24),%sp /* 6 regs */
moveml %a3-%a6/%d6-%d7,%sp@
.endm
.macro RESTORE_SWITCH_STACK
moveml %sp@,%a3-%a6/%d6-%d7
lea %sp@(24),%sp /* 6 regs */
.endm
/*
* Software copy of the user and kernel stack pointers... Ugh...
* Need these to get around ColdFire not having separate kernel
* and user stack pointers.
*/
.globl sw_usp
.globl sw_ksp
#else /* !CONFIG_COLDFIRE */
/*
* Standard 68k interrupt entry and exit macros.
*/
.macro SAVE_ALL
clrl %sp@- /* stkadj */
movel %d0,%sp@- /* orig d0 */
movel %d0,%sp@- /* d0 */
moveml %d1-%d5/%a0-%a2,%sp@-
.endm
.macro RESTORE_ALL
moveml %sp@+,%a0-%a2/%d1-%d5
movel %sp@+,%d0
addql #4,%sp /* orig d0 */
addl %sp@+,%sp /* stkadj */
rte
.endm
.macro SAVE_SWITCH_STACK
moveml %a3-%a6/%d6-%d7,%sp@-
.endm
.macro RESTORE_SWITCH_STACK
moveml %sp@+,%a3-%a6/%d6-%d7
.endm
#endif /* !CONFIG_COLDFIRE */
#endif /* __ASSEMBLY__ */
#endif /* __M68KNOMMU_ENTRY_H */

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#ifndef _M68K_ERRNO_H
#define _M68K_ERRNO_H
#include <asm-generic/errno.h>
#endif /* _M68K_ERRNO_H */

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#ifdef __uClinux__
#include "fb_no.h"
#else
#include "fb_mm.h"
#endif

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#ifndef _ASM_FB_H_
#define _ASM_FB_H_
#include <linux/fb.h>
#include <linux/fs.h>
#include <asm/page.h>
#include <asm/setup.h>
#ifdef CONFIG_SUN3
static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
unsigned long off)
{
pgprot_val(vma->vm_page_prot) |= SUN3_PAGE_NOCACHE;
}
#else
static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
unsigned long off)
{
if (CPU_IS_020_OR_030)
pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE030;
if (CPU_IS_040_OR_060) {
pgprot_val(vma->vm_page_prot) &= _CACHEMASK040;
/* Use no-cache mode, serialized */
pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE_S;
}
}
#endif /* CONFIG_SUN3 */
static inline int fb_is_primary_device(struct fb_info *info)
{
return 0;
}
#endif /* _ASM_FB_H_ */

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#ifndef _ASM_FB_H_
#define _ASM_FB_H_
#include <linux/fb.h>
#define fb_pgprotect(...) do {} while (0)
static inline int fb_is_primary_device(struct fb_info *info)
{
return 0;
}
#endif /* _ASM_FB_H_ */

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#ifndef __LINUX_FBIO_H
#define __LINUX_FBIO_H
#include <linux/compiler.h>
#include <linux/types.h>
/* Constants used for fbio SunOS compatibility */
/* (C) 1996 Miguel de Icaza */
/* Frame buffer types */
#define FBTYPE_NOTYPE -1
#define FBTYPE_SUN1BW 0 /* mono */
#define FBTYPE_SUN1COLOR 1
#define FBTYPE_SUN2BW 2
#define FBTYPE_SUN2COLOR 3
#define FBTYPE_SUN2GP 4
#define FBTYPE_SUN5COLOR 5
#define FBTYPE_SUN3COLOR 6
#define FBTYPE_MEMCOLOR 7
#define FBTYPE_SUN4COLOR 8
#define FBTYPE_NOTSUN1 9
#define FBTYPE_NOTSUN2 10
#define FBTYPE_NOTSUN3 11
#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
#define FBTYPE_SUNROP_COLOR 13
#define FBTYPE_SUNFB_VIDEO 14
#define FBTYPE_SUNGIFB 15
#define FBTYPE_SUNGPLAS 16
#define FBTYPE_SUNGP3 17
#define FBTYPE_SUNGT 18
#define FBTYPE_SUNLEO 19 /* zx Leo card */
#define FBTYPE_MDICOLOR 20 /* cg14 */
#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
/* Does not seem to be listed in the Sun file either */
#define FBTYPE_CREATOR 22
#define FBTYPE_PCI_IGA1682 23
#define FBTYPE_P9100COLOR 24
#define FBTYPE_PCI_GENERIC 1000
#define FBTYPE_PCI_MACH64 1001
/* fbio ioctls */
/* Returned by FBIOGTYPE */
struct fbtype {
int fb_type; /* fb type, see above */
int fb_height; /* pixels */
int fb_width; /* pixels */
int fb_depth;
int fb_cmsize; /* color map entries */
int fb_size; /* fb size in bytes */
};
#define FBIOGTYPE _IOR('F', 0, struct fbtype)
struct fbcmap {
int index; /* first element (0 origin) */
int count;
unsigned char __user *red;
unsigned char __user *green;
unsigned char __user *blue;
};
#ifdef __KERNEL__
#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
#else
#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
#endif
/* # of device specific values */
#define FB_ATTR_NDEVSPECIFIC 8
/* # of possible emulations */
#define FB_ATTR_NEMUTYPES 4
struct fbsattr {
int flags;
int emu_type; /* -1 if none */
int dev_specific[FB_ATTR_NDEVSPECIFIC];
};
struct fbgattr {
int real_type; /* real frame buffer type */
int owner; /* unknown */
struct fbtype fbtype; /* real frame buffer fbtype */
struct fbsattr sattr;
int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
};
#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
#define FBIOSVIDEO _IOW('F', 7, int)
#define FBIOGVIDEO _IOR('F', 8, int)
struct fbcursor {
short set; /* what to set, choose from the list above */
short enable; /* cursor on/off */
struct fbcurpos pos; /* cursor position */
struct fbcurpos hot; /* cursor hot spot */
struct fbcmap cmap; /* color map info */
struct fbcurpos size; /* cursor bit map size */
char __user *image; /* cursor image bits */
char __user *mask; /* cursor mask bits */
};
/* set/get cursor attributes/shape */
#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
/* set/get cursor position */
#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
/* get max cursor size */
#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
/* wid manipulation */
struct fb_wid_alloc {
#define FB_WID_SHARED_8 0
#define FB_WID_SHARED_24 1
#define FB_WID_DBL_8 2
#define FB_WID_DBL_24 3
__u32 wa_type;
__s32 wa_index; /* Set on return */
__u32 wa_count;
};
struct fb_wid_item {
__u32 wi_type;
__s32 wi_index;
__u32 wi_attrs;
__u32 wi_values[32];
};
struct fb_wid_list {
__u32 wl_flags;
__u32 wl_count;
struct fb_wid_item *wl_list;
};
#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
/* Creator ioctls */
#define FFB_IOCTL ('F'<<8)
#define FFB_SYS_INFO (FFB_IOCTL|80)
#define FFB_CLUTREAD (FFB_IOCTL|81)
#define FFB_CLUTPOST (FFB_IOCTL|82)
#define FFB_SETDIAGMODE (FFB_IOCTL|83)
#define FFB_GETMONITORID (FFB_IOCTL|84)
#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
#define FFB_SETSERVER (FFB_IOCTL|87)
#define FFB_SETOVCTL (FFB_IOCTL|88)
#define FFB_GETOVCTL (FFB_IOCTL|89)
#define FFB_GETSAXNUM (FFB_IOCTL|90)
#define FFB_FBDEBUG (FFB_IOCTL|91)
/* Cg14 ioctls */
#define MDI_IOCTL ('M'<<8)
#define MDI_RESET (MDI_IOCTL|1)
#define MDI_GET_CFGINFO (MDI_IOCTL|2)
#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
# define MDI_32_PIX 32
# define MDI_16_PIX 16
# define MDI_8_PIX 8
struct mdi_cfginfo {
int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
int mdi_type; /* FBTYPE name */
int mdi_height; /* height */
int mdi_width; /* widht */
int mdi_size; /* available ram */
int mdi_mode; /* 8bpp, 16bpp or 32bpp */
int mdi_pixfreq; /* pixel clock (from PROM) */
};
/* SparcLinux specific ioctl for the MDI, should be replaced for
* the SET_XLUT/SET_CLUTn ioctls instead
*/
#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
/* leo & ffb ioctls */
struct fb_clut_alloc {
__u32 clutid; /* Set on return */
__u32 flag;
__u32 index;
};
struct fb_clut {
#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
__u32 flag;
__u32 clutid;
__u32 offset;
__u32 count;
char * red;
char * green;
char * blue;
};
struct fb_clut32 {
__u32 flag;
__u32 clutid;
__u32 offset;
__u32 count;
__u32 red;
__u32 green;
__u32 blue;
};
#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
#ifdef __KERNEL__
/* Addresses on the fd of a cgsix that are mappable */
#define CG6_FBC 0x70000000
#define CG6_TEC 0x70001000
#define CG6_BTREGS 0x70002000
#define CG6_FHC 0x70004000
#define CG6_THC 0x70005000
#define CG6_ROM 0x70006000
#define CG6_RAM 0x70016000
#define CG6_DHC 0x80000000
#define CG3_MMAP_OFFSET 0x4000000
/* Addresses on the fd of a tcx that are mappable */
#define TCX_RAM8BIT 0x00000000
#define TCX_RAM24BIT 0x01000000
#define TCX_UNK3 0x10000000
#define TCX_UNK4 0x20000000
#define TCX_CONTROLPLANE 0x28000000
#define TCX_UNK6 0x30000000
#define TCX_UNK7 0x38000000
#define TCX_TEC 0x70000000
#define TCX_BTREGS 0x70002000
#define TCX_THC 0x70004000
#define TCX_DHC 0x70008000
#define TCX_ALT 0x7000a000
#define TCX_SYNC 0x7000e000
#define TCX_UNK2 0x70010000
/* CG14 definitions */
/* Offsets into the OBIO space: */
#define CG14_REGS 0 /* registers */
#define CG14_CURSORREGS 0x1000 /* cursor registers */
#define CG14_DACREGS 0x2000 /* DAC registers */
#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
#define CG14_CLUT1 0x4000 /* Color Look Up Table */
#define CG14_CLUT2 0x5000 /* Color Look Up Table */
#define CG14_CLUT3 0x6000 /* Color Look Up Table */
#define CG14_AUTO 0xf000
#endif /* KERNEL */
/* These are exported to userland for applications to use */
/* Mappable offsets for the cg14: control registers */
#define MDI_DIRECT_MAP 0x10000000
#define MDI_CTLREG_MAP 0x20000000
#define MDI_CURSOR_MAP 0x30000000
#define MDI_SHDW_VRT_MAP 0x40000000
/* Mappable offsets for the cg14: frame buffer resolutions */
/* 32 bits */
#define MDI_CHUNKY_XBGR_MAP 0x50000000
#define MDI_CHUNKY_BGR_MAP 0x60000000
/* 16 bits */
#define MDI_PLANAR_X16_MAP 0x70000000
#define MDI_PLANAR_C16_MAP 0x80000000
/* 8 bit is done as CG3 MMAP offset */
/* 32 bits, planar */
#define MDI_PLANAR_X32_MAP 0x90000000
#define MDI_PLANAR_B32_MAP 0xa0000000
#define MDI_PLANAR_G32_MAP 0xb0000000
#define MDI_PLANAR_R32_MAP 0xc0000000
/* Mappable offsets on leo */
#define LEO_SS0_MAP 0x00000000
#define LEO_LC_SS0_USR_MAP 0x00800000
#define LEO_LD_SS0_MAP 0x00801000
#define LEO_LX_CURSOR_MAP 0x00802000
#define LEO_SS1_MAP 0x00803000
#define LEO_LC_SS1_USR_MAP 0x01003000
#define LEO_LD_SS1_MAP 0x01004000
#define LEO_UNK_MAP 0x01005000
#define LEO_LX_KRN_MAP 0x01006000
#define LEO_LC_SS0_KRN_MAP 0x01007000
#define LEO_LC_SS1_KRN_MAP 0x01008000
#define LEO_LD_GBL_MAP 0x01009000
#define LEO_UNK2_MAP 0x0100a000
#ifdef __KERNEL__
struct fbcmap32 {
int index; /* first element (0 origin) */
int count;
u32 red;
u32 green;
u32 blue;
};
#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32)
#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32)
struct fbcursor32 {
short set; /* what to set, choose from the list above */
short enable; /* cursor on/off */
struct fbcurpos pos; /* cursor position */
struct fbcurpos hot; /* cursor hot spot */
struct fbcmap32 cmap; /* color map info */
struct fbcurpos size; /* cursor bit map size */
u32 image; /* cursor image bits */
u32 mask; /* cursor mask bits */
};
#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32)
#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32)
#endif
#endif /* __LINUX_FBIO_H */

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#ifndef _M68K_FCNTL_H
#define _M68K_FCNTL_H
#define O_DIRECTORY 040000 /* must be a directory */
#define O_NOFOLLOW 0100000 /* don't follow links */
#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
#define O_LARGEFILE 0400000
#include <asm-generic/fcntl.h>
#endif /* _M68K_FCNTL_H */

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/*
* include/asm-m68knommu/flat.h -- uClinux flat-format executables
*/
#ifndef __M68KNOMMU_FLAT_H__
#define __M68KNOMMU_FLAT_H__
#define flat_stack_align(sp) /* nothing needed */
#define flat_argvp_envp_on_stack() 1
#define flat_old_ram_flag(flags) (flags)
#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp)
#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
#define flat_get_relocate_addr(rel) (rel)
#define flat_set_persistent(relval, p) 0
#endif /* __M68KNOMMU_FLAT_H__ */

254
arch/m68k/include/asm/floppy.h Normal file
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/*
* Implementation independent bits of the Floppy driver.
*
* much of this file is derived from what was originally the Q40 floppy driver.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999, 2000, 2001
*
* Sun3x support added 2/4/2000 Sam Creasey (sammy@sammy.net)
*
*/
#include <asm/io.h>
#include <linux/vmalloc.h>
asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id);
/* constants... */
#undef MAX_DMA_ADDRESS
#define MAX_DMA_ADDRESS 0x00 /* nothing like that */
/*
* Again, the CMOS information doesn't work on m68k..
*/
#define FLOPPY0_TYPE (MACH_IS_Q40 ? 6 : 4)
#define FLOPPY1_TYPE 0
/* basically PC init + set use_virtual_dma */
#define FDC1 m68k_floppy_init()
#define N_FDC 1
#define N_DRIVE 8
/* vdma globals adapted from asm-i386/floppy.h */
static int virtual_dma_count=0;
static int virtual_dma_residue=0;
static char *virtual_dma_addr=NULL;
static int virtual_dma_mode=0;
static int doing_pdma=0;
#include <asm/sun3xflop.h>
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
static __inline__ unsigned char fd_inb(int port)
{
if(MACH_IS_Q40)
return inb_p(port);
else if(MACH_IS_SUN3X)
return sun3x_82072_fd_inb(port);
return 0;
}
static __inline__ void fd_outb(unsigned char value, int port)
{
if(MACH_IS_Q40)
outb_p(value, port);
else if(MACH_IS_SUN3X)
sun3x_82072_fd_outb(value, port);
}
static int fd_request_irq(void)
{
if(MACH_IS_Q40)
return request_irq(FLOPPY_IRQ, floppy_hardint,
IRQF_DISABLED, "floppy", floppy_hardint);
else if(MACH_IS_SUN3X)
return sun3xflop_request_irq();
return -ENXIO;
}
static void fd_free_irq(void)
{
if(MACH_IS_Q40)
free_irq(FLOPPY_IRQ, floppy_hardint);
}
#define fd_request_dma() vdma_request_dma(FLOPPY_DMA,"floppy")
#define fd_get_dma_residue() vdma_get_dma_residue(FLOPPY_DMA)
#define fd_dma_mem_alloc(size) vdma_mem_alloc(size)
#define fd_dma_setup(addr, size, mode, io) vdma_dma_setup(addr, size, mode, io)
#define fd_enable_irq() /* nothing... */
#define fd_disable_irq() /* nothing... */
#define fd_free_dma() /* nothing */
/* No 64k boundary crossing problems on Q40 - no DMA at all */
#define CROSS_64KB(a,s) (0)
#define DMA_MODE_READ 0x44 /* i386 look-alike */
#define DMA_MODE_WRITE 0x48
static int m68k_floppy_init(void)
{
use_virtual_dma =1;
can_use_virtual_dma = 1;
if (MACH_IS_Q40)
return 0x3f0;
else if(MACH_IS_SUN3X)
return sun3xflop_init();
else
return -1;
}
static int vdma_request_dma(unsigned int dmanr, const char * device_id)
{
return 0;
}
static int vdma_get_dma_residue(unsigned int dummy)
{
return virtual_dma_count + virtual_dma_residue;
}
static unsigned long vdma_mem_alloc(unsigned long size)
{
return (unsigned long) vmalloc(size);
}
static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
{
vfree((void *)addr);
}
#define fd_dma_mem_free(addr,size) _fd_dma_mem_free(addr, size)
/* choose_dma_mode ???*/
static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
{
doing_pdma = 1;
virtual_dma_port = (MACH_IS_Q40 ? io : 0);
virtual_dma_mode = (mode == DMA_MODE_WRITE);
virtual_dma_addr = addr;
virtual_dma_count = size;
virtual_dma_residue = 0;
return 0;
}
static void fd_disable_dma(void)
{
doing_pdma = 0;
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
}
/* this is the only truly Q40 specific function */
asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id)
{
register unsigned char st;
#undef TRACE_FLPY_INT
#define NO_FLOPPY_ASSEMBLER
#ifdef TRACE_FLPY_INT
static int calls=0;
static int bytes=0;
static int dma_wait=0;
#endif
if(!doing_pdma) {
floppy_interrupt(irq, dev_id);
return IRQ_HANDLED;
}
#ifdef TRACE_FLPY_INT
if(!calls)
bytes = virtual_dma_count;
#endif
{
register int lcount;
register char *lptr;
/* serve 1st byte fast: */
st=1;
for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
lcount; lcount--, lptr++) {
st=inb(virtual_dma_port+4) & 0xa0 ;
if(st != 0xa0)
break;
if(virtual_dma_mode)
outb_p(*lptr, virtual_dma_port+5);
else
*lptr = inb_p(virtual_dma_port+5);
}
virtual_dma_count = lcount;
virtual_dma_addr = lptr;
st = inb(virtual_dma_port+4);
}
#ifdef TRACE_FLPY_INT
calls++;
#endif
if(st == 0x20)
return IRQ_HANDLED;
if(!(st & 0x20)) {
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
#ifdef TRACE_FLPY_INT
printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
virtual_dma_count, virtual_dma_residue, calls, bytes,
dma_wait);
calls = 0;
dma_wait=0;
#endif
doing_pdma = 0;
floppy_interrupt(irq, dev_id);
return IRQ_HANDLED;
}
#ifdef TRACE_FLPY_INT
if(!virtual_dma_count)
dma_wait++;
#endif
return IRQ_HANDLED;
}
#define EXTRA_FLOPPY_PARAMS

5
arch/m68k/include/asm/fpu.h Normal file
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#ifdef __uClinux__
#include "fpu_no.h"
#else
#include "fpu_mm.h"
#endif

21
arch/m68k/include/asm/fpu_mm.h Normal file
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@@ -0,0 +1,21 @@
#ifndef __M68K_FPU_H
#define __M68K_FPU_H
/*
* MAX floating point unit state size (FSAVE/FRESTORE)
*/
#if defined(CONFIG_M68020) || defined(CONFIG_M68030)
#define FPSTATESIZE (216)
#elif defined(CONFIG_M68040)
#define FPSTATESIZE (96)
#elif defined(CONFIG_M68KFPU_EMU)
#define FPSTATESIZE (28)
#elif defined(CONFIG_M68060)
#define FPSTATESIZE (12)
#else
#define FPSTATESIZE (0)
#endif
#endif /* __M68K_FPU_H */

21
arch/m68k/include/asm/fpu_no.h Normal file
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@@ -0,0 +1,21 @@
#ifndef __M68KNOMMU_FPU_H
#define __M68KNOMMU_FPU_H
/*
* MAX floating point unit state size (FSAVE/FRESTORE)
*/
#if defined(CONFIG_M68020) || defined(CONFIG_M68030)
#define FPSTATESIZE (216/sizeof(unsigned char))
#elif defined(CONFIG_M68040)
#define FPSTATESIZE (96/sizeof(unsigned char))
#elif defined(CONFIG_M68KFPU_EMU)
#define FPSTATESIZE (28/sizeof(unsigned char))
#elif defined(CONFIG_M68060)
#define FPSTATESIZE (12/sizeof(unsigned char))
#else
/* Assume no FP unit present then... */
#define FPSTATESIZE (2) /* dummy size */
#endif
#endif /* __M68K_FPU_H */

6
arch/m68k/include/asm/futex.h Normal file
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#ifndef _ASM_FUTEX_H
#define _ASM_FUTEX_H
#include <asm-generic/futex.h>
#endif

5
arch/m68k/include/asm/hardirq.h Normal file
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@@ -0,0 +1,5 @@
#ifdef __uClinux__
#include "hardirq_no.h"
#else
#include "hardirq_mm.h"
#endif

16
arch/m68k/include/asm/hardirq_mm.h Normal file
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@@ -0,0 +1,16 @@
#ifndef __M68K_HARDIRQ_H
#define __M68K_HARDIRQ_H
#include <linux/threads.h>
#include <linux/cache.h>
/* entry.S is sensitive to the offsets of these fields */
typedef struct {
unsigned int __softirq_pending;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
#define HARDIRQ_BITS 8
#endif

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