Merge tag 'char-misc-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver updates from Greg KH: "Here is the "big" char and misc driver patches for 4.18-rc1. It's not a lot of stuff here, but there are some highlights: - coreboot driver updates - soundwire driver updates - android binder updates - fpga big sync, mostly documentation - lots of minor driver updates All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (81 commits) vmw_balloon: fixing double free when batching mode is off MAINTAINERS: Add driver-api/fpga path fpga: clarify that unregister functions also free documentation: fpga: move fpga-region.txt to driver-api documentation: fpga: add bridge document to driver-api documentation: fpga: move fpga-mgr.txt to driver-api Documentation: fpga: move fpga overview to driver-api fpga: region: kernel-doc fixes fpga: bridge: kernel-doc fixes fpga: mgr: kernel-doc fixes fpga: use SPDX fpga: region: change api, add fpga_region_create/free fpga: bridge: change api, don't use drvdata fpga: manager: change api, don't use drvdata fpga: region: don't use drvdata in common fpga code Drivers: hv: vmbus: Removed an unnecessary cast from void * ver_linux: Drop redundant calls to system() to test if file is readable ver_linux: Move stderr redirection from function parameter to function body misc: IBM Virtual Management Channel Driver (VMC) rpmsg: Correct support for MODULE_DEVICE_TABLE() ...
This commit is contained in:
Linus Torvalds
@@ -1,13 +1,6 @@
|
||||
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_CORESIGHT_H
|
||||
|
||||
@@ -1,3 +1,4 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Driver for Altera Partial Reconfiguration IP Core
|
||||
*
|
||||
@@ -5,18 +6,6 @@
|
||||
*
|
||||
* Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
|
||||
* by Alan Tull <atull@opensource.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _ALT_PR_IP_CORE_H
|
||||
|
||||
@@ -62,8 +62,11 @@ int of_fpga_bridge_get_to_list(struct device_node *np,
|
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struct fpga_image_info *info,
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struct list_head *bridge_list);
|
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|
||||
int fpga_bridge_register(struct device *dev, const char *name,
|
||||
const struct fpga_bridge_ops *br_ops, void *priv);
|
||||
void fpga_bridge_unregister(struct device *dev);
|
||||
struct fpga_bridge *fpga_bridge_create(struct device *dev, const char *name,
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const struct fpga_bridge_ops *br_ops,
|
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void *priv);
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void fpga_bridge_free(struct fpga_bridge *br);
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int fpga_bridge_register(struct fpga_bridge *br);
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void fpga_bridge_unregister(struct fpga_bridge *br);
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|
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#endif /* _LINUX_FPGA_BRIDGE_H */
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|
||||
@@ -1,20 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* FPGA Framework
|
||||
*
|
||||
* Copyright (C) 2013-2016 Altera Corporation
|
||||
* Copyright (C) 2017 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef _LINUX_FPGA_MGR_H
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#define _LINUX_FPGA_MGR_H
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@@ -170,9 +159,11 @@ struct fpga_manager *fpga_mgr_get(struct device *dev);
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|
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void fpga_mgr_put(struct fpga_manager *mgr);
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|
||||
int fpga_mgr_register(struct device *dev, const char *name,
|
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const struct fpga_manager_ops *mops, void *priv);
|
||||
|
||||
void fpga_mgr_unregister(struct device *dev);
|
||||
struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name,
|
||||
const struct fpga_manager_ops *mops,
|
||||
void *priv);
|
||||
void fpga_mgr_free(struct fpga_manager *mgr);
|
||||
int fpga_mgr_register(struct fpga_manager *mgr);
|
||||
void fpga_mgr_unregister(struct fpga_manager *mgr);
|
||||
|
||||
#endif /*_LINUX_FPGA_MGR_H */
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|
||||
@@ -1,3 +1,5 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#ifndef _FPGA_REGION_H
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#define _FPGA_REGION_H
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|
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@@ -14,7 +16,6 @@
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* @info: FPGA image info
|
||||
* @priv: private data
|
||||
* @get_bridges: optional function to get bridges to a list
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* @groups: optional attribute groups.
|
||||
*/
|
||||
struct fpga_region {
|
||||
struct device dev;
|
||||
@@ -24,7 +25,6 @@ struct fpga_region {
|
||||
struct fpga_image_info *info;
|
||||
void *priv;
|
||||
int (*get_bridges)(struct fpga_region *region);
|
||||
const struct attribute_group **groups;
|
||||
};
|
||||
|
||||
#define to_fpga_region(d) container_of(d, struct fpga_region, dev)
|
||||
@@ -34,7 +34,12 @@ struct fpga_region *fpga_region_class_find(
|
||||
int (*match)(struct device *, const void *));
|
||||
|
||||
int fpga_region_program_fpga(struct fpga_region *region);
|
||||
int fpga_region_register(struct device *dev, struct fpga_region *region);
|
||||
int fpga_region_unregister(struct fpga_region *region);
|
||||
|
||||
struct fpga_region
|
||||
*fpga_region_create(struct device *dev, struct fpga_manager *mgr,
|
||||
int (*get_bridges)(struct fpga_region *));
|
||||
void fpga_region_free(struct fpga_region *region);
|
||||
int fpga_region_register(struct fpga_region *region);
|
||||
void fpga_region_unregister(struct fpga_region *region);
|
||||
|
||||
#endif /* _FPGA_REGION_H */
|
||||
|
||||
@@ -163,6 +163,7 @@ static inline u32 hv_get_bytes_to_write(const struct hv_ring_buffer_info *rbi)
|
||||
* 2 . 4 (Windows 8)
|
||||
* 3 . 0 (Windows 8 R2)
|
||||
* 4 . 0 (Windows 10)
|
||||
* 5 . 0 (Newer Windows 10)
|
||||
*/
|
||||
|
||||
#define VERSION_WS2008 ((0 << 16) | (13))
|
||||
@@ -170,10 +171,11 @@ static inline u32 hv_get_bytes_to_write(const struct hv_ring_buffer_info *rbi)
|
||||
#define VERSION_WIN8 ((2 << 16) | (4))
|
||||
#define VERSION_WIN8_1 ((3 << 16) | (0))
|
||||
#define VERSION_WIN10 ((4 << 16) | (0))
|
||||
#define VERSION_WIN10_V5 ((5 << 16) | (0))
|
||||
|
||||
#define VERSION_INVAL -1
|
||||
|
||||
#define VERSION_CURRENT VERSION_WIN10
|
||||
#define VERSION_CURRENT VERSION_WIN10_V5
|
||||
|
||||
/* Make maximum size of pipe payload of 16K */
|
||||
#define MAX_PIPE_DATA_PAYLOAD (sizeof(u8) * 16384)
|
||||
@@ -570,7 +572,14 @@ struct vmbus_channel_initiate_contact {
|
||||
struct vmbus_channel_message_header header;
|
||||
u32 vmbus_version_requested;
|
||||
u32 target_vcpu; /* The VCPU the host should respond to */
|
||||
u64 interrupt_page;
|
||||
union {
|
||||
u64 interrupt_page;
|
||||
struct {
|
||||
u8 msg_sint;
|
||||
u8 padding1[3];
|
||||
u32 padding2;
|
||||
};
|
||||
};
|
||||
u64 monitor_page1;
|
||||
u64 monitor_page2;
|
||||
} __packed;
|
||||
@@ -585,6 +594,19 @@ struct vmbus_channel_tl_connect_request {
|
||||
struct vmbus_channel_version_response {
|
||||
struct vmbus_channel_message_header header;
|
||||
u8 version_supported;
|
||||
|
||||
u8 connection_state;
|
||||
u16 padding;
|
||||
|
||||
/*
|
||||
* On new hosts that support VMBus protocol 5.0, we must use
|
||||
* VMBUS_MESSAGE_CONNECTION_ID_4 for the Initiate Contact Message,
|
||||
* and for subsequent messages, we must use the Message Connection ID
|
||||
* field in the host-returned Version Response Message.
|
||||
*
|
||||
* On old hosts, we should always use VMBUS_MESSAGE_CONNECTION_ID (1).
|
||||
*/
|
||||
u32 msg_conn_id;
|
||||
} __packed;
|
||||
|
||||
enum vmbus_channel_state {
|
||||
|
||||
@@ -163,7 +163,7 @@ void nubus_seq_write_rsrc_mem(struct seq_file *m,
|
||||
unsigned char *nubus_dirptr(const struct nubus_dirent *nd);
|
||||
|
||||
/* Declarations relating to driver model objects */
|
||||
int nubus_bus_register(void);
|
||||
int nubus_parent_device_register(void);
|
||||
int nubus_device_register(struct nubus_board *board);
|
||||
int nubus_driver_register(struct nubus_driver *ndrv);
|
||||
void nubus_driver_unregister(struct nubus_driver *ndrv);
|
||||
|
||||
@@ -77,6 +77,9 @@ struct nvmem_device *devm_nvmem_register(struct device *dev,
|
||||
|
||||
int devm_nvmem_unregister(struct device *dev, struct nvmem_device *nvmem);
|
||||
|
||||
int nvmem_add_cells(struct nvmem_device *nvmem,
|
||||
const struct nvmem_cell_info *info,
|
||||
int ncells);
|
||||
#else
|
||||
|
||||
static inline struct nvmem_device *nvmem_register(const struct nvmem_config *c)
|
||||
@@ -99,6 +102,14 @@ static inline int
|
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devm_nvmem_unregister(struct device *dev, struct nvmem_device *nvmem)
|
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{
|
||||
return nvmem_unregister(nvmem);
|
||||
|
||||
}
|
||||
|
||||
static inline int nvmem_add_cells(struct nvmem_device *nvmem,
|
||||
const struct nvmem_cell_info *info,
|
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int ncells)
|
||||
{
|
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return -ENOSYS;
|
||||
}
|
||||
|
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#endif /* CONFIG_NVMEM */
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@@ -23,9 +23,24 @@ struct sdw_slave;
|
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#define SDW_MASTER_DEV_NUM 14
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|
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#define SDW_NUM_DEV_ID_REGISTERS 6
|
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/* frame shape defines */
|
||||
|
||||
/*
|
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* Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
|
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* fill hole with 0, one more dummy entry is added
|
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*/
|
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#define SDW_FRAME_ROWS 24
|
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#define SDW_FRAME_COLS 8
|
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#define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
|
||||
|
||||
#define SDW_FRAME_CTRL_BITS 48
|
||||
#define SDW_MAX_DEVICES 11
|
||||
|
||||
#define SDW_VALID_PORT_RANGE(n) (n <= 14 && n >= 1)
|
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|
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#define SDW_DAI_ID_RANGE_START 100
|
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#define SDW_DAI_ID_RANGE_END 200
|
||||
|
||||
/**
|
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* enum sdw_slave_status - Slave status
|
||||
* @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
|
||||
@@ -61,6 +76,30 @@ enum sdw_command_response {
|
||||
SDW_CMD_FAIL_OTHER = 4,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum sdw_stream_type: data stream type
|
||||
*
|
||||
* @SDW_STREAM_PCM: PCM data stream
|
||||
* @SDW_STREAM_PDM: PDM data stream
|
||||
*
|
||||
* spec doesn't define this, but is used in implementation
|
||||
*/
|
||||
enum sdw_stream_type {
|
||||
SDW_STREAM_PCM = 0,
|
||||
SDW_STREAM_PDM = 1,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum sdw_data_direction: Data direction
|
||||
*
|
||||
* @SDW_DATA_DIR_RX: Data into Port
|
||||
* @SDW_DATA_DIR_TX: Data out of Port
|
||||
*/
|
||||
enum sdw_data_direction {
|
||||
SDW_DATA_DIR_RX = 0,
|
||||
SDW_DATA_DIR_TX = 1,
|
||||
};
|
||||
|
||||
/*
|
||||
* SDW properties, defined in MIPI DisCo spec v1.0
|
||||
*/
|
||||
@@ -341,11 +380,92 @@ struct sdw_slave_intr_status {
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_slave_ops - Slave driver callback ops
|
||||
* sdw_reg_bank - SoundWire register banks
|
||||
* @SDW_BANK0: Soundwire register bank 0
|
||||
* @SDW_BANK1: Soundwire register bank 1
|
||||
*/
|
||||
enum sdw_reg_bank {
|
||||
SDW_BANK0,
|
||||
SDW_BANK1,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_bus_conf: Bus configuration
|
||||
*
|
||||
* @clk_freq: Clock frequency, in Hz
|
||||
* @num_rows: Number of rows in frame
|
||||
* @num_cols: Number of columns in frame
|
||||
* @bank: Next register bank
|
||||
*/
|
||||
struct sdw_bus_conf {
|
||||
unsigned int clk_freq;
|
||||
unsigned int num_rows;
|
||||
unsigned int num_cols;
|
||||
unsigned int bank;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
|
||||
*
|
||||
* @num: Port number
|
||||
* @ch_mask: Active channel mask
|
||||
* @prepare: Prepare (true) /de-prepare (false) channel
|
||||
* @bank: Register bank, which bank Slave/Master driver should program for
|
||||
* implementation defined registers. This is always updated to next_bank
|
||||
* value read from bus params.
|
||||
*
|
||||
*/
|
||||
struct sdw_prepare_ch {
|
||||
unsigned int num;
|
||||
unsigned int ch_mask;
|
||||
bool prepare;
|
||||
unsigned int bank;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum sdw_port_prep_ops: Prepare operations for Data Port
|
||||
*
|
||||
* @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
|
||||
* @SDW_OPS_PORT_PREP: Prepare operation for the Port
|
||||
* @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
|
||||
*/
|
||||
enum sdw_port_prep_ops {
|
||||
SDW_OPS_PORT_PRE_PREP = 0,
|
||||
SDW_OPS_PORT_PREP = 1,
|
||||
SDW_OPS_PORT_POST_PREP = 2,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_bus_params: Structure holding bus configuration
|
||||
*
|
||||
* @curr_bank: Current bank in use (BANK0/BANK1)
|
||||
* @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
|
||||
* set to !curr_bank
|
||||
* @max_dr_freq: Maximum double rate clock frequency supported, in Hz
|
||||
* @curr_dr_freq: Current double rate clock frequency, in Hz
|
||||
* @bandwidth: Current bandwidth
|
||||
* @col: Active columns
|
||||
* @row: Active rows
|
||||
*/
|
||||
struct sdw_bus_params {
|
||||
enum sdw_reg_bank curr_bank;
|
||||
enum sdw_reg_bank next_bank;
|
||||
unsigned int max_dr_freq;
|
||||
unsigned int curr_dr_freq;
|
||||
unsigned int bandwidth;
|
||||
unsigned int col;
|
||||
unsigned int row;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_slave_ops: Slave driver callback ops
|
||||
*
|
||||
* @read_prop: Read Slave properties
|
||||
* @interrupt_callback: Device interrupt notification (invoked in thread
|
||||
* context)
|
||||
* @update_status: Update Slave status
|
||||
* @bus_config: Update the bus config for Slave
|
||||
* @port_prep: Prepare the port with parameters
|
||||
*/
|
||||
struct sdw_slave_ops {
|
||||
int (*read_prop)(struct sdw_slave *sdw);
|
||||
@@ -353,6 +473,11 @@ struct sdw_slave_ops {
|
||||
struct sdw_slave_intr_status *status);
|
||||
int (*update_status)(struct sdw_slave *slave,
|
||||
enum sdw_slave_status status);
|
||||
int (*bus_config)(struct sdw_slave *slave,
|
||||
struct sdw_bus_params *params);
|
||||
int (*port_prep)(struct sdw_slave *slave,
|
||||
struct sdw_prepare_ch *prepare_ch,
|
||||
enum sdw_port_prep_ops pre_ops);
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -406,6 +531,93 @@ int sdw_handle_slave_status(struct sdw_bus *bus,
|
||||
* SDW master structures and APIs
|
||||
*/
|
||||
|
||||
/**
|
||||
* struct sdw_port_params: Data Port parameters
|
||||
*
|
||||
* @num: Port number
|
||||
* @bps: Word length of the Port
|
||||
* @flow_mode: Port Data flow mode
|
||||
* @data_mode: Test modes or normal mode
|
||||
*
|
||||
* This is used to program the Data Port based on Data Port stream
|
||||
* parameters.
|
||||
*/
|
||||
struct sdw_port_params {
|
||||
unsigned int num;
|
||||
unsigned int bps;
|
||||
unsigned int flow_mode;
|
||||
unsigned int data_mode;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_transport_params: Data Port Transport Parameters
|
||||
*
|
||||
* @blk_grp_ctrl_valid: Port implements block group control
|
||||
* @num: Port number
|
||||
* @blk_grp_ctrl: Block group control value
|
||||
* @sample_interval: Sample interval
|
||||
* @offset1: Blockoffset of the payload data
|
||||
* @offset2: Blockoffset of the payload data
|
||||
* @hstart: Horizontal start of the payload data
|
||||
* @hstop: Horizontal stop of the payload data
|
||||
* @blk_pkg_mode: Block per channel or block per port
|
||||
* @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
|
||||
* data lane is supported in bus
|
||||
*
|
||||
* This is used to program the Data Port based on Data Port transport
|
||||
* parameters. All these parameters are banked and can be modified
|
||||
* during a bank switch without any artifacts in audio stream.
|
||||
*/
|
||||
struct sdw_transport_params {
|
||||
bool blk_grp_ctrl_valid;
|
||||
unsigned int port_num;
|
||||
unsigned int blk_grp_ctrl;
|
||||
unsigned int sample_interval;
|
||||
unsigned int offset1;
|
||||
unsigned int offset2;
|
||||
unsigned int hstart;
|
||||
unsigned int hstop;
|
||||
unsigned int blk_pkg_mode;
|
||||
unsigned int lane_ctrl;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_enable_ch: Enable/disable Data Port channel
|
||||
*
|
||||
* @num: Port number
|
||||
* @ch_mask: Active channel mask
|
||||
* @enable: Enable (true) /disable (false) channel
|
||||
*/
|
||||
struct sdw_enable_ch {
|
||||
unsigned int port_num;
|
||||
unsigned int ch_mask;
|
||||
bool enable;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_master_port_ops: Callback functions from bus to Master
|
||||
* driver to set Master Data ports.
|
||||
*
|
||||
* @dpn_set_port_params: Set the Port parameters for the Master Port.
|
||||
* Mandatory callback
|
||||
* @dpn_set_port_transport_params: Set transport parameters for the Master
|
||||
* Port. Mandatory callback
|
||||
* @dpn_port_prep: Port prepare operations for the Master Data Port.
|
||||
* @dpn_port_enable_ch: Enable the channels of Master Port.
|
||||
*/
|
||||
struct sdw_master_port_ops {
|
||||
int (*dpn_set_port_params)(struct sdw_bus *bus,
|
||||
struct sdw_port_params *port_params,
|
||||
unsigned int bank);
|
||||
int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
|
||||
struct sdw_transport_params *transport_params,
|
||||
enum sdw_reg_bank bank);
|
||||
int (*dpn_port_prep)(struct sdw_bus *bus,
|
||||
struct sdw_prepare_ch *prepare_ch);
|
||||
int (*dpn_port_enable_ch)(struct sdw_bus *bus,
|
||||
struct sdw_enable_ch *enable_ch, unsigned int bank);
|
||||
};
|
||||
|
||||
struct sdw_msg;
|
||||
|
||||
/**
|
||||
@@ -426,6 +638,9 @@ struct sdw_defer {
|
||||
* @xfer_msg: Transfer message callback
|
||||
* @xfer_msg_defer: Defer version of transfer message callback
|
||||
* @reset_page_addr: Reset the SCP page address registers
|
||||
* @set_bus_conf: Set the bus configuration
|
||||
* @pre_bank_switch: Callback for pre bank switch
|
||||
* @post_bank_switch: Callback for post bank switch
|
||||
*/
|
||||
struct sdw_master_ops {
|
||||
int (*read_prop)(struct sdw_bus *bus);
|
||||
@@ -437,6 +652,11 @@ struct sdw_master_ops {
|
||||
struct sdw_defer *defer);
|
||||
enum sdw_command_response (*reset_page_addr)
|
||||
(struct sdw_bus *bus, unsigned int dev_num);
|
||||
int (*set_bus_conf)(struct sdw_bus *bus,
|
||||
struct sdw_bus_params *params);
|
||||
int (*pre_bank_switch)(struct sdw_bus *bus);
|
||||
int (*post_bank_switch)(struct sdw_bus *bus);
|
||||
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -449,9 +669,15 @@ struct sdw_master_ops {
|
||||
* @bus_lock: bus lock
|
||||
* @msg_lock: message lock
|
||||
* @ops: Master callback ops
|
||||
* @port_ops: Master port callback ops
|
||||
* @params: Current bus parameters
|
||||
* @prop: Master properties
|
||||
* @m_rt_list: List of Master instance of all stream(s) running on Bus. This
|
||||
* is used to compute and program bus bandwidth, clock, frame shape,
|
||||
* transport and port parameters
|
||||
* @defer_msg: Defer message
|
||||
* @clk_stop_timeout: Clock stop timeout computed
|
||||
* @bank_switch_timeout: Bank switch timeout computed
|
||||
*/
|
||||
struct sdw_bus {
|
||||
struct device *dev;
|
||||
@@ -461,14 +687,118 @@ struct sdw_bus {
|
||||
struct mutex bus_lock;
|
||||
struct mutex msg_lock;
|
||||
const struct sdw_master_ops *ops;
|
||||
const struct sdw_master_port_ops *port_ops;
|
||||
struct sdw_bus_params params;
|
||||
struct sdw_master_prop prop;
|
||||
struct list_head m_rt_list;
|
||||
struct sdw_defer defer_msg;
|
||||
unsigned int clk_stop_timeout;
|
||||
u32 bank_switch_timeout;
|
||||
};
|
||||
|
||||
int sdw_add_bus_master(struct sdw_bus *bus);
|
||||
void sdw_delete_bus_master(struct sdw_bus *bus);
|
||||
|
||||
/**
|
||||
* sdw_port_config: Master or Slave Port configuration
|
||||
*
|
||||
* @num: Port number
|
||||
* @ch_mask: channels mask for port
|
||||
*/
|
||||
struct sdw_port_config {
|
||||
unsigned int num;
|
||||
unsigned int ch_mask;
|
||||
};
|
||||
|
||||
/**
|
||||
* sdw_stream_config: Master or Slave stream configuration
|
||||
*
|
||||
* @frame_rate: Audio frame rate of the stream, in Hz
|
||||
* @ch_count: Channel count of the stream
|
||||
* @bps: Number of bits per audio sample
|
||||
* @direction: Data direction
|
||||
* @type: Stream type PCM or PDM
|
||||
*/
|
||||
struct sdw_stream_config {
|
||||
unsigned int frame_rate;
|
||||
unsigned int ch_count;
|
||||
unsigned int bps;
|
||||
enum sdw_data_direction direction;
|
||||
enum sdw_stream_type type;
|
||||
};
|
||||
|
||||
/**
|
||||
* sdw_stream_state: Stream states
|
||||
*
|
||||
* @SDW_STREAM_ALLOCATED: New stream allocated.
|
||||
* @SDW_STREAM_CONFIGURED: Stream configured
|
||||
* @SDW_STREAM_PREPARED: Stream prepared
|
||||
* @SDW_STREAM_ENABLED: Stream enabled
|
||||
* @SDW_STREAM_DISABLED: Stream disabled
|
||||
* @SDW_STREAM_DEPREPARED: Stream de-prepared
|
||||
* @SDW_STREAM_RELEASED: Stream released
|
||||
*/
|
||||
enum sdw_stream_state {
|
||||
SDW_STREAM_ALLOCATED = 0,
|
||||
SDW_STREAM_CONFIGURED = 1,
|
||||
SDW_STREAM_PREPARED = 2,
|
||||
SDW_STREAM_ENABLED = 3,
|
||||
SDW_STREAM_DISABLED = 4,
|
||||
SDW_STREAM_DEPREPARED = 5,
|
||||
SDW_STREAM_RELEASED = 6,
|
||||
};
|
||||
|
||||
/**
|
||||
* sdw_stream_params: Stream parameters
|
||||
*
|
||||
* @rate: Sampling frequency, in Hz
|
||||
* @ch_count: Number of channels
|
||||
* @bps: bits per channel sample
|
||||
*/
|
||||
struct sdw_stream_params {
|
||||
unsigned int rate;
|
||||
unsigned int ch_count;
|
||||
unsigned int bps;
|
||||
};
|
||||
|
||||
/**
|
||||
* sdw_stream_runtime: Runtime stream parameters
|
||||
*
|
||||
* @name: SoundWire stream name
|
||||
* @params: Stream parameters
|
||||
* @state: Current state of the stream
|
||||
* @type: Stream type PCM or PDM
|
||||
* @m_rt: Master runtime
|
||||
*/
|
||||
struct sdw_stream_runtime {
|
||||
char *name;
|
||||
struct sdw_stream_params params;
|
||||
enum sdw_stream_state state;
|
||||
enum sdw_stream_type type;
|
||||
struct sdw_master_runtime *m_rt;
|
||||
};
|
||||
|
||||
struct sdw_stream_runtime *sdw_alloc_stream(char *stream_name);
|
||||
void sdw_release_stream(struct sdw_stream_runtime *stream);
|
||||
int sdw_stream_add_master(struct sdw_bus *bus,
|
||||
struct sdw_stream_config *stream_config,
|
||||
struct sdw_port_config *port_config,
|
||||
unsigned int num_ports,
|
||||
struct sdw_stream_runtime *stream);
|
||||
int sdw_stream_add_slave(struct sdw_slave *slave,
|
||||
struct sdw_stream_config *stream_config,
|
||||
struct sdw_port_config *port_config,
|
||||
unsigned int num_ports,
|
||||
struct sdw_stream_runtime *stream);
|
||||
int sdw_stream_remove_master(struct sdw_bus *bus,
|
||||
struct sdw_stream_runtime *stream);
|
||||
int sdw_stream_remove_slave(struct sdw_slave *slave,
|
||||
struct sdw_stream_runtime *stream);
|
||||
int sdw_prepare_stream(struct sdw_stream_runtime *stream);
|
||||
int sdw_enable_stream(struct sdw_stream_runtime *stream);
|
||||
int sdw_disable_stream(struct sdw_stream_runtime *stream);
|
||||
int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
|
||||
|
||||
/* messaging and data APIs */
|
||||
|
||||
int sdw_read(struct sdw_slave *slave, u32 addr);
|
||||
|
||||
@@ -4,18 +4,32 @@
|
||||
#ifndef __SDW_INTEL_H
|
||||
#define __SDW_INTEL_H
|
||||
|
||||
/**
|
||||
* struct sdw_intel_ops: Intel audio driver callback ops
|
||||
*
|
||||
* @config_stream: configure the stream with the hw_params
|
||||
*/
|
||||
struct sdw_intel_ops {
|
||||
int (*config_stream)(void *arg, void *substream,
|
||||
void *dai, void *hw_params, int stream_num);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sdw_intel_res - Soundwire Intel resource structure
|
||||
* @mmio_base: mmio base of SoundWire registers
|
||||
* @irq: interrupt number
|
||||
* @handle: ACPI parent handle
|
||||
* @parent: parent device
|
||||
* @ops: callback ops
|
||||
* @arg: callback arg
|
||||
*/
|
||||
struct sdw_intel_res {
|
||||
void __iomem *mmio_base;
|
||||
int irq;
|
||||
acpi_handle handle;
|
||||
struct device *parent;
|
||||
const struct sdw_intel_ops *ops;
|
||||
void *arg;
|
||||
};
|
||||
|
||||
void *sdw_intel_init(acpi_handle *parent_handle, struct sdw_intel_res *res);
|
||||
|
||||
@@ -14,6 +14,7 @@
|
||||
#ifndef _UIO_DRIVER_H_
|
||||
#define _UIO_DRIVER_H_
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
@@ -68,12 +69,13 @@ struct uio_port {
|
||||
|
||||
struct uio_device {
|
||||
struct module *owner;
|
||||
struct device *dev;
|
||||
struct device dev;
|
||||
int minor;
|
||||
atomic_t event;
|
||||
struct fasync_struct *async_queue;
|
||||
wait_queue_head_t wait;
|
||||
struct uio_info *info;
|
||||
spinlock_t info_lock;
|
||||
struct kobject *map_dir;
|
||||
struct kobject *portio_dir;
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user