sh: Generic kgdb stub support.
This migrates from the old bitrotted kgdb stub implementation and moves to the generic stub. In the process support for SH-2/SH-2A is also added, which the old stub never provided. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Esse commit está contido em:
Paul Mundt
285
arch/sh/kernel/kgdb.c
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285
arch/sh/kernel/kgdb.c
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/*
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* SuperH KGDB support
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*
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* Copyright (C) 2008 Paul Mundt
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*
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* Single stepping taken from the old stub by Henry Bell and Jeremy Siegel.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kgdb.h>
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#include <linux/kdebug.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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char in_nmi = 0; /* Set during NMI to prevent re-entry */
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/* Macros for single step instruction identification */
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#define OPCODE_BT(op) (((op) & 0xff00) == 0x8900)
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#define OPCODE_BF(op) (((op) & 0xff00) == 0x8b00)
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#define OPCODE_BTF_DISP(op) (((op) & 0x80) ? (((op) | 0xffffff80) << 1) : \
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(((op) & 0x7f ) << 1))
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#define OPCODE_BFS(op) (((op) & 0xff00) == 0x8f00)
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#define OPCODE_BTS(op) (((op) & 0xff00) == 0x8d00)
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#define OPCODE_BRA(op) (((op) & 0xf000) == 0xa000)
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#define OPCODE_BRA_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \
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(((op) & 0x7ff) << 1))
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#define OPCODE_BRAF(op) (((op) & 0xf0ff) == 0x0023)
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#define OPCODE_BRAF_REG(op) (((op) & 0x0f00) >> 8)
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#define OPCODE_BSR(op) (((op) & 0xf000) == 0xb000)
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#define OPCODE_BSR_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \
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(((op) & 0x7ff) << 1))
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#define OPCODE_BSRF(op) (((op) & 0xf0ff) == 0x0003)
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#define OPCODE_BSRF_REG(op) (((op) >> 8) & 0xf)
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#define OPCODE_JMP(op) (((op) & 0xf0ff) == 0x402b)
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#define OPCODE_JMP_REG(op) (((op) >> 8) & 0xf)
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#define OPCODE_JSR(op) (((op) & 0xf0ff) == 0x400b)
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#define OPCODE_JSR_REG(op) (((op) >> 8) & 0xf)
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#define OPCODE_RTS(op) ((op) == 0xb)
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#define OPCODE_RTE(op) ((op) == 0x2b)
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#define SR_T_BIT_MASK 0x1
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#define STEP_OPCODE 0xc33d
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/* Calculate the new address for after a step */
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static short *get_step_address(struct pt_regs *linux_regs)
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{
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opcode_t op = __raw_readw(linux_regs->pc);
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long addr;
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/* BT */
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if (OPCODE_BT(op)) {
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if (linux_regs->sr & SR_T_BIT_MASK)
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addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op);
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else
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addr = linux_regs->pc + 2;
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}
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/* BTS */
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else if (OPCODE_BTS(op)) {
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if (linux_regs->sr & SR_T_BIT_MASK)
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addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op);
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else
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addr = linux_regs->pc + 4; /* Not in delay slot */
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}
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/* BF */
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else if (OPCODE_BF(op)) {
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if (!(linux_regs->sr & SR_T_BIT_MASK))
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addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op);
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else
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addr = linux_regs->pc + 2;
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}
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/* BFS */
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else if (OPCODE_BFS(op)) {
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if (!(linux_regs->sr & SR_T_BIT_MASK))
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addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op);
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else
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addr = linux_regs->pc + 4; /* Not in delay slot */
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}
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/* BRA */
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else if (OPCODE_BRA(op))
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addr = linux_regs->pc + 4 + OPCODE_BRA_DISP(op);
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/* BRAF */
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else if (OPCODE_BRAF(op))
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addr = linux_regs->pc + 4
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+ linux_regs->regs[OPCODE_BRAF_REG(op)];
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/* BSR */
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else if (OPCODE_BSR(op))
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addr = linux_regs->pc + 4 + OPCODE_BSR_DISP(op);
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/* BSRF */
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else if (OPCODE_BSRF(op))
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addr = linux_regs->pc + 4
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+ linux_regs->regs[OPCODE_BSRF_REG(op)];
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/* JMP */
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else if (OPCODE_JMP(op))
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addr = linux_regs->regs[OPCODE_JMP_REG(op)];
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/* JSR */
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else if (OPCODE_JSR(op))
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addr = linux_regs->regs[OPCODE_JSR_REG(op)];
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/* RTS */
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else if (OPCODE_RTS(op))
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addr = linux_regs->pr;
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/* RTE */
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else if (OPCODE_RTE(op))
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addr = linux_regs->regs[15];
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/* Other */
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else
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addr = linux_regs->pc + instruction_size(op);
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flush_icache_range(addr, addr + instruction_size(op));
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return (short *)addr;
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}
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/*
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* Replace the instruction immediately after the current instruction
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* (i.e. next in the expected flow of control) with a trap instruction,
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* so that returning will cause only a single instruction to be executed.
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* Note that this model is slightly broken for instructions with delay
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* slots (e.g. B[TF]S, BSR, BRA etc), where both the branch and the
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* instruction in the delay slot will be executed.
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*/
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static unsigned long stepped_address;
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static opcode_t stepped_opcode;
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static void do_single_step(struct pt_regs *linux_regs)
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{
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/* Determine where the target instruction will send us to */
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unsigned short *addr = get_step_address(linux_regs);
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stepped_address = (int)addr;
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/* Replace it */
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stepped_opcode = __raw_readw((long)addr);
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*addr = STEP_OPCODE;
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/* Flush and return */
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flush_icache_range((long)addr, (long)addr +
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instruction_size(stepped_opcode));
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}
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/* Undo a single step */
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static void undo_single_step(struct pt_regs *linux_regs)
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{
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/* If we have stepped, put back the old instruction */
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/* Use stepped_address in case we stopped elsewhere */
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if (stepped_opcode != 0) {
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__raw_writew(stepped_opcode, stepped_address);
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flush_icache_range(stepped_address, stepped_address + 2);
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}
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stepped_opcode = 0;
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}
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void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
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{
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int i;
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for (i = 0; i < 16; i++)
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gdb_regs[GDB_R0 + i] = regs->regs[i];
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gdb_regs[GDB_PC] = regs->pc;
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gdb_regs[GDB_PR] = regs->pr;
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gdb_regs[GDB_SR] = regs->sr;
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gdb_regs[GDB_GBR] = regs->gbr;
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gdb_regs[GDB_MACH] = regs->mach;
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gdb_regs[GDB_MACL] = regs->macl;
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__asm__ __volatile__ ("stc vbr, %0" : "=r" (gdb_regs[GDB_VBR]));
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}
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void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
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{
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int i;
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for (i = 0; i < 16; i++)
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regs->regs[GDB_R0 + i] = gdb_regs[GDB_R0 + i];
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regs->pc = gdb_regs[GDB_PC];
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regs->pr = gdb_regs[GDB_PR];
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regs->sr = gdb_regs[GDB_SR];
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regs->gbr = gdb_regs[GDB_GBR];
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regs->mach = gdb_regs[GDB_MACH];
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regs->macl = gdb_regs[GDB_MACL];
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__asm__ __volatile__ ("ldc %0, vbr" : : "r" (gdb_regs[GDB_VBR]));
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}
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void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
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{
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gdb_regs[GDB_R15] = p->thread.sp;
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gdb_regs[GDB_PC] = p->thread.pc;
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}
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int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
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char *remcomInBuffer, char *remcomOutBuffer,
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struct pt_regs *linux_regs)
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{
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unsigned long addr;
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char *ptr;
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/* Undo any stepping we may have done */
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undo_single_step(linux_regs);
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switch (remcomInBuffer[0]) {
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case 'c':
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case 's':
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/* try to read optional parameter, pc unchanged if no parm */
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ptr = &remcomInBuffer[1];
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if (kgdb_hex2long(&ptr, &addr))
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linux_regs->pc = addr;
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case 'D':
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case 'k':
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atomic_set(&kgdb_cpu_doing_single_step, -1);
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if (remcomInBuffer[0] == 's') {
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do_single_step(linux_regs);
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kgdb_single_step = 1;
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atomic_set(&kgdb_cpu_doing_single_step,
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raw_smp_processor_id());
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}
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return 0;
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}
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/* this means that we do not want to exit from the handler: */
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return -1;
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}
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/*
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* The primary entry points for the kgdb debug trap table entries.
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*/
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BUILD_TRAP_HANDLER(singlestep)
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{
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unsigned long flags;
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TRAP_HANDLER_DECL;
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local_irq_save(flags);
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regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
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kgdb_handle_exception(vec >> 2, SIGTRAP, 0, regs);
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local_irq_restore(flags);
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}
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BUILD_TRAP_HANDLER(breakpoint)
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{
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unsigned long flags;
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TRAP_HANDLER_DECL;
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local_irq_save(flags);
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kgdb_handle_exception(vec >> 2, SIGTRAP, 0, regs);
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local_irq_restore(flags);
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}
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int kgdb_arch_init(void)
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{
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return 0;
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}
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void kgdb_arch_exit(void)
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{
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}
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struct kgdb_arch arch_kgdb_ops = {
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/* Breakpoint instruction: trapa #0x3c */
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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.gdb_bpt_instr = { 0x3c, 0xc3 },
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#else
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.gdb_bpt_instr = { 0xc3, 0x3c },
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#endif
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};
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