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perf, x86: Improve the PEBS ABI

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Rename perf_event_attr::precise to perf_event_attr::precise_ip and
widen it to 2 bits. This new field describes the required precision of
the PERF_SAMPLE_IP field:

  0 - SAMPLE_IP can have arbitrary skid
  1 - SAMPLE_IP must have constant skid
  2 - SAMPLE_IP requested to have 0 skid
  3 - SAMPLE_IP must have 0 skid

And modify the Intel PEBS code accordingly. The PEBS implementation
now supports up to precise_ip == 2, where we perform the IP fixup.

Also s/PERF_RECORD_MISC_EXACT/&_IP/ to clarify its meaning, this bit
should be set for each PERF_SAMPLE_IP field known to match the actual
instruction triggering the event.

This new scheme allows for a PEBS mode that uses the buffer for more
than a single event.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Stephane Eranian <eranian@google.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Peter Zijlstra
2010-04-08 23:03:20 +02:00
committed by Ingo Molnar
parent 2b0b5c6fe9
commit ab608344bc
6 changed files with 59 additions and 22 deletions
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2
tools/perf/builtin-top.c
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@@ -1021,7 +1021,7 @@ static void event__process_sample(const event_t *self,
return;
}
if (self->header.misc & PERF_RECORD_MISC_EXACT)
if (self->header.misc & PERF_RECORD_MISC_EXACT_IP)
exact_samples++;
if (event__preprocess_sample(self, session, &al, symbol_filter) < 0 ||