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Enable a suitable ISA for the assembler around ll/sc so that code

Telusuri Sumber 
builds even for processors that don't support the instructions.
Plus minor formatting fixes.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
2005-06-14 17:35:03 +00:00
committed by Ralf Baechle
orang tua fded2e508a
melakukan aac8aa7717
4 mengubah file dengan 118 tambahan dan 32 penghapusan
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12
arch/mips/kernel/semaphore.c
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@@ -42,24 +42,28 @@ static inline int __sem_update_count(struct semaphore *sem, int incr)
if (cpu_has_llsc && R10000_LLSC_WAR) {
__asm__ __volatile__(
"1: ll %0, %2 \n"
" .set mips2 \n"
"1: ll %0, %2 # __sem_update_count \n"
" sra %1, %0, 31 \n"
" not %1 \n"
" and %1, %0, %1 \n"
" add %1, %1, %3 \n"
" addu %1, %1, %3 \n"
" sc %1, %2 \n"
" beqzl %1, 1b \n"
" .set mips0 \n"
: "=&r" (old_count), "=&r" (tmp), "=m" (sem->count)
: "r" (incr), "m" (sem->count));
} else if (cpu_has_llsc) {
__asm__ __volatile__(
"1: ll %0, %2 \n"
" .set mips2 \n"
"1: ll %0, %2 # __sem_update_count \n"
" sra %1, %0, 31 \n"
" not %1 \n"
" and %1, %0, %1 \n"
" add %1, %1, %3 \n"
" addu %1, %1, %3 \n"
" sc %1, %2 \n"
" beqz %1, 1b \n"
" .set mips0 \n"
: "=&r" (old_count), "=&r" (tmp), "=m" (sem->count)
: "r" (incr), "m" (sem->count));
} else {