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cxl: Flush PSL cache before resetting the adapter

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If the capi link is going down while the PSL owns a dirty cache line,
any access from the host for that data could lead to an Uncorrectable
Error.

So when resetting the capi adapter through sysfs, make sure the PSL
cache is flushed. It won't help if there are any active Process
Elements on the card, as the cache would likely get new dirty cache
lines immediately, but if resetting an idle adapter, it should avoid
any bad surprises from data left over from terminated Process Elements.

Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Frederic Barrat
2016-10-03 21:36:02 +02:00
committed by Michael Ellerman
parent e2ad477cb2
commit aaa2245ed8
3 changed files with 39 additions and 1 deletions
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31
drivers/misc/cxl/native.c
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@@ -290,6 +290,37 @@ int cxl_tlb_slb_invalidate(struct cxl *adapter)
return 0;
}
int cxl_data_cache_flush(struct cxl *adapter)
{
u64 reg;
unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
pr_devel("Flushing data cache\n");
reg = cxl_p1_read(adapter, CXL_PSL_Control);
reg |= CXL_PSL_Control_Fr;
cxl_p1_write(adapter, CXL_PSL_Control, reg);
reg = cxl_p1_read(adapter, CXL_PSL_Control);
while ((reg & CXL_PSL_Control_Fs_MASK) != CXL_PSL_Control_Fs_Complete) {
if (time_after_eq(jiffies, timeout)) {
dev_warn(&adapter->dev, "WARNING: cache flush timed out!\n");
return -EBUSY;
}
if (!cxl_ops->link_ok(adapter, NULL)) {
dev_warn(&adapter->dev, "WARNING: link down when flushing cache\n");
return -EIO;
}
cpu_relax();
reg = cxl_p1_read(adapter, CXL_PSL_Control);
}
reg &= ~CXL_PSL_Control_Fr;
cxl_p1_write(adapter, CXL_PSL_Control, reg);
return 0;
}
static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
{
int rc;