xiaomi-sm8450/android_kernel_xiaomi_sm8450
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Merge tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

소스 검색 
Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Fix the incorrect display clock on R-Car M3-N,
  - Always use readl()/writel(),
  - Small fixes.

* tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Adjust r8a77980 ifdef
  clk: renesas: rcar-gen3: Always use readl()/writel()
  clk: renesas: sh73a0: Always use readl()/writel()
  clk: renesas: rza1: Always use readl()/writel()
  clk: renesas: rcar-gen2: Always use readl()/writel()
  clk: renesas: r8a7740: Always use readl()/writel()
  clk: renesas: r8a73a4: Always use readl()/writel()
  clk: renesas: mstp: Always use readl()/writel()
  clk: renesas: div6: Always use readl()/writel()
  clk: renesas: r8a77965: Replace DU2 clock
This commit is contained in:
Stephen Boyd
2018-03-23 09:40:52 -07:00
부모 ce33f28493 472f5f3918
커밋 aa584d28f3
10개의 변경된 파일과 48개의 추가작업 그리고 50개의 파일을 삭제
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14
drivers/clk/renesas/clk-sh73a0.c
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@@ -85,7 +85,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
if (!strcmp(name, "main")) {
/* extal1, extal1_div2, extal2, extal2_div2 */
u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
div = (parent_idx & 1) + 1;
@@ -110,11 +110,11 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
default:
return ERR_PTR(-EINVAL);
}
if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1;
if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
/* handle CFG bit for PLL1 and PLL2 */
if (enable_bit == 1 || enable_bit == 2)
if (clk_readl(enable_reg) & BIT(20))
if (readl(enable_reg) & BIT(20))
mult *= 2;
}
} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
@@ -193,9 +193,9 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np)
return;
/* Set SDHI clocks to a known state */
clk_writel(0x108, cpg->reg + CPG_SD0CKCR);
clk_writel(0x108, cpg->reg + CPG_SD1CKCR);
clk_writel(0x108, cpg->reg + CPG_SD2CKCR);
writel(0x108, cpg->reg + CPG_SD0CKCR);
writel(0x108, cpg->reg + CPG_SD1CKCR);
writel(0x108, cpg->reg + CPG_SD2CKCR);
for (i = 0; i < num_clks; ++i) {
const char *name;