MIPS: Octeon: Update register definitions for CN63XX chips

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The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.

Join some lines back together.  This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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David Daney

2010-10-07 16:03:40 -07:00

committed by Ralf Baechle

parent b93b2abce4

commit aa32a955ae

20 changed files with 4219 additions and 2168 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

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807

arch/mips/include/asm/octeon/cvmx-mio-defs.h

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