Merge tag 'tty-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty/serial driver patches from Greg KH: "Here's the big tty/serial driver update for 3.20-rc1. Nothing huge here, just lots of driver updates and some core tty layer fixes as well. All have been in linux-next with no reported issues" * tag 'tty-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (119 commits) serial: 8250: Fix UART_BUG_TXEN workaround serial: driver for ETRAX FS UART tty: remove unused variable sprop serial: of-serial: fetch line number from DT serial: samsung: earlycon support depends on CONFIG_SERIAL_SAMSUNG_CONSOLE tty/serial: serial8250_set_divisor() can be static tty/serial: Add Spreadtrum sc9836-uart driver support Documentation: DT: Add bindings for Spreadtrum SoC Platform serial: samsung: remove redundant interrupt enabling tty: Remove external interface for tty_set_termios() serial: omap: Fix RTS handling serial: 8250_omap: Use UPSTAT_AUTORTS for RTS handling serial: core: Rework hw-assisted flow control support tty/serial: 8250_early: Add support for PXA UARTs tty/serial: of_serial: add support for PXA/MMP uarts tty/serial: of_serial: add DT alias ID handling serial: 8250: Prevent concurrent updates to shadow registers serial: 8250: Use canary to restart console after suspend serial: 8250: Refactor XR17V35X divisor calculation serial: 8250: Refactor divisor programming ...
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@@ -55,7 +55,8 @@
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#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
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#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
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#define PORT_RT2880 29 /* Ralink RT2880 internal UART */
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#define PORT_MAX_8250 29 /* max port ID */
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#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
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#define PORT_MAX_8250 30 /* max port ID */
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/*
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* ARM specific type numbers. These are not currently guaranteed
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@@ -248,4 +249,13 @@
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/* MESON */
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#define PORT_MESON 109
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/* Conexant Digicolor */
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#define PORT_DIGICOLOR 110
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/* SPRD SERIAL */
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#define PORT_SPRD 111
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/* Cris v10 / v32 SoC */
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#define PORT_CRIS 112
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#endif /* _UAPILINUX_SERIAL_CORE_H */
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@@ -86,7 +86,8 @@
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#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
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#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
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#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
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#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
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#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750 and
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some Freescale UARTs) */
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#define UART_FCR_R_TRIG_SHIFT 6
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#define UART_FCR_R_TRIG_BITS(x) \
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