Merge tag 'tty-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty/serial driver patches from Greg KH: "Here's the big tty/serial driver update for 3.20-rc1. Nothing huge here, just lots of driver updates and some core tty layer fixes as well. All have been in linux-next with no reported issues" * tag 'tty-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (119 commits) serial: 8250: Fix UART_BUG_TXEN workaround serial: driver for ETRAX FS UART tty: remove unused variable sprop serial: of-serial: fetch line number from DT serial: samsung: earlycon support depends on CONFIG_SERIAL_SAMSUNG_CONSOLE tty/serial: serial8250_set_divisor() can be static tty/serial: Add Spreadtrum sc9836-uart driver support Documentation: DT: Add bindings for Spreadtrum SoC Platform serial: samsung: remove redundant interrupt enabling tty: Remove external interface for tty_set_termios() serial: omap: Fix RTS handling serial: 8250_omap: Use UPSTAT_AUTORTS for RTS handling serial: core: Rework hw-assisted flow control support tty/serial: 8250_early: Add support for PXA UARTs tty/serial: of_serial: add support for PXA/MMP uarts tty/serial: of_serial: add DT alias ID handling serial: 8250: Prevent concurrent updates to shadow registers serial: 8250: Use canary to restart console after suspend serial: 8250: Refactor XR17V35X divisor calculation serial: 8250: Refactor divisor programming ...
Esse commit está contido em:
Linus Torvalds
@@ -16,8 +16,6 @@ obj-$(subst m,y,$(CONFIG_INPUT_MPU3050)) += platform_mpu3050.o
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obj-$(subst m,y,$(CONFIG_INPUT_BMA150)) += platform_bma023.o
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obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o
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obj-$(subst m,y,$(CONFIG_DRM_MEDFIELD)) += platform_tc35876x.o
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# SPI Devices
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obj-$(subst m,y,$(CONFIG_SERIAL_MRST_MAX3110)) += platform_max3111.o
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# MISC Devices
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obj-$(subst m,y,$(CONFIG_KEYBOARD_GPIO)) += platform_gpio_keys.o
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obj-$(subst m,y,$(CONFIG_INTEL_MID_WATCHDOG)) += platform_wdt.o
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@@ -1,35 +0,0 @@
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/*
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* platform_max3111.c: max3111 platform data initilization file
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*
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* (C) Copyright 2013 Intel Corporation
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* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/gpio.h>
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#include <linux/spi/spi.h>
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#include <asm/intel-mid.h>
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static void __init *max3111_platform_data(void *info)
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{
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struct spi_board_info *spi_info = info;
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int intr = get_gpio_by_name("max3111_int");
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spi_info->mode = SPI_MODE_0;
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if (intr == -1)
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return NULL;
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spi_info->irq = intr + INTEL_MID_IRQ_OFFSET;
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return NULL;
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}
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static const struct devs_id max3111_dev_id __initconst = {
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.name = "spi_max3111",
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.type = SFI_DEV_TYPE_SPI,
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.get_platform_data = &max3111_platform_data,
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};
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sfi_device(max3111_dev_id);
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@@ -10,15 +10,13 @@
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*/
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/*
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* This file implements two early consoles named mrst and hsu.
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* mrst is based on Maxim3110 spi-uart device, it exists in both
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* Moorestown and Medfield platforms, while hsu is based on a High
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* Speed UART device which only exists in the Medfield platform
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* This file implements early console named hsu.
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* hsu is based on a High Speed UART device which only exists in the Medfield
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* platform
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*/
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#include <linux/serial_reg.h>
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#include <linux/serial_mfd.h>
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#include <linux/kmsg_dump.h>
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#include <linux/console.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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@@ -28,216 +26,6 @@
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#include <asm/pgtable.h>
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#include <asm/intel-mid.h>
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#define MRST_SPI_TIMEOUT 0x200000
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#define MRST_REGBASE_SPI0 0xff128000
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#define MRST_REGBASE_SPI1 0xff128400
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#define MRST_CLK_SPI0_REG 0xff11d86c
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/* Bit fields in CTRLR0 */
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#define SPI_DFS_OFFSET 0
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#define SPI_FRF_OFFSET 4
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#define SPI_FRF_SPI 0x0
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#define SPI_FRF_SSP 0x1
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#define SPI_FRF_MICROWIRE 0x2
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#define SPI_FRF_RESV 0x3
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#define SPI_MODE_OFFSET 6
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#define SPI_SCPH_OFFSET 6
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#define SPI_SCOL_OFFSET 7
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#define SPI_TMOD_OFFSET 8
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#define SPI_TMOD_TR 0x0 /* xmit & recv */
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#define SPI_TMOD_TO 0x1 /* xmit only */
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#define SPI_TMOD_RO 0x2 /* recv only */
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#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
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#define SPI_SLVOE_OFFSET 10
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#define SPI_SRL_OFFSET 11
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#define SPI_CFS_OFFSET 12
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/* Bit fields in SR, 7 bits */
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#define SR_MASK 0x7f /* cover 7 bits */
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#define SR_BUSY (1 << 0)
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#define SR_TF_NOT_FULL (1 << 1)
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#define SR_TF_EMPT (1 << 2)
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#define SR_RF_NOT_EMPT (1 << 3)
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#define SR_RF_FULL (1 << 4)
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#define SR_TX_ERR (1 << 5)
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#define SR_DCOL (1 << 6)
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struct dw_spi_reg {
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u32 ctrl0;
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u32 ctrl1;
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u32 ssienr;
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u32 mwcr;
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u32 ser;
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u32 baudr;
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u32 txfltr;
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u32 rxfltr;
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u32 txflr;
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u32 rxflr;
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u32 sr;
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u32 imr;
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u32 isr;
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u32 risr;
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u32 txoicr;
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u32 rxoicr;
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u32 rxuicr;
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u32 msticr;
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u32 icr;
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u32 dmacr;
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u32 dmatdlr;
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u32 dmardlr;
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u32 idr;
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u32 version;
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/* Currently operates as 32 bits, though only the low 16 bits matter */
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u32 dr;
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} __packed;
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#define dw_readl(dw, name) __raw_readl(&(dw)->name)
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#define dw_writel(dw, name, val) __raw_writel((val), &(dw)->name)
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/* Default use SPI0 register for mrst, we will detect Penwell and use SPI1 */
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static unsigned long mrst_spi_paddr = MRST_REGBASE_SPI0;
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static u32 *pclk_spi0;
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/* Always contains an accessible address, start with 0 */
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static struct dw_spi_reg *pspi;
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static struct kmsg_dumper dw_dumper;
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static int dumper_registered;
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static void dw_kmsg_dump(struct kmsg_dumper *dumper,
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enum kmsg_dump_reason reason)
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{
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static char line[1024];
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size_t len;
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/* When run to this, we'd better re-init the HW */
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mrst_early_console_init();
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while (kmsg_dump_get_line(dumper, true, line, sizeof(line), &len))
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early_mrst_console.write(&early_mrst_console, line, len);
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}
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/* Set the ratio rate to 115200, 8n1, IRQ disabled */
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static void max3110_write_config(void)
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{
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u16 config;
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config = 0xc001;
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dw_writel(pspi, dr, config);
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}
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/* Translate char to a eligible word and send to max3110 */
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static void max3110_write_data(char c)
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{
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u16 data;
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data = 0x8000 | c;
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dw_writel(pspi, dr, data);
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}
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void mrst_early_console_init(void)
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{
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u32 ctrlr0 = 0;
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u32 spi0_cdiv;
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u32 freq; /* Freqency info only need be searched once */
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/* Base clk is 100 MHz, the actual clk = 100M / (clk_divider + 1) */
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pclk_spi0 = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
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MRST_CLK_SPI0_REG);
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spi0_cdiv = ((*pclk_spi0) & 0xe00) >> 9;
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freq = 100000000 / (spi0_cdiv + 1);
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if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL)
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mrst_spi_paddr = MRST_REGBASE_SPI1;
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pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
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mrst_spi_paddr);
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/* Disable SPI controller */
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dw_writel(pspi, ssienr, 0);
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/* Set control param, 8 bits, transmit only mode */
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ctrlr0 = dw_readl(pspi, ctrl0);
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ctrlr0 &= 0xfcc0;
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ctrlr0 |= 0xf | (SPI_FRF_SPI << SPI_FRF_OFFSET)
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| (SPI_TMOD_TO << SPI_TMOD_OFFSET);
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dw_writel(pspi, ctrl0, ctrlr0);
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/*
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* Change the spi0 clk to comply with 115200 bps, use 100000 to
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* calculate the clk dividor to make the clock a little slower
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* than real baud rate.
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*/
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dw_writel(pspi, baudr, freq/100000);
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/* Disable all INT for early phase */
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dw_writel(pspi, imr, 0x0);
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/* Set the cs to spi-uart */
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dw_writel(pspi, ser, 0x2);
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/* Enable the HW, the last step for HW init */
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dw_writel(pspi, ssienr, 0x1);
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/* Set the default configuration */
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max3110_write_config();
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/* Register the kmsg dumper */
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if (!dumper_registered) {
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dw_dumper.dump = dw_kmsg_dump;
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kmsg_dump_register(&dw_dumper);
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dumper_registered = 1;
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}
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}
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/* Slave select should be called in the read/write function */
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static void early_mrst_spi_putc(char c)
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{
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unsigned int timeout;
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u32 sr;
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timeout = MRST_SPI_TIMEOUT;
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/* Early putc needs to make sure the TX FIFO is not full */
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while (--timeout) {
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sr = dw_readl(pspi, sr);
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if (!(sr & SR_TF_NOT_FULL))
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cpu_relax();
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else
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break;
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}
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if (!timeout)
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pr_warn("MRST earlycon: timed out\n");
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else
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max3110_write_data(c);
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}
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/* Early SPI only uses polling mode */
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static void early_mrst_spi_write(struct console *con, const char *str,
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unsigned n)
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{
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int i;
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for (i = 0; i < n && *str; i++) {
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if (*str == '\n')
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early_mrst_spi_putc('\r');
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early_mrst_spi_putc(*str);
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str++;
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}
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}
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struct console early_mrst_console = {
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.name = "earlymrst",
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.write = early_mrst_spi_write,
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.flags = CON_PRINTBUFFER,
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.index = -1,
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};
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/*
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* Following is the early console based on Medfield HSU (High
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* Speed UART) device.
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@@ -259,7 +47,7 @@ void hsu_early_console_init(const char *s)
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port = clamp_val(port, 0, 2);
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paddr = HSU_PORT_BASE + port * 0x80;
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phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr);
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phsu = (void __iomem *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr);
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/* Disable FIFO */
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writeb(0x0, phsu + UART_FCR);
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