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ptp: support DPAA FMan 1588 timer in ptp_qoriq

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This patch is to support DPAA (Data Path Acceleration Architecture)
1588 timer by adding "fsl,fman-ptp-timer" compatible, sharing
interrupt with FMan, adding FSL_DPAA_ETH dependency, and fixing
up register offset.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
Acked-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yangbo Lu
2018-06-25 20:37:08 +08:00
committed by David S. Miller
parent c401530256
commit a8f62d0c6f
3 changed files with 98 additions and 46 deletions
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38
include/linux/fsl/ptp_qoriq.h
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@@ -11,9 +11,8 @@
/*
* qoriq ptp registers
* Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
*/
struct qoriq_ptp_registers {
struct ctrl_regs {
u32 tmr_ctrl; /* Timer control register */
u32 tmr_tevent; /* Timestamp event register */
u32 tmr_temask; /* Timer event mask register */
@@ -28,22 +27,47 @@ struct qoriq_ptp_registers {
u8 res1[4];
u32 tmroff_h; /* Timer offset high */
u32 tmroff_l; /* Timer offset low */
u8 res2[8];
};
struct alarm_regs {
u32 tmr_alarm1_h; /* Timer alarm 1 high register */
u32 tmr_alarm1_l; /* Timer alarm 1 high register */
u32 tmr_alarm2_h; /* Timer alarm 2 high register */
u32 tmr_alarm2_l; /* Timer alarm 2 high register */
u8 res3[48];
};
struct fiper_regs {
u32 tmr_fiper1; /* Timer fixed period interval */
u32 tmr_fiper2; /* Timer fixed period interval */
u32 tmr_fiper3; /* Timer fixed period interval */
u8 res4[20];
};
struct etts_regs {
u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
};
struct qoriq_ptp_registers {
struct ctrl_regs __iomem *ctrl_regs;
struct alarm_regs __iomem *alarm_regs;
struct fiper_regs __iomem *fiper_regs;
struct etts_regs __iomem *etts_regs;
};
/* Offset definitions for the four register groups */
#define CTRL_REGS_OFFSET 0x0
#define ALARM_REGS_OFFSET 0x40
#define FIPER_REGS_OFFSET 0x80
#define ETTS_REGS_OFFSET 0xa0
#define FMAN_CTRL_REGS_OFFSET 0x80
#define FMAN_ALARM_REGS_OFFSET 0xb8
#define FMAN_FIPER_REGS_OFFSET 0xd0
#define FMAN_ETTS_REGS_OFFSET 0xe0
/* Bit definitions for the TMR_CTRL register */
#define ALM1P (1<<31) /* Alarm1 output polarity */
#define ALM2P (1<<30) /* Alarm2 output polarity */
@@ -105,10 +129,10 @@ struct qoriq_ptp_registers {
#define DRIVER "ptp_qoriq"
#define DEFAULT_CKSEL 1
#define N_EXT_TS 2
#define REG_SIZE sizeof(struct qoriq_ptp_registers)
struct qoriq_ptp {
struct qoriq_ptp_registers __iomem *regs;
void __iomem *base;
struct qoriq_ptp_registers regs;
spinlock_t lock; /* protects regs */
struct ptp_clock *clock;
struct ptp_clock_info caps;