Merge git://git.infradead.org/mtd-2.6
* git://git.infradead.org/mtd-2.6: (120 commits) [MTD] Fix mtdoops.c compilation [MTD] [NOR] fix startup lock when using multiple nor flash chips [MTD] [DOC200x] eccbuf is statically defined and always evaluate to true [MTD] Fix maps/physmap.c compilation with CONFIG_PM [MTD] onenand: Add panic_write function to the onenand driver [MTD] mtdoops: Use the panic_write function when present [MTD] Add mtd panic_write function pointer [MTD] [NAND] Freescale enhanced Local Bus Controller FCM NAND support. [MTD] physmap.c: Add support for multiple resources [MTD] [NAND] Fix misparenthesization introduced by commit 78b65179... [MTD] [NAND] Fix Blackfin NFC ECC calculating bug with page size 512 bytes [MTD] [NAND] Remove wrong operation in PM function of the BF54x NFC driver [MTD] [NAND] Remove unused variable in plat_nand_remove [MTD] Unlocking all Intel flash that is locked on power up. [MTD] [NAND] at91_nand: Make mtdparts option can override board info [MTD] mtdoops: Various minor cleanups [MTD] mtdoops: Ensure sequential write to the buffer [MTD] mtdoops: Perform write operations in a workqueue [MTD] mtdoops: Add further error return code checking [MTD] [NOR] Test devtype, not definition in flash_probe(), drivers/mtd/devices/lart.c ...
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@@ -120,6 +120,8 @@ struct s3c2410_nand_info {
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int sel_bit;
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int mtd_count;
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unsigned long save_nfconf;
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enum s3c_cpu_type cpu_type;
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};
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@@ -364,23 +366,21 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
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/* calculate the bit position of the error */
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bit = (diff2 >> 2) & 1;
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bit |= (diff2 >> 3) & 2;
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bit |= (diff2 >> 4) & 4;
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bit = ((diff2 >> 3) & 1) |
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((diff2 >> 4) & 2) |
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((diff2 >> 5) & 4);
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/* calculate the byte position of the error */
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byte = (diff1 << 1) & 0x80;
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byte |= (diff1 << 2) & 0x40;
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byte |= (diff1 << 3) & 0x20;
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byte |= (diff1 << 4) & 0x10;
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byte |= (diff0 >> 3) & 0x08;
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byte |= (diff0 >> 2) & 0x04;
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byte |= (diff0 >> 1) & 0x02;
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byte |= (diff0 >> 0) & 0x01;
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byte |= (diff2 << 8) & 0x100;
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byte = ((diff2 << 7) & 0x100) |
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((diff1 << 0) & 0x80) |
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((diff1 << 1) & 0x40) |
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((diff1 << 2) & 0x20) |
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((diff1 << 3) & 0x10) |
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((diff0 >> 4) & 0x08) |
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((diff0 >> 3) & 0x04) |
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((diff0 >> 2) & 0x02) |
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((diff0 >> 1) & 0x01);
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dev_dbg(info->device, "correcting error bit %d, byte %d\n",
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bit, byte);
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@@ -399,7 +399,7 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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if ((diff0 & ~(1<<fls(diff0))) == 0)
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return 1;
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return 0;
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return -1;
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}
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/* ECC functions
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@@ -810,6 +810,16 @@ static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
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struct s3c2410_nand_info *info = platform_get_drvdata(dev);
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if (info) {
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info->save_nfconf = readl(info->regs + S3C2410_NFCONF);
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/* For the moment, we must ensure nFCE is high during
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* the time we are suspended. This really should be
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* handled by suspending the MTDs we are using, but
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* that is currently not the case. */
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writel(info->save_nfconf | info->sel_bit,
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info->regs + S3C2410_NFCONF);
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if (!allow_clk_stop(info))
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clk_disable(info->clk);
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}
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@@ -820,11 +830,19 @@ static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
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static int s3c24xx_nand_resume(struct platform_device *dev)
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{
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struct s3c2410_nand_info *info = platform_get_drvdata(dev);
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unsigned long nfconf;
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if (info) {
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clk_enable(info->clk);
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s3c2410_nand_inithw(info, dev);
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/* Restore the state of the nFCE line. */
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nfconf = readl(info->regs + S3C2410_NFCONF);
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nfconf &= ~info->sel_bit;
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nfconf |= info->save_nfconf & info->sel_bit;
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writel(nfconf, info->regs + S3C2410_NFCONF);
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if (allow_clk_stop(info))
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clk_disable(info->clk);
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}
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