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bnx2: Fix shutdown sequence

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The pci shutdown handler added in:

    bnx2: Add pci shutdown handler
    commit 25bfb1dd4b

created a shutdown down sequence without chip reset if the device was
never brought up.  This can cause the firmware to shutdown the PHY
prematurely and cause MMIO read cycles to be unresponsive.  On some
systems, it may generate NMI in the bnx2's pci shutdown handler.

The fix is to tell the firmware not to shutdown the PHY if there was
no prior chip reset.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
2014-03-09 15:45:32 -08:00
committed by David S. Miller
parent c88507fbad
commit a8d9bc2e9f
2 changed files with 38 additions and 4 deletions
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37
drivers/net/ethernet/broadcom/bnx2.c
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@@ -2507,6 +2507,7 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
bp->fw_wr_seq++;
msg_data |= bp->fw_wr_seq;
bp->fw_last_msg = msg_data;
bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
@@ -4000,8 +4001,23 @@ bnx2_setup_wol(struct bnx2 *bp)
wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
}
if (!(bp->flags & BNX2_FLAG_NO_WOL))
bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 1, 0);
if (!(bp->flags & BNX2_FLAG_NO_WOL)) {
u32 val;
wol_msg |= BNX2_DRV_MSG_DATA_WAIT3;
if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {
bnx2_fw_sync(bp, wol_msg, 1, 0);
return;
}
/* Tell firmware not to power down the PHY yet, otherwise
* the chip will take a long time to respond to MMIO reads.
*/
val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,
val | BNX2_PORT_FEATURE_ASF_ENABLED);
bnx2_fw_sync(bp, wol_msg, 1, 0);
bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);
}
}
@@ -4033,9 +4049,22 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
if (bp->wol)
pci_set_power_state(bp->pdev, PCI_D3hot);
} else {
pci_set_power_state(bp->pdev, PCI_D3hot);
break;
}
if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {
u32 val;
/* Tell firmware not to power down the PHY yet,
* otherwise the other port may not respond to
* MMIO reads.
*/
val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
val &= ~BNX2_CONDITION_PM_STATE_MASK;
val |= BNX2_CONDITION_PM_STATE_UNPREP;
bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);
}
pci_set_power_state(bp->pdev, PCI_D3hot);
/* No more memory access after this point until
* device is brought back to D0.