KVM: VMX: Move VMX specific files to a "vmx" subdirectory
...to prepare for shattering vmx.c into multiple files without having to prepend "vmx_" to all new files. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Sean Christopherson
committed by
Paolo Bonzini
Paolo Bonzini
parent
3592cda6bc
commit
a821bab2d1
358
arch/x86/kvm/vmx/pmu_intel.c
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358
arch/x86/kvm/vmx/pmu_intel.c
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/*
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* KVM PMU support for Intel CPUs
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*
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* Copyright 2011 Red Hat, Inc. and/or its affiliates.
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*
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* Authors:
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* Avi Kivity <avi@redhat.com>
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* Gleb Natapov <gleb@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include <linux/types.h>
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#include <linux/kvm_host.h>
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#include <linux/perf_event.h>
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#include <asm/perf_event.h>
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#include "x86.h"
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#include "cpuid.h"
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#include "lapic.h"
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#include "pmu.h"
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static struct kvm_event_hw_type_mapping intel_arch_events[] = {
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/* Index must match CPUID 0x0A.EBX bit vector */
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[0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
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[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
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[2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES },
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[3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES },
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[4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
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[5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
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[6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
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[7] = { 0x00, 0x30, PERF_COUNT_HW_REF_CPU_CYCLES },
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};
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/* mapping between fixed pmc index and intel_arch_events array */
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static int fixed_pmc_events[] = {1, 0, 7};
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static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
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{
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int i;
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for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
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u8 new_ctrl = fixed_ctrl_field(data, i);
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u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);
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struct kvm_pmc *pmc;
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pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);
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if (old_ctrl == new_ctrl)
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continue;
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reprogram_fixed_counter(pmc, new_ctrl, i);
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}
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pmu->fixed_ctr_ctrl = data;
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}
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/* function is called when global control register has been updated. */
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static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)
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{
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int bit;
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u64 diff = pmu->global_ctrl ^ data;
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pmu->global_ctrl = data;
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for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
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reprogram_counter(pmu, bit);
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}
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static unsigned intel_find_arch_event(struct kvm_pmu *pmu,
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u8 event_select,
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u8 unit_mask)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(intel_arch_events); i++)
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if (intel_arch_events[i].eventsel == event_select
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&& intel_arch_events[i].unit_mask == unit_mask
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&& (pmu->available_event_types & (1 << i)))
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break;
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if (i == ARRAY_SIZE(intel_arch_events))
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return PERF_COUNT_HW_MAX;
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return intel_arch_events[i].event_type;
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}
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static unsigned intel_find_fixed_event(int idx)
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{
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if (idx >= ARRAY_SIZE(fixed_pmc_events))
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return PERF_COUNT_HW_MAX;
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return intel_arch_events[fixed_pmc_events[idx]].event_type;
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}
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/* check if a PMC is enabled by comparing it with globl_ctrl bits. */
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static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
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}
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static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
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{
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if (pmc_idx < INTEL_PMC_IDX_FIXED)
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return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx,
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MSR_P6_EVNTSEL0);
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else {
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u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED;
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return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);
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}
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}
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/* returns 0 if idx's corresponding MSR exists; otherwise returns 1. */
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static int intel_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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bool fixed = idx & (1u << 30);
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idx &= ~(3u << 30);
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return (!fixed && idx >= pmu->nr_arch_gp_counters) ||
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(fixed && idx >= pmu->nr_arch_fixed_counters);
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}
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static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu,
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unsigned idx)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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bool fixed = idx & (1u << 30);
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struct kvm_pmc *counters;
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idx &= ~(3u << 30);
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if (!fixed && idx >= pmu->nr_arch_gp_counters)
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return NULL;
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if (fixed && idx >= pmu->nr_arch_fixed_counters)
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return NULL;
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counters = fixed ? pmu->fixed_counters : pmu->gp_counters;
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return &counters[idx];
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}
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static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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int ret;
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switch (msr) {
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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case MSR_CORE_PERF_GLOBAL_STATUS:
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case MSR_CORE_PERF_GLOBAL_CTRL:
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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ret = pmu->version > 1;
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break;
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default:
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ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
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get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||
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get_fixed_pmc(pmu, msr);
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break;
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}
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return ret;
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}
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static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *pmc;
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switch (msr) {
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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*data = pmu->fixed_ctr_ctrl;
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return 0;
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case MSR_CORE_PERF_GLOBAL_STATUS:
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*data = pmu->global_status;
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return 0;
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case MSR_CORE_PERF_GLOBAL_CTRL:
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*data = pmu->global_ctrl;
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return 0;
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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*data = pmu->global_ovf_ctrl;
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return 0;
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default:
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if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
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(pmc = get_fixed_pmc(pmu, msr))) {
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*data = pmc_read_counter(pmc);
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return 0;
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} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
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*data = pmc->eventsel;
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return 0;
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}
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}
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return 1;
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}
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static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *pmc;
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u32 msr = msr_info->index;
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u64 data = msr_info->data;
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switch (msr) {
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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if (pmu->fixed_ctr_ctrl == data)
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return 0;
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if (!(data & 0xfffffffffffff444ull)) {
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reprogram_fixed_counters(pmu, data);
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return 0;
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}
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break;
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case MSR_CORE_PERF_GLOBAL_STATUS:
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if (msr_info->host_initiated) {
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pmu->global_status = data;
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return 0;
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}
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break; /* RO MSR */
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case MSR_CORE_PERF_GLOBAL_CTRL:
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if (pmu->global_ctrl == data)
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return 0;
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if (!(data & pmu->global_ctrl_mask)) {
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global_ctrl_changed(pmu, data);
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return 0;
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}
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break;
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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if (!(data & (pmu->global_ctrl_mask & ~(3ull<<62)))) {
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if (!msr_info->host_initiated)
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pmu->global_status &= ~data;
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pmu->global_ovf_ctrl = data;
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return 0;
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}
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break;
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default:
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if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
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(pmc = get_fixed_pmc(pmu, msr))) {
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if (!msr_info->host_initiated)
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data = (s64)(s32)data;
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pmc->counter += data - pmc_read_counter(pmc);
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return 0;
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} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
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if (data == pmc->eventsel)
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return 0;
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if (!(data & pmu->reserved_bits)) {
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reprogram_gp_counter(pmc, data);
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return 0;
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}
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}
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}
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return 1;
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}
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static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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struct kvm_cpuid_entry2 *entry;
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union cpuid10_eax eax;
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union cpuid10_edx edx;
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pmu->nr_arch_gp_counters = 0;
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pmu->nr_arch_fixed_counters = 0;
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pmu->counter_bitmask[KVM_PMC_GP] = 0;
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pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
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pmu->version = 0;
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pmu->reserved_bits = 0xffffffff00200000ull;
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entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
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if (!entry)
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return;
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eax.full = entry->eax;
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edx.full = entry->edx;
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pmu->version = eax.split.version_id;
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if (!pmu->version)
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return;
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pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
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INTEL_PMC_MAX_GENERIC);
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pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
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pmu->available_event_types = ~entry->ebx &
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((1ull << eax.split.mask_length) - 1);
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if (pmu->version == 1) {
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pmu->nr_arch_fixed_counters = 0;
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} else {
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pmu->nr_arch_fixed_counters =
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min_t(int, edx.split.num_counters_fixed,
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INTEL_PMC_MAX_FIXED);
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pmu->counter_bitmask[KVM_PMC_FIXED] =
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((u64)1 << edx.split.bit_width_fixed) - 1;
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}
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pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |
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(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
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pmu->global_ctrl_mask = ~pmu->global_ctrl;
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entry = kvm_find_cpuid_entry(vcpu, 7, 0);
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if (entry &&
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(boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
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(entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM)))
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pmu->reserved_bits ^= HSW_IN_TX|HSW_IN_TX_CHECKPOINTED;
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}
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static void intel_pmu_init(struct kvm_vcpu *vcpu)
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{
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int i;
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
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pmu->gp_counters[i].type = KVM_PMC_GP;
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pmu->gp_counters[i].vcpu = vcpu;
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pmu->gp_counters[i].idx = i;
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}
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for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
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pmu->fixed_counters[i].type = KVM_PMC_FIXED;
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pmu->fixed_counters[i].vcpu = vcpu;
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pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
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}
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}
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static void intel_pmu_reset(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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int i;
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for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
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struct kvm_pmc *pmc = &pmu->gp_counters[i];
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pmc_stop_counter(pmc);
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pmc->counter = pmc->eventsel = 0;
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}
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for (i = 0; i < INTEL_PMC_MAX_FIXED; i++)
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pmc_stop_counter(&pmu->fixed_counters[i]);
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pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
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pmu->global_ovf_ctrl = 0;
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}
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struct kvm_pmu_ops intel_pmu_ops = {
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.find_arch_event = intel_find_arch_event,
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.find_fixed_event = intel_find_fixed_event,
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.pmc_is_enabled = intel_pmc_is_enabled,
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.pmc_idx_to_pmc = intel_pmc_idx_to_pmc,
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.msr_idx_to_pmc = intel_msr_idx_to_pmc,
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.is_valid_msr_idx = intel_is_valid_msr_idx,
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.is_valid_msr = intel_is_valid_msr,
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.get_msr = intel_pmu_get_msr,
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.set_msr = intel_pmu_set_msr,
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.refresh = intel_pmu_refresh,
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.init = intel_pmu_init,
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.reset = intel_pmu_reset,
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};
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