dma-mapping: treat dev->bus_dma_mask as a DMA limit
Using a mask to represent bus DMA constraints has a set of limitations. The biggest one being it can only hold a power of two (minus one). The DMA mapping code is already aware of this and treats dev->bus_dma_mask as a limit. This quirk is already used by some architectures although still rare. With the introduction of the Raspberry Pi 4 we've found a new contender for the use of bus DMA limits, as its PCIe bus can only address the lower 3GB of memory (of a total of 4GB). This is impossible to represent with a mask. To make things worse the device-tree code rounds non power of two bus DMA limits to the next power of two, which is unacceptable in this case. In the light of this, rename dev->bus_dma_mask to dev->bus_dma_limit all over the tree and treat it as such. Note that dev->bus_dma_limit should contain the higher accessible DMA address. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
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committed by
Christoph Hellwig

parent
d7293f79ca
commit
a7ba70f178
@@ -27,10 +27,10 @@ static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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if (!dev->dma_mask) {
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dev_err_once(dev, "DMA map on device without dma_mask\n");
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} else if (*dev->dma_mask >= DMA_BIT_MASK(32) || dev->bus_dma_mask) {
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} else if (*dev->dma_mask >= DMA_BIT_MASK(32) || dev->bus_dma_limit) {
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dev_err_once(dev,
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"overflow %pad+%zu of DMA mask %llx bus mask %llx\n",
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&dma_addr, size, *dev->dma_mask, dev->bus_dma_mask);
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"overflow %pad+%zu of DMA mask %llx bus limit %llx\n",
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&dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
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}
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WARN_ON_ONCE(1);
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}
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@@ -57,15 +57,14 @@ u64 dma_direct_get_required_mask(struct device *dev)
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}
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static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
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u64 *phys_mask)
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u64 *phys_limit)
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{
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if (dev->bus_dma_mask && dev->bus_dma_mask < dma_mask)
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dma_mask = dev->bus_dma_mask;
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u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
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if (force_dma_unencrypted(dev))
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*phys_mask = __dma_to_phys(dev, dma_mask);
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*phys_limit = __dma_to_phys(dev, dma_limit);
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else
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*phys_mask = dma_to_phys(dev, dma_mask);
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*phys_limit = dma_to_phys(dev, dma_limit);
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/*
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* Optimistically try the zone that the physical address mask falls
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@@ -75,9 +74,9 @@ static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
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* Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
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* zones.
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*/
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if (*phys_mask <= DMA_BIT_MASK(zone_dma_bits))
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if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
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return GFP_DMA;
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if (*phys_mask <= DMA_BIT_MASK(32))
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if (*phys_limit <= DMA_BIT_MASK(32))
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return GFP_DMA32;
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return 0;
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}
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@@ -85,7 +84,7 @@ static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
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static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
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{
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return phys_to_dma_direct(dev, phys) + size - 1 <=
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min_not_zero(dev->coherent_dma_mask, dev->bus_dma_mask);
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min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
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}
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struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
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@@ -94,7 +93,7 @@ struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
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size_t alloc_size = PAGE_ALIGN(size);
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int node = dev_to_node(dev);
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struct page *page = NULL;
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u64 phys_mask;
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u64 phys_limit;
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if (attrs & DMA_ATTR_NO_WARN)
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gfp |= __GFP_NOWARN;
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@@ -102,7 +101,7 @@ struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
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/* we always manually zero the memory once we are done: */
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gfp &= ~__GFP_ZERO;
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gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
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&phys_mask);
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&phys_limit);
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page = dma_alloc_contiguous(dev, alloc_size, gfp);
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if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
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dma_free_contiguous(dev, page, alloc_size);
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@@ -116,7 +115,7 @@ again:
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page = NULL;
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if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
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phys_mask < DMA_BIT_MASK(64) &&
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phys_limit < DMA_BIT_MASK(64) &&
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!(gfp & (GFP_DMA32 | GFP_DMA))) {
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gfp |= GFP_DMA32;
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goto again;
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