Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "We have a small collection of core framework updates this time, mostly around clk registration by clk providers and debugfs "nice to haves" for rate constraints. I'll highlight that we're now setting the clk_init_data pointer inside struct clk_hw to NULL during clk_register(), which may break some drivers that thought they could use that pointer during normal operations. That change has been sitting in next for a while now but maybe something is still broken. We'l see. Other than that the core framework changes aren't invasive and they're fixing bugs, simplifying, and making things better. On the clk driver side we got the usual addition of new SoC support, new features for existing drivers, and bug fixes scattered throughout. The biggest diffstat is the Amlogic driver that gained CPU clk support in addition to migrating to the new way of specifying clk parents. After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and clock controllers from those vendors. Core: - Drop NULL checks in clk debugfs - Add min/max rates to clk debugfs - Set clk_init_data pointer inside clk_hw to NULL after registration - Make clk_bulk_get_all() return an 'id' corresponding to clock-names - Evict parents from parent cache when they're unregistered New Drivers: - Add clock driver for i.MX8MN SoCs - Support aspeed AST2600 SoCs - Support for Mediatek MT6779 SoCs - Support qcom SM8150 GCC and RPMh clks - Support qcom QCS404 WCSS clks - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807) - Addition of clock driver for Rockchip rk3308 SoCs Updates: - Add regulator support to the cdce925 clk driver - Add support for Raspberry Pi 4 bcm2711 SoCs - Add SDIO gate support to aspeed driver - Add missing of_node_put() calls in various clk drivers - Migrate Amlogic driver to new clock parent description method - Add DVFS support to Amlogic Meson g12 - Add Amlogic Meson g12a reset support to the axg audio clock controller - Add sm1 support to the Amlogic Meson g12a clock controller - Switch i.MX8MM clock driver to platform driver - Add Hifi4 DSP related clocks for i.MX8QXP SoC - Fix Audio PLL setting and parent clock for USB - Misc i.MX8 clock driver improvements and corrections - Set floor ops for Qualcomm SD clks so that rounding works - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1 - Enable the Allwinner V3 SoC and fix the i2s clock for H6" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: Drop !clk checks in debugfs dumping clk: imx: imx8mn: fix pll mux bit clk: imx: imx8mm: fix pll mux bit clk: imx: clk-pll14xx: unbypass PLL by default clk: imx: pll14xx: avoid glitch when set rate clk: mvebu: ap80x: add AP807 clock support clk: mvebu: ap806: Prepare the introduction of AP807 clock support clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver clk: mvebu: ap806: be more explicit on what SaR is clk: mvebu: ap80x-cpu: add AP807 CPU clock support clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock dt-bindings: ap806: Document AP807 clock compatible dt-bindings: ap80x: Document AP807 CPU clock compatible clk: sprd: add missing kfree clk: at91: allow 24 Mhz clock as input for PLL clk: Make clk_bulk_get_all() return a valid "id" clk: actions: Fix factor clk struct member access clk: qcom: rcg: Return failure for RCG update clk: remove extra ---help--- tags in Kconfig clk: add include guard to clk-conf.h ...
This commit is contained in:
Linus Torvalds
@@ -18,17 +18,19 @@ Clocks:
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-------
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The Device Tree node representing the AP806 system controller provides
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a number of clocks:
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The Device Tree node representing the AP806/AP807 system controller
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provides a number of clocks:
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- 0: clock of CPU cluster 0
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- 1: clock of CPU cluster 1
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- 0: reference clock of CPU cluster 0
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- 1: reference clock of CPU cluster 1
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- 2: fixed PLL at 1200 Mhz
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- 3: MSS clock, derived from the fixed PLL
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Required properties:
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- compatible: must be: "marvell,ap806-clock"
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- compatible: must be one of:
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* "marvell,ap806-clock"
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* "marvell,ap807-clock"
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- #clock-cells: must be set to 1
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Pinctrl:
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@@ -143,3 +145,33 @@ ap_syscon1: system-controller@6f8000 {
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#thermal-sensor-cells = <1>;
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};
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};
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Cluster clocks:
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---------------
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Device Tree Clock bindings for cluster clock of Marvell
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AP806/AP807. Each cluster contain up to 2 CPUs running at the same
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frequency.
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Required properties:
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- compatible: must be one of:
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* "marvell,ap806-cpu-clock"
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* "marvell,ap807-cpu-clock"
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- #clock-cells : should be set to 1.
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- clocks : shall be the input parent clock(s) phandle for the clock
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(one per cluster)
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- reg: register range associated with the cluster clocks
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ap_syscon1: system-controller@6f8000 {
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compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
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reg = <0x6f8000 0x1000>;
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cpu_clk: clock-cpu@278 {
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compatible = "marvell,ap806-cpu-clock";
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clocks = <&ap_clk 0>, <&ap_clk 1>;
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#clock-cells = <1>;
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reg = <0x278 0xa30>;
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};
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};
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-apmixedsys"
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- "mediatek,mt2712-apmixedsys", "syscon"
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- "mediatek,mt6779-apmixedsys", "syscon"
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- "mediatek,mt6797-apmixedsys"
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- "mediatek,mt7622-apmixedsys"
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- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt6779-audio", "syscon"
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- "mediatek,mt7622-audsys", "syscon"
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt8183-audiosys", "syscon"
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@@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt6779-camsys", "syscon"
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- "mediatek,mt8183-camsys", "syscon"
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- #clock-cells: Must be 1
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt2712-imgsys", "syscon"
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- "mediatek,mt6779-imgsys", "syscon"
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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@@ -9,6 +9,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt2712-infracfg", "syscon"
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- "mediatek,mt6779-infracfg_ao", "syscon"
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- "mediatek,mt6797-infracfg", "syscon"
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- "mediatek,mt7622-infracfg", "syscon"
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- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
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@@ -0,0 +1,22 @@
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Mediatek ipesys controller
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============================
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The Mediatek ipesys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt6779-ipesys", "syscon"
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- #clock-cells: Must be 1
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The ipesys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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ipesys: clock-controller@1b000000 {
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compatible = "mediatek,mt6779-ipesys", "syscon";
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reg = <0 0x1b000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-mfgcfg", "syscon"
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- "mediatek,mt6779-mfgcfg", "syscon"
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- "mediatek,mt8183-mfgcfg", "syscon"
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- #clock-cells: Must be 1
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt2712-mmsys", "syscon"
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- "mediatek,mt6779-mmsys", "syscon"
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- "mediatek,mt6797-mmsys", "syscon"
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- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt8173-mmsys", "syscon"
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@@ -14,6 +14,7 @@ Required Properties:
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- "mediatek,mt7629-pericfg", "syscon"
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- "mediatek,mt8135-pericfg", "syscon"
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- "mediatek,mt8173-pericfg", "syscon"
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- "mediatek,mt8183-pericfg", "syscon"
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- #clock-cells: Must be 1
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- #reset-cells: Must be 1
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-topckgen"
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- "mediatek,mt2712-topckgen", "syscon"
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- "mediatek,mt6779-topckgen", "syscon"
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- "mediatek,mt6797-topckgen"
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- "mediatek,mt7622-topckgen"
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- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt2712-vdecsys", "syscon"
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- "mediatek,mt6779-vdecsys", "syscon"
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- "mediatek,mt6797-vdecsys", "syscon"
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- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt8173-vdecsys", "syscon"
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-vencsys", "syscon"
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- "mediatek,mt6779-vencsys", "syscon"
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- "mediatek,mt6797-vencsys", "syscon"
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- "mediatek,mt8173-vencsys", "syscon"
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- "mediatek,mt8183-vencsys", "syscon"
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@@ -31,6 +31,7 @@ properties:
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- allwinner,sun8i-h3-ccu
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- allwinner,sun8i-h3-r-ccu
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- allwinner,sun8i-r40-ccu
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- allwinner,sun8i-v3-ccu
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- allwinner,sun8i-v3s-ccu
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- allwinner,sun9i-a80-ccu
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- allwinner,sun50i-a64-ccu
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@@ -12,7 +12,9 @@ clock generators, but a few (like the ARM or HDMI) will source from
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the PLL dividers directly.
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Required properties:
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- compatible: Should be "brcm,bcm2835-cprman"
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- compatible: should be one of the following,
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"brcm,bcm2711-cprman"
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"brcm,bcm2835-cprman"
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- #clock-cells: Should be <1>. The permitted clock-specifier values can be
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found in include/dt-bindings/clock/bcm2835.h
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- reg: Specifies base physical address and size of the registers
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@@ -23,6 +23,7 @@ Required properties :
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"qcom,gcc-sdm630"
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"qcom,gcc-sdm660"
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"qcom,gcc-sdm845"
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"qcom,gcc-sm8150"
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- reg : shall contain base register location and length
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- #clock-cells : shall contain 1
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@@ -38,6 +39,13 @@ Documentation/devicetree/bindings/thermal/qcom-tsens.txt
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- protected-clocks : Protected clock specifier list as per common clock
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binding.
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For SM8150 only:
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: "bi_tcxo" (required)
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"sleep_clk" (optional)
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"aud_ref_clock" (optional)
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Example:
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clock-controller@900000 {
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compatible = "qcom,gcc-msm8960";
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@@ -71,3 +79,16 @@ Example of GCC with protected-clocks properties:
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<GCC_LPASS_Q6_AXI_CLK>,
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<GCC_LPASS_SWAY_CLK>;
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};
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Example of GCC with clocks
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sm8150";
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reg = <0x00100000 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clock-names = "bi_tcxo",
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"sleep_clk";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&sleep_clk>;
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};
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@@ -6,9 +6,14 @@ some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
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other hardware subsystems via RSC to control clocks.
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Required properties :
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- compatible : shall contain "qcom,sdm845-rpmh-clk"
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- compatible : must be one of:
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"qcom,sdm845-rpmh-clk"
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"qcom,sm8150-rpmh-clk"
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- #clock-cells : must contain 1
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: Parent board clock: "xo".
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Example :
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@@ -0,0 +1,60 @@
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* Rockchip RK3308 Clock and Reset Unit
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The RK3308 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: CRU should be "rockchip,rk3308-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing, pll rates are not changeable, due to the missing pll lock status.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
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these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "xin32k" - rtc clock - optional,
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- "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
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"mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
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"mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
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- "mac_clkin" - external MAC clock - optional
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Example: Clock controller node:
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cru: clock-controller@ff500000 {
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compatible = "rockchip,rk3308-cru";
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reg = <0x0 0xff500000 0x0 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial@ff0a0000 {
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compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff0a0000 0x0 0x100>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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@@ -24,6 +24,8 @@ Required properties:
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Optional properties:
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- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
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board, or to compensate for external influences.
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- vdd-supply: A regulator node for Vdd
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- vddout-supply: A regulator node for Vddout
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For all PLL1, PLL2, ... an optional child node can be used to specify spread
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spectrum clocking parameters for a board.
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@@ -41,6 +43,8 @@ Example:
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clocks = <&xtal_27Mhz>;
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#clock-cells = <1>;
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xtal-load-pf = <5>;
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vdd-supply = <&1v8-reg>;
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vddout-supply = <&3v3-reg>;
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/* PLL options to get SSC 1% centered */
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PLL2 {
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spread-spectrum = <4>;
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