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MIPS: Netlogic: Split XLP L1 i-cache among threads

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Since we now use r4k cache code for Netlogic XLP, it is
better to split L1 icache among the active threads, so that
threads won't step on each other while flushing icache.

The L1 dcache is already split among the threads in the core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4787/
Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Jayachandran C
2013-01-14 15:11:56 +00:00
committed by John Crispin
parent a264b5e8dc
commit a69ba6293d
2 changed files with 8 additions and 0 deletions
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arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
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@@ -46,6 +46,8 @@
#define CPU_BLOCKID_FPU 9
#define CPU_BLOCKID_MAP 10
#define ICU_DEFEATURE 0x100
#define LSU_DEFEATURE 0x304
#define LSU_DEBUG_ADDR 0x305
#define LSU_DEBUG_DATA0 0x306