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arm: dts: mt7623: add BTIF, HSDMA and SPI-NOR device nodes

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add BTIF, HSDMA and SPI-NOR device nodes and enable it on relevant boards

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Sean Wang
2018-04-11 16:53:59 +08:00
committed by Matthias Brugger
parent 1c8fadd38f
commit a63e3d2ac6
2 changed files with 40 additions and 2 deletions
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36
arch/arm/boot/dts/mt7623.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Copyright (c) 2017 MediaTek Inc. * Copyright (c) 2017-2018 MediaTek Inc.
* Author: John Crispin <john@phrozen.org> * Author: John Crispin <john@phrozen.org>
* Sean Wang <sean.wang@mediatek.com> * Sean Wang <sean.wang@mediatek.com>
* *
@@ -486,6 +486,18 @@
nvmem-cell-names = "calibration-data"; nvmem-cell-names = "calibration-data";
}; };
btif: serial@1100c000 {
compatible = "mediatek,mt7623-btif",
"mediatek,mtk-btif";
reg = <0 0x1100c000 0 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_BTIF>;
clock-names = "main";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
nandc: nfi@1100d000 { nandc: nfi@1100d000 {
compatible = "mediatek,mt7623-nfc", compatible = "mediatek,mt7623-nfc",
"mediatek,mt2701-nfc"; "mediatek,mt2701-nfc";
@@ -511,6 +523,18 @@
status = "disabled"; status = "disabled";
}; };
nor_flash: spi@11014000 {
compatible = "mediatek,mt7623-nor",
"mediatek,mt8173-nor";
reg = <0 0x11014000 0 0x1000>;
clocks = <&pericfg CLK_PERI_FLASH>,
<&topckgen CLK_TOP_FLASH_SEL>;
clock-names = "spi", "sf";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@11016000 { spi1: spi@11016000 {
compatible = "mediatek,mt7623-spi", compatible = "mediatek,mt7623-spi",
"mediatek,mt2701-spi"; "mediatek,mt2701-spi";
@@ -861,6 +885,16 @@
#reset-cells = <1>; #reset-cells = <1>;
}; };
hsdma: dma-controller@1b007000 {
compatible = "mediatek,mt7623-hsdma";
reg = <0 0x1b007000 0 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
clocks = <&ethsys CLK_ETHSYS_HSDMA>;
clock-names = "hsdma";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
#dma-cells = <1>;
};
eth: ethernet@1b100000 { eth: ethernet@1b100000 {
compatible = "mediatek,mt7623-eth", compatible = "mediatek,mt7623-eth",
"mediatek,mt2701-eth", "mediatek,mt2701-eth",

6
arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright 2017 Sean Wang <sean.wang@mediatek.com> * Copyright 2017-2018 Sean Wang <sean.wang@mediatek.com>
* *
* SPDX-License-Identifier: (GPL-2.0+ OR MIT) * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/ */
@@ -114,6 +114,10 @@
}; };
}; };
&btif {
status = "okay";
};
&cir { &cir {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&cir_pins_a>; pinctrl-0 = <&cir_pins_a>;