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IB/mlx5: Add support for extended atomic operations

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Extended atomic operations cmp&swp and fetch&add is a Mellanox
feature extending the standard atomic operation to use, varied
operand sizes, as apposed to normal atomic operation that use
an 8 byte operand only.
Extended atomics allows masking the results and arguments.

This patch configures QP to support extended atomic operation
with the maximum size possible, as exposed by HCA capabilities.

Signed-off-by: Yonatan Cohen <yonatanc@mellanox.com>
Reviewed-by: Guy Levi <guyle@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Yonatan Cohen
2018-10-10 09:25:16 +03:00
committed by Doug Ledford
parent 76d865b87c
commit a60109dc9a
2 changed files with 96 additions and 25 deletions
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23
include/linux/mlx5/driver.h
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@@ -97,14 +97,15 @@ enum {
};
enum {
MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
MLX5_ATOMIC_MODE_CX = 2 << 16,
MLX5_ATOMIC_MODE_8B = 3 << 16,
MLX5_ATOMIC_MODE_16B = 4 << 16,
MLX5_ATOMIC_MODE_32B = 5 << 16,
MLX5_ATOMIC_MODE_64B = 6 << 16,
MLX5_ATOMIC_MODE_128B = 7 << 16,
MLX5_ATOMIC_MODE_256B = 8 << 16,
MLX5_ATOMIC_MODE_OFFSET = 16,
MLX5_ATOMIC_MODE_IB_COMP = 1,
MLX5_ATOMIC_MODE_CX = 2,
MLX5_ATOMIC_MODE_8B = 3,
MLX5_ATOMIC_MODE_16B = 4,
MLX5_ATOMIC_MODE_32B = 5,
MLX5_ATOMIC_MODE_64B = 6,
MLX5_ATOMIC_MODE_128B = 7,
MLX5_ATOMIC_MODE_256B = 8,
};
enum {
@@ -162,13 +163,11 @@ enum mlx5_dcbx_oper_mode {
MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
};
enum mlx5_dct_atomic_mode {
MLX5_ATOMIC_MODE_DCT_CX = 2,
};
enum {
MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
};
enum mlx5_page_fault_resume_flags {