Use physical addresses at the interface level, letting drivers remap
them as appropriate. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
committed by
Ralf Baechle
Ralf Baechle
parent
7d7ee22121
commit
a5fc9c0bbe
@@ -10,31 +10,29 @@
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* Copyright (c) Harald Koerfgen, 1998
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* Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki
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*/
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/bug.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/paccess.h>
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#include <asm/dec/machtype.h>
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#include <asm/dec/prom.h>
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#include <asm/dec/tcinfo.h>
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#include <asm/dec/tcmodule.h>
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#include <asm/dec/interrupts.h>
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#include <asm/paccess.h>
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#include <asm/ptrace.h>
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#define TC_DEBUG
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MODULE_LICENSE("GPL");
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slot_info tc_bus[MAX_SLOT];
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static int num_tcslots;
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static tcinfo *info;
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unsigned long system_base;
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/*
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* Interface to the world. Read comment in include/asm-mips/tc.h.
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*/
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@@ -97,13 +95,16 @@ unsigned long get_tc_speed(void)
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static void __init tc_probe(unsigned long startaddr, unsigned long size,
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int slots)
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{
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unsigned long slotaddr;
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int i, slot, err;
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long offset;
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unsigned char pattern[4];
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unsigned char *module;
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u8 pattern[4];
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volatile u8 *module;
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for (slot = 0; slot < slots; slot++) {
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module = (char *)(startaddr + slot * size);
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slotaddr = startaddr + slot * size;
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module = ioremap_nocache(slotaddr, size);
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BUG_ON(!module);
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offset = OLDCARD;
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@@ -112,8 +113,10 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
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err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1);
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err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2);
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err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3);
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if (err)
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if (err) {
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iounmap(module);
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continue;
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}
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if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
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pattern[2] != 0xaa || pattern[3] != 0xff) {
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@@ -124,16 +127,20 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
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err |= get_dbe(pattern[1], module + TC_PATTERN1);
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err |= get_dbe(pattern[2], module + TC_PATTERN2);
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err |= get_dbe(pattern[3], module + TC_PATTERN3);
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if (err)
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if (err) {
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iounmap(module);
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continue;
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}
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}
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if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
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pattern[2] != 0xaa || pattern[3] != 0xff)
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pattern[2] != 0xaa || pattern[3] != 0xff) {
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iounmap(module);
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continue;
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}
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tc_bus[slot].base_addr = (unsigned long)module;
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for(i = 0; i < 8; i++) {
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tc_bus[slot].base_addr = slotaddr;
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for (i = 0; i < 8; i++) {
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tc_bus[slot].firmware[i] =
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module[TC_FIRM_VER + offset + 4 * i];
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tc_bus[slot].vendor[i] =
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@@ -171,6 +178,8 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
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tc_bus[slot].interrupt = -1;
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break;
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}
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iounmap(module);
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}
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}
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@@ -196,8 +205,8 @@ static int __init tc_init(void)
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tc_bus[i].flags = FREE;
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}
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info = (tcinfo *) rex_gettcinfo();
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slot0addr = (unsigned long)CKSEG1ADDR(rex_slot_address(0));
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info = rex_gettcinfo();
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slot0addr = CPHYSADDR((long)rex_slot_address(0));
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switch (mips_machtype) {
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case MACH_DS5000_200:
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@@ -216,35 +225,21 @@ static int __init tc_init(void)
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tc_clock = 10000 / info->clk_period;
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if (TURBOCHANNEL && info->slot_size && slot0addr) {
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printk("TURBOchannel rev. %1d at %2d.%1d MHz ", info->revision,
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tc_clock / 10, tc_clock % 10);
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printk("(with%s parity)\n", info->parity ? "" : "out");
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if (info->slot_size && slot0addr) {
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pr_info("TURBOchannel rev. %d at %d.%d MHz (with%s parity)\n",
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info->revision, tc_clock / 10, tc_clock % 10,
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info->parity ? "" : "out");
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slot_size = info->slot_size << 20;
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tc_probe(slot0addr, slot_size, num_tcslots);
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/*
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* All TURBOchannel DECstations have the onboard devices
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* where the (num_tcslots + 0 or 1 on DS5k/xx) Option Module
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* would be.
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*/
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if(mips_machtype == MACH_DS5000_XX)
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i = 1;
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else
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i = 0;
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system_base = slot0addr + slot_size * (num_tcslots + i);
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#ifdef TC_DEBUG
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for (i = 0; i < num_tcslots; i++)
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if (tc_bus[i].base_addr) {
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printk(" slot %d: ", i);
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printk("%s %s %s\n", tc_bus[i].vendor,
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tc_bus[i].name, tc_bus[i].firmware);
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}
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#endif
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for (i = 0; i < num_tcslots; i++) {
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if (!tc_bus[i].base_addr)
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continue;
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pr_info(" slot %d: %s %s %s\n", i, tc_bus[i].vendor,
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tc_bus[i].name, tc_bus[i].firmware);
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}
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}
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return 0;
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@@ -258,4 +253,3 @@ EXPORT_SYMBOL(release_tc_card);
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EXPORT_SYMBOL(get_tc_base_addr);
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EXPORT_SYMBOL(get_tc_irq_nr);
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EXPORT_SYMBOL(get_tc_speed);
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EXPORT_SYMBOL(system_base);
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@@ -65,14 +65,14 @@
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/bootinfo.h>
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#include <asm/dec/serial.h>
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#ifdef CONFIG_MACH_DECSTATION
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#include <asm/dec/interrupts.h>
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#include <asm/dec/machtype.h>
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#include <asm/dec/tc.h>
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#include <asm/dec/ioasic_addrs.h>
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#endif
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#include <asm/dec/machtype.h>
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#include <asm/dec/serial.h>
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#include <asm/dec/system.h>
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#include <asm/dec/tc.h>
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#ifdef CONFIG_KGDB
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#include <asm/kgdb.h>
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#endif
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@@ -1616,30 +1616,22 @@ static void __init probe_sccs(void)
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return;
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}
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/*
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* When serial console is activated, tc_init has not been called yet
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* and system_base is undefined. Unfortunately we have to hardcode
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* system_base for this case :-(. HK
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*/
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switch(mips_machtype) {
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#ifdef CONFIG_MACH_DECSTATION
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case MACH_DS5000_2X0:
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case MACH_DS5900:
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system_base = CKSEG1ADDR(0x1f800000);
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n_chips = 2;
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zs_parms = &ds_parms;
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zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
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zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
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break;
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case MACH_DS5000_1XX:
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system_base = CKSEG1ADDR(0x1c000000);
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n_chips = 2;
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zs_parms = &ds_parms;
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zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
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zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
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break;
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case MACH_DS5000_XX:
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system_base = CKSEG1ADDR(0x1c000000);
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n_chips = 1;
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zs_parms = &ds_parms;
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zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
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@@ -1661,10 +1653,10 @@ static void __init probe_sccs(void)
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* The sccs reside on the high byte of the 16 bit IOBUS
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*/
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zs_channels[n_channels].control =
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(volatile unsigned char *)system_base +
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(volatile void *)CKSEG1ADDR(dec_kn_slot_base +
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(0 == chip ? zs_parms->scc0 : zs_parms->scc1) +
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(0 == channel ? zs_parms->channel_a_offset :
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zs_parms->channel_b_offset);
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zs_parms->channel_b_offset));
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zs_channels[n_channels].data =
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zs_channels[n_channels].control + 4;
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