Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu updates from Ingo Molnar: "The biggest changes are an extension of the Intel RDT code to extend it with Intel Memory Bandwidth Allocation CPU support: MBA allows bandwidth allocation between cores, while CBM (already upstream) allows CPU cache partitioning. There's also misc smaller fixes and updates" * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits) x86/intel_rdt: Return error for incorrect resource names in schemata x86/intel_rdt: Trim whitespace while parsing schemata input x86/intel_rdt: Fix padding when resource is enabled via mount x86/intel_rdt: Get rid of anon union x86/cpu: Keep model defines sorted by model number x86/intel_rdt/mba: Add schemata file support for MBA x86/intel_rdt: Make schemata file parsers resource specific x86/intel_rdt/mba: Add info directory files for Memory Bandwidth Allocation x86/intel_rdt: Make information files resource specific x86/intel_rdt/mba: Add primary support for Memory Bandwidth Allocation (MBA) x86/intel_rdt/mba: Memory bandwith allocation feature detect x86/intel_rdt: Add resource specific msr update function x86/intel_rdt: Move CBM specific data into a struct x86/intel_rdt: Cleanup namespace to support multiple resource types Documentation, x86: Intel Memory bandwidth allocation x86/intel_rdt: Organize code properly x86/intel_rdt: Init padding only if a device exists x86/intel_rdt: Add cpus_list rdtgroup file x86/intel_rdt: Cleanup kernel-doc x86/intel_rdt: Update schemata read to show data in tabular format ...
This commit is contained in:
Linus Torvalds
@@ -202,6 +202,8 @@
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#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
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@@ -12,6 +12,7 @@
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*/
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#define INTEL_FAM6_CORE_YONAH 0x0E
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#define INTEL_FAM6_CORE2_MEROM 0x0F
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#define INTEL_FAM6_CORE2_MEROM_L 0x16
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#define INTEL_FAM6_CORE2_PENRYN 0x17
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@@ -21,6 +22,7 @@
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#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
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#define INTEL_FAM6_NEHALEM_EP 0x1A
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#define INTEL_FAM6_NEHALEM_EX 0x2E
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#define INTEL_FAM6_WESTMERE 0x25
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#define INTEL_FAM6_WESTMERE_EP 0x2C
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#define INTEL_FAM6_WESTMERE_EX 0x2F
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@@ -36,9 +38,9 @@
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#define INTEL_FAM6_HASWELL_GT3E 0x46
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#define INTEL_FAM6_BROADWELL_CORE 0x3D
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#define INTEL_FAM6_BROADWELL_XEON_D 0x56
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#define INTEL_FAM6_BROADWELL_GT3E 0x47
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#define INTEL_FAM6_BROADWELL_X 0x4F
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#define INTEL_FAM6_BROADWELL_XEON_D 0x56
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#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
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#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
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@@ -59,8 +61,8 @@
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#define INTEL_FAM6_ATOM_MERRIFIELD 0x4A /* Tangier */
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#define INTEL_FAM6_ATOM_MOOREFIELD 0x5A /* Anniedale */
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C
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#define INTEL_FAM6_ATOM_GEMINI_LAKE 0x7A
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#define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */
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#define INTEL_FAM6_ATOM_GEMINI_LAKE 0x7A
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/* Xeon Phi */
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@@ -12,6 +12,7 @@
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#define IA32_L3_QOS_CFG 0xc81
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#define IA32_L3_CBM_BASE 0xc90
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#define IA32_L2_CBM_BASE 0xd10
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#define IA32_MBA_THRTL_BASE 0xd50
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#define L3_QOS_CDP_ENABLE 0x01ULL
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@@ -37,23 +38,30 @@ struct rdtgroup {
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/* rdtgroup.flags */
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#define RDT_DELETED 1
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/* rftype.flags */
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#define RFTYPE_FLAGS_CPUS_LIST 1
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/* List of all resource groups */
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extern struct list_head rdt_all_groups;
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extern int max_name_width, max_data_width;
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int __init rdtgroup_init(void);
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/**
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* struct rftype - describe each file in the resctrl file system
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* @name: file name
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* @mode: access mode
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* @kf_ops: operations
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* @seq_show: show content of the file
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* @write: write to the file
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* @name: File name
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* @mode: Access mode
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* @kf_ops: File operations
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* @flags: File specific RFTYPE_FLAGS_* flags
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* @seq_show: Show content of the file
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* @write: Write to the file
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*/
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struct rftype {
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char *name;
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umode_t mode;
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struct kernfs_ops *kf_ops;
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unsigned long flags;
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int (*seq_show)(struct kernfs_open_file *of,
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struct seq_file *sf, void *v);
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@@ -66,55 +74,22 @@ struct rftype {
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char *buf, size_t nbytes, loff_t off);
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};
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/**
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* struct rdt_resource - attributes of an RDT resource
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* @enabled: Is this feature enabled on this machine
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* @capable: Is this feature available on this machine
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* @name: Name to use in "schemata" file
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* @num_closid: Number of CLOSIDs available
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* @max_cbm: Largest Cache Bit Mask allowed
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* @min_cbm_bits: Minimum number of consecutive bits to be set
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* in a cache bit mask
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* @domains: All domains for this resource
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* @num_domains: Number of domains active
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* @msr_base: Base MSR address for CBMs
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* @tmp_cbms: Scratch space when updating schemata
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* @num_tmp_cbms: Number of CBMs in tmp_cbms
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* @cache_level: Which cache level defines scope of this domain
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* @cbm_idx_multi: Multiplier of CBM index
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* @cbm_idx_offset: Offset of CBM index. CBM index is computed by:
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* closid * cbm_idx_multi + cbm_idx_offset
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*/
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struct rdt_resource {
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bool enabled;
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bool capable;
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char *name;
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int num_closid;
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int cbm_len;
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int min_cbm_bits;
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u32 max_cbm;
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struct list_head domains;
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int num_domains;
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int msr_base;
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u32 *tmp_cbms;
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int num_tmp_cbms;
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int cache_level;
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int cbm_idx_multi;
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int cbm_idx_offset;
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};
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/**
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* struct rdt_domain - group of cpus sharing an RDT resource
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* @list: all instances of this resource
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* @id: unique id for this instance
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* @cpu_mask: which cpus share this resource
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* @cbm: array of cache bit masks (indexed by CLOSID)
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* @ctrl_val: array of cache or mem ctrl values (indexed by CLOSID)
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* @new_ctrl: new ctrl value to be loaded
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* @have_new_ctrl: did user provide new_ctrl for this domain
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*/
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struct rdt_domain {
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struct list_head list;
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int id;
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struct cpumask cpu_mask;
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u32 *cbm;
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u32 *ctrl_val;
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u32 new_ctrl;
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bool have_new_ctrl;
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};
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/**
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@@ -129,6 +104,83 @@ struct msr_param {
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int high;
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};
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/**
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* struct rdt_cache - Cache allocation related data
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* @cbm_len: Length of the cache bit mask
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* @min_cbm_bits: Minimum number of consecutive bits to be set
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* @cbm_idx_mult: Multiplier of CBM index
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* @cbm_idx_offset: Offset of CBM index. CBM index is computed by:
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* closid * cbm_idx_multi + cbm_idx_offset
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* in a cache bit mask
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*/
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struct rdt_cache {
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unsigned int cbm_len;
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unsigned int min_cbm_bits;
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unsigned int cbm_idx_mult;
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unsigned int cbm_idx_offset;
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};
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/**
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* struct rdt_membw - Memory bandwidth allocation related data
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* @max_delay: Max throttle delay. Delay is the hardware
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* representation for memory bandwidth.
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* @min_bw: Minimum memory bandwidth percentage user can request
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* @bw_gran: Granularity at which the memory bandwidth is allocated
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* @delay_linear: True if memory B/W delay is in linear scale
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* @mb_map: Mapping of memory B/W percentage to memory B/W delay
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*/
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struct rdt_membw {
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u32 max_delay;
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u32 min_bw;
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u32 bw_gran;
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u32 delay_linear;
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u32 *mb_map;
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};
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/**
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* struct rdt_resource - attributes of an RDT resource
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* @enabled: Is this feature enabled on this machine
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* @capable: Is this feature available on this machine
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* @name: Name to use in "schemata" file
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* @num_closid: Number of CLOSIDs available
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* @cache_level: Which cache level defines scope of this resource
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* @default_ctrl: Specifies default cache cbm or memory B/W percent.
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* @msr_base: Base MSR address for CBMs
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* @msr_update: Function pointer to update QOS MSRs
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* @data_width: Character width of data when displaying
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* @domains: All domains for this resource
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* @cache: Cache allocation related data
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* @info_files: resctrl info files for the resource
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* @nr_info_files: Number of info files
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* @format_str: Per resource format string to show domain value
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* @parse_ctrlval: Per resource function pointer to parse control values
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*/
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struct rdt_resource {
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bool enabled;
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bool capable;
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char *name;
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int num_closid;
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int cache_level;
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u32 default_ctrl;
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unsigned int msr_base;
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void (*msr_update) (struct rdt_domain *d, struct msr_param *m,
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struct rdt_resource *r);
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int data_width;
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struct list_head domains;
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struct rdt_cache cache;
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struct rdt_membw membw;
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struct rftype *info_files;
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int nr_info_files;
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const char *format_str;
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int (*parse_ctrlval) (char *buf, struct rdt_resource *r,
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struct rdt_domain *d);
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};
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void rdt_get_cache_infofile(struct rdt_resource *r);
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void rdt_get_mba_infofile(struct rdt_resource *r);
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int parse_cbm(char *buf, struct rdt_resource *r, struct rdt_domain *d);
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int parse_bw(char *buf, struct rdt_resource *r, struct rdt_domain *d);
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extern struct mutex rdtgroup_mutex;
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extern struct rdt_resource rdt_resources_all[];
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@@ -142,6 +194,7 @@ enum {
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RDT_RESOURCE_L3DATA,
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RDT_RESOURCE_L3CODE,
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RDT_RESOURCE_L2,
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RDT_RESOURCE_MBA,
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/* Must be the last */
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RDT_NUM_RESOURCES,
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@@ -149,7 +202,7 @@ enum {
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#define for_each_capable_rdt_resource(r) \
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for (r = rdt_resources_all; r < rdt_resources_all + RDT_NUM_RESOURCES;\
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r++) \
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r++) \
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if (r->capable)
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#define for_each_enabled_rdt_resource(r) \
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@@ -165,8 +218,16 @@ union cpuid_0x10_1_eax {
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unsigned int full;
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};
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/* CPUID.(EAX=10H, ECX=ResID=1).EDX */
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union cpuid_0x10_1_edx {
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/* CPUID.(EAX=10H, ECX=ResID=3).EAX */
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union cpuid_0x10_3_eax {
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struct {
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unsigned int max_delay:12;
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} split;
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unsigned int full;
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};
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/* CPUID.(EAX=10H, ECX=ResID).EDX */
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union cpuid_0x10_x_edx {
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struct {
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unsigned int cos_max:16;
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} split;
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@@ -175,7 +236,7 @@ union cpuid_0x10_1_edx {
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DECLARE_PER_CPU_READ_MOSTLY(int, cpu_closid);
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void rdt_cbm_update(void *arg);
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void rdt_ctrl_update(void *arg);
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struct rdtgroup *rdtgroup_kn_lock_live(struct kernfs_node *kn);
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void rdtgroup_kn_unlock(struct kernfs_node *kn);
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ssize_t rdtgroup_schemata_write(struct kernfs_open_file *of,
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@@ -80,7 +80,7 @@ extern u16 __read_mostly tlb_lld_1g[NR_INFO];
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/*
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* CPU type and hardware bug flags. Kept separately for each CPU.
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* Members of this structure are referenced in head.S, so think twice
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* Members of this structure are referenced in head_32.S, so think twice
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* before touching them. [mj]
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*/
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@@ -89,14 +89,7 @@ struct cpuinfo_x86 {
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__u8 x86_vendor; /* CPU vendor */
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__u8 x86_model;
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__u8 x86_mask;
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#ifdef CONFIG_X86_32
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char wp_works_ok; /* It doesn't on 386's */
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/* Problems on some 486Dx4's and old 386's: */
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char rfu;
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char pad0;
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char pad1;
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#else
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#ifdef CONFIG_X86_64
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/* Number of 4K pages in DTLB/ITLB combined(in pages): */
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int x86_tlbsize;
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#endif
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