ARC: [plat-hsdk] initial port for HSDK board
This initial port adds support of ARC HS Development Kit board with some basic features such serial port, USB, SD/MMC and Ethernet. Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and heavily use IO Coherency for speeding-up DMA-aware peripherals. Note as opposed to other ARC boards we link Linux kernel to 0x9000_0000 intentionally because cores 1 and 3 configured with DCCM situated at our more usual link base 0x8000_0000. We still can use memory region starting at 0x8000_0000 as we reallocate DCCM in our platform code. Note that PAE remapping for DMA clients does not work due to an RTL bug, so CREG_PAE register must be programmed to all zeroes, otherwise it will cause problems with DMA to/from peripherals even if PAE40 is not used. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Alexey Brodkin
committed by
Vineet Gupta
Vineet Gupta
parent
9ed68785f7
commit
a518d63777
189
arch/arc/boot/dts/hsdk.dts
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189
arch/arc/boot/dts/hsdk.dts
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/*
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* Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Device Tree for ARC HS Development Kit
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*/
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/dts-v1/;
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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model = "snps,hsdk";
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compatible = "snps,hsdk";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <0>;
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clocks = <&core_clk>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <1>;
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clocks = <&core_clk>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <2>;
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clocks = <&core_clk>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <3>;
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clocks = <&core_clk>;
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};
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};
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core_clk: core-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <500000000>;
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};
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cpu_intc: cpu-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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};
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arcpct: pct {
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compatible = "snps,archs-pct";
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};
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/* TIMER0 with interrupt for clockevent */
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timer {
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compatible = "snps,arc-timer";
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interrupts = <16>;
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interrupt-parent = <&cpu_intc>;
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clocks = <&core_clk>;
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};
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/* 64-bit Global Free Running Counter */
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gfrc {
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compatible = "snps,archs-timer-gfrc";
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clocks = <&core_clk>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&idu_intc>;
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ranges = <0x00000000 0xf0000000 0x10000000>;
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serial: serial@5000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x5000 0x100>;
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clock-frequency = <33330000>;
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interrupts = <6>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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gmacclk: gmacclk {
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compatible = "fixed-clock";
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clock-frequency = <400000000>;
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#clock-cells = <0>;
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};
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mmcclk_ciu: mmcclk-ciu {
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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#clock-cells = <0>;
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};
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mmcclk_biu: mmcclk-biu {
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compatible = "fixed-clock";
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clock-frequency = <400000000>;
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#clock-cells = <0>;
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};
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ethernet@8000 {
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#interrupt-cells = <1>;
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compatible = "snps,dwmac";
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reg = <0x8000 0x2000>;
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interrupts = <10>;
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interrupt-names = "macirq";
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phy-mode = "rgmii";
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snps,pbl = <32>;
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clocks = <&gmacclk>;
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clock-names = "stmmaceth";
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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};
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ohci@60000 {
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compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
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reg = <0x60000 0x100>;
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interrupts = <15>;
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};
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ehci@40000 {
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compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
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reg = <0x40000 0x100>;
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interrupts = <15>;
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};
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mmc@a000 {
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compatible = "altr,socfpga-dw-mshc";
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reg = <0xa000 0x400>;
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num-slots = <1>;
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fifo-depth = <16>;
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card-detect-delay = <200>;
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clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
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clock-names = "biu", "ciu";
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interrupts = <12>;
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bus-width = <4>;
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};
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};
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memory@80000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "memory";
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reg = <0x80000000 0x40000000>; /* 1 GiB */
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};
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};
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