drm/amdgpu: add gfx clock gating for raven
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
@@ -2877,6 +2877,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_VEGA10:
|
||||
case CHIP_RAVEN:
|
||||
gfx_v9_0_update_gfx_clock_gating(adev,
|
||||
state == AMD_CG_STATE_GATE ? true : false);
|
||||
break;
|
||||
@@ -3736,6 +3737,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_VEGA10:
|
||||
case CHIP_RAVEN:
|
||||
adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
|
||||
break;
|
||||
default:
|
||||
|
Reference in New Issue
Block a user