gpu: ipu-v3: Move IDMAC channel names to imx-ipu-v3.h
Move the IDMAC channel names to imx-ipu-v3.h, to make the names available outside IPU. Add a couple new channels in the process (async display BG/FG, channels 24 and 29). Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Philipp Zabel

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4cea940d34
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@@ -24,31 +24,6 @@ struct ipu_soc;
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#include <video/imx-ipu-v3.h>
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#define IPUV3_CHANNEL_CSI0 0
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#define IPUV3_CHANNEL_CSI1 1
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#define IPUV3_CHANNEL_CSI2 2
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#define IPUV3_CHANNEL_CSI3 3
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#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
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#define IPUV3_CHANNEL_MEM_IC_PP 11
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#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
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#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
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#define IPUV3_CHANNEL_G_MEM_IC_PP 15
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#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
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#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
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#define IPUV3_CHANNEL_IC_PP_MEM 22
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#define IPUV3_CHANNEL_MEM_BG_SYNC 23
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#define IPUV3_CHANNEL_MEM_FG_SYNC 27
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#define IPUV3_CHANNEL_MEM_DC_SYNC 28
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#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
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#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
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#define IPUV3_CHANNEL_MEM_ROT_ENC 45
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#define IPUV3_CHANNEL_MEM_ROT_VF 46
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#define IPUV3_CHANNEL_MEM_ROT_PP 47
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#define IPUV3_CHANNEL_ROT_ENC_MEM 48
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#define IPUV3_CHANNEL_ROT_VF_MEM 49
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#define IPUV3_CHANNEL_ROT_PP_MEM 50
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#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
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#define IPU_MCU_T_DEFAULT 8
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#define IPU_CM_IDMAC_REG_OFS 0x00008000
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#define IPU_CM_IC_REG_OFS 0x00020000
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