tg3: Make the TX BD DMA limit configurable

The 57766 ASIC rev will impose a new TX BD DMA limit on the driver.
This patch prepares for 57766 support by making the tx BD DMA limit
tunable.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
2011-12-14 11:09:58 +00:00
committed by David S. Miller
parent 4f27209605
commit a4cb428d31
2 changed files with 9 additions and 8 deletions

View File

@@ -2994,6 +2994,7 @@ struct tg3 {
/* begin "tx thread" cacheline section */
void (*write32_tx_mbox) (struct tg3 *, u32,
u32);
u32 dma_limit;
/* begin "rx thread" cacheline section */
struct tg3_napi napi[TG3_IRQ_MAX_VECS];