Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: mmp: pxa910: fix return value check in pxa910_clk_init() clk: mmp: pxa168: fix return value check in pxa168_clk_init() clk: mmp: mmp2: fix return value check in mmp2_clk_init() clk: qoriq: Don't allow CPU clocks higher than starting value
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@@ -740,6 +740,7 @@ static struct clk * __init create_mux_common(struct clockgen *cg,
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struct mux_hwclock *hwc,
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const struct clk_ops *ops,
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unsigned long min_rate,
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unsigned long max_rate,
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unsigned long pct80_rate,
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const char *fmt, int idx)
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{
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@@ -768,6 +769,8 @@ static struct clk * __init create_mux_common(struct clockgen *cg,
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continue;
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if (rate < min_rate)
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continue;
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if (rate > max_rate)
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continue;
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parent_names[j] = div->name;
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hwc->parent_to_clksel[j] = i;
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@@ -799,7 +802,7 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
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struct mux_hwclock *hwc;
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const struct clockgen_pll_div *div;
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unsigned long plat_rate, min_rate;
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u64 pct80_rate;
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u64 max_rate, pct80_rate;
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u32 clksel;
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hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
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@@ -827,8 +830,8 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
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return NULL;
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}
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pct80_rate = clk_get_rate(div->clk);
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pct80_rate *= 8;
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max_rate = clk_get_rate(div->clk);
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pct80_rate = max_rate * 8;
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do_div(pct80_rate, 10);
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plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
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@@ -838,7 +841,7 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
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else
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min_rate = plat_rate / 2;
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return create_mux_common(cg, hwc, &cmux_ops, min_rate,
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return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
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pct80_rate, "cg-cmux%d", idx);
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}
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@@ -853,7 +856,7 @@ static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
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hwc->reg = cg->regs + 0x20 * idx + 0x10;
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hwc->info = cg->info.hwaccel[idx];
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return create_mux_common(cg, hwc, &hwaccel_ops, 0, 0,
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return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
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"cg-hwaccel%d", idx);
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}
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