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Merge tag 'v4.10-rc2' into drm-intel-next-queued

Browse Source 
Backmerge Linux 4.10-rc2 to resync with our -fixes cherry-picks. I've
done the backmerge directly because Dave is on vacation.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
This commit is contained in:
Daniel Vetter
2017-01-04 11:34:01 +01:00
parent 7800fb69dd 0c744ea4f7
commit a402eae64d
10655 changed files with 667450 additions and 219622 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/acpi/acconfig.h
View File

@@ -146,7 +146,7 @@
/* Maximum number of While() loops before abort */
#define ACPI_MAX_LOOP_COUNT 0xFFFF
#define ACPI_MAX_LOOP_COUNT 0x000FFFFF
/******************************************************************************
*

2
include/acpi/acpi_bus.h
View File

@@ -573,6 +573,8 @@ struct acpi_pci_root {
bool acpi_dma_supported(struct acpi_device *adev);
enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev);
void acpi_dma_configure(struct device *dev, enum dev_dma_attr attr);
void acpi_dma_deconfigure(struct device *dev);
struct acpi_device *acpi_find_child_device(struct acpi_device *parent,
u64 address, bool check_children);

2
include/acpi/acpi_io.h
View File

@@ -13,6 +13,8 @@ static inline void __iomem *acpi_os_ioremap(acpi_physical_address phys,
}
#endif
extern bool acpi_permanent_mmap;
void __iomem *__ref
acpi_os_map_iomem(acpi_physical_address phys, acpi_size size);
void __ref acpi_os_unmap_iomem(void __iomem *virt, acpi_size size);

26
include/acpi/acpixf.h
View File

@@ -46,7 +46,7 @@
/* Current ACPICA subsystem version in YYYYMMDD format */
#define ACPI_CA_VERSION 0x20160831
#define ACPI_CA_VERSION 0x20160930
#include <acpi/acconfig.h>
#include <acpi/actypes.h>
@@ -258,6 +258,13 @@ ACPI_INIT_GLOBAL(u8, acpi_gbl_osi_data, 0);
*/
ACPI_INIT_GLOBAL(u8, acpi_gbl_reduced_hardware, FALSE);
/*
* Maximum number of While() loop iterations before forced method abort.
* This mechanism is intended to prevent infinite loops during interpreter
* execution within a host kernel.
*/
ACPI_INIT_GLOBAL(u32, acpi_gbl_max_loop_iterations, ACPI_MAX_LOOP_COUNT);
/*
* This mechanism is used to trace a specified AML method. The method is
* traced each time it is executed.
@@ -506,10 +513,12 @@ ACPI_EXTERNAL_RETURN_STATUS(acpi_status
acpi_get_table(acpi_string signature, u32 instance,
struct acpi_table_header
**out_table))
ACPI_EXTERNAL_RETURN_VOID(void acpi_put_table(struct acpi_table_header *table))
ACPI_EXTERNAL_RETURN_STATUS(acpi_status
acpi_get_table_by_index(u32 table_index,
struct acpi_table_header
**out_table))
acpi_get_table_by_index(u32 table_index,
struct acpi_table_header
**out_table))
ACPI_EXTERNAL_RETURN_STATUS(acpi_status
acpi_install_table_handler(acpi_table_handler
handler, void *context))
@@ -958,15 +967,6 @@ void acpi_terminate_debugger(void);
/*
* Divergences
*/
ACPI_GLOBAL(u8, acpi_gbl_permanent_mmap);
ACPI_EXTERNAL_RETURN_STATUS(acpi_status
acpi_get_table_with_size(acpi_string signature,
u32 instance,
struct acpi_table_header
**out_table,
acpi_size *tbl_size))
ACPI_EXTERNAL_RETURN_STATUS(acpi_status
acpi_get_data_full(acpi_handle object,
acpi_object_handler handler,

1
include/acpi/actbl.h
View File

@@ -371,6 +371,7 @@ struct acpi_table_desc {
union acpi_name_union signature;
acpi_owner_id owner_id;
u8 flags;
u16 validation_count;
};
/* Masks for Flags field above */

1
include/acpi/platform/aclinuxex.h
View File

@@ -142,7 +142,6 @@ static inline void acpi_os_terminate_command_signals(void)
/*
* OSL interfaces added by Linux
*/
void early_acpi_os_unmap_memory(void __iomem * virt, acpi_size size);
#endif /* __KERNEL__ */

3
include/acpi/processor.h
View File

@@ -249,6 +249,7 @@ extern int acpi_processor_register_performance(struct acpi_processor_performance
*performance, unsigned int cpu);
extern void acpi_processor_unregister_performance(unsigned int cpu);
int acpi_processor_pstate_control(void);
/* note: this locks both the calling module and the processor module
if a _PPC object exists, rmmod is disallowed then */
int acpi_processor_notify_smm(struct module *calling_module);
@@ -294,7 +295,7 @@ static inline void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx
#ifdef CONFIG_CPU_FREQ
void acpi_processor_ppc_init(void);
void acpi_processor_ppc_exit(void);
int acpi_processor_ppc_has_changed(struct acpi_processor *pr, int event_flag);
void acpi_processor_ppc_has_changed(struct acpi_processor *pr, int event_flag);
extern int acpi_processor_get_bios_limit(int cpu, unsigned int *limit);
#else
static inline void acpi_processor_ppc_init(void)

11
include/acpi/video.h
View File

@@ -30,6 +30,17 @@ struct acpi_device;
#define ACPI_VIDEO_DISPLAY_LEGACY_PANEL 0x0110
#define ACPI_VIDEO_DISPLAY_LEGACY_TV 0x0200
#define ACPI_VIDEO_NOTIFY_SWITCH 0x80
#define ACPI_VIDEO_NOTIFY_PROBE 0x81
#define ACPI_VIDEO_NOTIFY_CYCLE 0x82
#define ACPI_VIDEO_NOTIFY_NEXT_OUTPUT 0x83
#define ACPI_VIDEO_NOTIFY_PREV_OUTPUT 0x84
#define ACPI_VIDEO_NOTIFY_CYCLE_BRIGHTNESS 0x85
#define ACPI_VIDEO_NOTIFY_INC_BRIGHTNESS 0x86
#define ACPI_VIDEO_NOTIFY_DEC_BRIGHTNESS 0x87
#define ACPI_VIDEO_NOTIFY_ZERO_BRIGHTNESS 0x88
#define ACPI_VIDEO_NOTIFY_DISPLAY_OFF 0x89
enum acpi_backlight_type {
acpi_backlight_undef = -1,
acpi_backlight_none = 0,

7
include/asm-generic/asm-prototypes.h Normal file
View File

@@ -0,0 +1,7 @@
#include <linux/bitops.h>
extern void *__memset(void *, int, __kernel_size_t);
extern void *__memcpy(void *, const void *, __kernel_size_t);
extern void *__memmove(void *, const void *, __kernel_size_t);
extern void *memset(void *, int, __kernel_size_t);
extern void *memcpy(void *, const void *, __kernel_size_t);
extern void *memmove(void *, const void *, __kernel_size_t);

1
include/asm-generic/cputime_jiffies.h
View File

@@ -7,7 +7,6 @@ typedef unsigned long __nocast cputime_t;
#define cputime_one_jiffy jiffies_to_cputime(1)
#define cputime_to_jiffies(__ct) (__force unsigned long)(__ct)
#define cputime_to_scaled(__ct) (__ct)
#define jiffies_to_cputime(__hz) (__force cputime_t)(__hz)
typedef u64 __nocast cputime64_t;

1
include/asm-generic/cputime_nsecs.h
View File

@@ -34,7 +34,6 @@ typedef u64 __nocast cputime64_t;
*/
#define cputime_to_jiffies(__ct) \
cputime_div(__ct, NSEC_PER_SEC / HZ)
#define cputime_to_scaled(__ct) (__ct)
#define jiffies_to_cputime(__jif) \
(__force cputime_t)((__jif) * (NSEC_PER_SEC / HZ))
#define cputime64_to_jiffies64(__ct) \

1
include/asm-generic/export.h
View File

@@ -54,7 +54,6 @@ KSYM(__kstrtab_\name):
KSYM(__kcrctab_\name):
__put KSYM(__crc_\name)
.weak KSYM(__crc_\name)
.set KSYM(__crc_\name), 0
.previous
#endif
#endif

88
include/asm-generic/mutex-dec.h
View File

@@ -1,88 +0,0 @@
/*
* include/asm-generic/mutex-dec.h
*
* Generic implementation of the mutex fastpath, based on atomic
* decrement/increment.
*/
#ifndef _ASM_GENERIC_MUTEX_DEC_H
#define _ASM_GENERIC_MUTEX_DEC_H
/**
* __mutex_fastpath_lock - try to take the lock by moving the count
* from 1 to a 0 value
* @count: pointer of type atomic_t
* @fail_fn: function to call if the original value was not 1
*
* Change the count from 1 to a value lower than 1, and call <fail_fn> if
* it wasn't 1 originally. This function MUST leave the value lower than
* 1 even when the "1" assertion wasn't true.
*/
static inline void
__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
if (unlikely(atomic_dec_return_acquire(count) < 0))
fail_fn(count);
}
/**
* __mutex_fastpath_lock_retval - try to take the lock by moving the count
* from 1 to a 0 value
* @count: pointer of type atomic_t
*
* Change the count from 1 to a value lower than 1. This function returns 0
* if the fastpath succeeds, or -1 otherwise.
*/
static inline int
__mutex_fastpath_lock_retval(atomic_t *count)
{
if (unlikely(atomic_dec_return_acquire(count) < 0))
return -1;
return 0;
}
/**
* __mutex_fastpath_unlock - try to promote the count from 0 to 1
* @count: pointer of type atomic_t
* @fail_fn: function to call if the original value was not 0
*
* Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>.
* In the failure case, this function is allowed to either set the value to
* 1, or to set it to a value lower than 1.
*
* If the implementation sets it to a value of lower than 1, then the
* __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs
* to return 0 otherwise.
*/
static inline void
__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
if (unlikely(atomic_inc_return_release(count) <= 0))
fail_fn(count);
}
#define __mutex_slowpath_needs_to_unlock() 1
/**
* __mutex_fastpath_trylock - try to acquire the mutex, without waiting
*
* @count: pointer of type atomic_t
* @fail_fn: fallback function
*
* Change the count from 1 to a value lower than 1, and return 0 (failure)
* if it wasn't 1 originally, or return 1 (success) otherwise. This function
* MUST leave the value lower than 1 even when the "1" assertion wasn't true.
* Additionally, if the value was < 0 originally, this function must not leave
* it to 0 on failure.
*
* If the architecture has no effective trylock variant, it should call the
* <fail_fn> spinlock-based trylock variant unconditionally.
*/
static inline int
__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
{
if (likely(atomic_read(count) == 1 && atomic_cmpxchg_acquire(count, 1, 0) == 1))
return 1;
return 0;
}
#endif

19
include/asm-generic/mutex-null.h
View File

@@ -1,19 +0,0 @@
/*
* include/asm-generic/mutex-null.h
*
* Generic implementation of the mutex fastpath, based on NOP :-)
*
* This is used by the mutex-debugging infrastructure, but it can also
* be used by architectures that (for whatever reason) want to use the
* spinlock based slowpath.
*/
#ifndef _ASM_GENERIC_MUTEX_NULL_H
#define _ASM_GENERIC_MUTEX_NULL_H
#define __mutex_fastpath_lock(count, fail_fn) fail_fn(count)
#define __mutex_fastpath_lock_retval(count) (-1)
#define __mutex_fastpath_unlock(count, fail_fn) fail_fn(count)
#define __mutex_fastpath_trylock(count, fail_fn) fail_fn(count)
#define __mutex_slowpath_needs_to_unlock() 1
#endif

120
include/asm-generic/mutex-xchg.h
View File

@@ -1,120 +0,0 @@
/*
* include/asm-generic/mutex-xchg.h
*
* Generic implementation of the mutex fastpath, based on xchg().
*
* NOTE: An xchg based implementation might be less optimal than an atomic
* decrement/increment based implementation. If your architecture
* has a reasonable atomic dec/inc then you should probably use
* asm-generic/mutex-dec.h instead, or you could open-code an
* optimized version in asm/mutex.h.
*/
#ifndef _ASM_GENERIC_MUTEX_XCHG_H
#define _ASM_GENERIC_MUTEX_XCHG_H
/**
* __mutex_fastpath_lock - try to take the lock by moving the count
* from 1 to a 0 value
* @count: pointer of type atomic_t
* @fail_fn: function to call if the original value was not 1
*
* Change the count from 1 to a value lower than 1, and call <fail_fn> if it
* wasn't 1 originally. This function MUST leave the value lower than 1
* even when the "1" assertion wasn't true.
*/
static inline void
__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
if (unlikely(atomic_xchg(count, 0) != 1))
/*
* We failed to acquire the lock, so mark it contended
* to ensure that any waiting tasks are woken up by the
* unlock slow path.
*/
if (likely(atomic_xchg_acquire(count, -1) != 1))
fail_fn(count);
}
/**
* __mutex_fastpath_lock_retval - try to take the lock by moving the count
* from 1 to a 0 value
* @count: pointer of type atomic_t
*
* Change the count from 1 to a value lower than 1. This function returns 0
* if the fastpath succeeds, or -1 otherwise.
*/
static inline int
__mutex_fastpath_lock_retval(atomic_t *count)
{
if (unlikely(atomic_xchg_acquire(count, 0) != 1))
if (likely(atomic_xchg(count, -1) != 1))
return -1;
return 0;
}
/**
* __mutex_fastpath_unlock - try to promote the mutex from 0 to 1
* @count: pointer of type atomic_t
* @fail_fn: function to call if the original value was not 0
*
* try to promote the mutex from 0 to 1. if it wasn't 0, call <function>
* In the failure case, this function is allowed to either set the value to
* 1, or to set it to a value lower than one.
* If the implementation sets it to a value of lower than one, the
* __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs
* to return 0 otherwise.
*/
static inline void
__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
if (unlikely(atomic_xchg_release(count, 1) != 0))
fail_fn(count);
}
#define __mutex_slowpath_needs_to_unlock() 0
/**
* __mutex_fastpath_trylock - try to acquire the mutex, without waiting
*
* @count: pointer of type atomic_t
* @fail_fn: spinlock based trylock implementation
*
* Change the count from 1 to a value lower than 1, and return 0 (failure)
* if it wasn't 1 originally, or return 1 (success) otherwise. This function
* MUST leave the value lower than 1 even when the "1" assertion wasn't true.
* Additionally, if the value was < 0 originally, this function must not leave
* it to 0 on failure.
*
* If the architecture has no effective trylock variant, it should call the
* <fail_fn> spinlock-based trylock variant unconditionally.
*/
static inline int
__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
{
int prev;
if (atomic_read(count) != 1)
return 0;
prev = atomic_xchg_acquire(count, 0);
if (unlikely(prev < 0)) {
/*
* The lock was marked contended so we must restore that
* state. If while doing so we get back a prev value of 1
* then we just own it.
*
* [ In the rare case of the mutex going to 1, to 0, to -1
* and then back to 0 in this few-instructions window,
* this has the potential to trigger the slowpath for the
* owner's unlock path needlessly, but that's not a problem
* in practice. ]
*/
prev = atomic_xchg_acquire(count, prev);
if (prev < 0)
prev = 0;
}
return prev;
}
#endif

9
include/asm-generic/mutex.h
View File

@@ -1,9 +0,0 @@
#ifndef __ASM_GENERIC_MUTEX_H
#define __ASM_GENERIC_MUTEX_H
/*
* Pull in the generic implementation for the mutex fastpath,
* which is a reasonable default on many architectures.
*/
#include <asm-generic/mutex-dec.h>
#endif /* __ASM_GENERIC_MUTEX_H */

22
include/asm-generic/pgtable.h
View File

@@ -558,10 +558,9 @@ static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
* track_pfn_insert is called when a _new_ single pfn is established
* by vm_insert_pfn().
*/
static inline int track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
pfn_t pfn)
static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
pfn_t pfn)
{
return 0;
}
/*
@@ -593,8 +592,8 @@ static inline void untrack_pfn_moved(struct vm_area_struct *vma)
extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
unsigned long pfn, unsigned long addr,
unsigned long size);
extern int track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
pfn_t pfn);
extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
pfn_t pfn);
extern int track_pfn_copy(struct vm_area_struct *vma);
extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
unsigned long size);
@@ -653,18 +652,9 @@ static inline pmd_t pmd_read_atomic(pmd_t *pmdp)
}
#endif
#ifndef pmd_move_must_withdraw
static inline int pmd_move_must_withdraw(spinlock_t *new_pmd_ptl,
spinlock_t *old_pmd_ptl)
{
/*
* With split pmd lock we also need to move preallocated
* PTE page table if new_pmd is on different PMD page table.
*/
return new_pmd_ptl != old_pmd_ptl;
}
#ifndef arch_needs_pgtable_deposit
#define arch_needs_pgtable_deposit() (false)
#endif
/*
* This function is meant to be used by sites walking pagetables with
* the mmap_sem hold in read mode to protect against MADV_DONTNEED and

2
include/asm-generic/termios-base.h
View File

@@ -4,7 +4,7 @@
#ifndef _ASM_GENERIC_TERMIOS_BASE_H
#define _ASM_GENERIC_TERMIOS_BASE_H
#include <asm/uaccess.h>
#include <linux/uaccess.h>
#ifndef __ARCH_TERMIO_GETPUT

2
include/asm-generic/termios.h
View File

@@ -2,7 +2,7 @@
#define _ASM_GENERIC_TERMIOS_H
#include <asm/uaccess.h>
#include <linux/uaccess.h>
#include <uapi/asm-generic/termios.h>
/* intr=^C quit=^\ erase=del kill=^U

83
include/asm-generic/tlb.h
View File

@@ -107,11 +107,6 @@ struct mmu_gather {
struct mmu_gather_batch local;
struct page *__pages[MMU_GATHER_BUNDLE];
unsigned int batch_count;
/*
* __tlb_adjust_range will track the new addr here,
* that that we can adjust the range after the flush
*/
unsigned long addr;
int page_size;
};
@@ -125,16 +120,11 @@ extern bool __tlb_remove_page_size(struct mmu_gather *tlb, struct page *page,
int page_size);
static inline void __tlb_adjust_range(struct mmu_gather *tlb,
unsigned long address)
unsigned long address,
unsigned int range_size)
{
tlb->start = min(tlb->start, address);
tlb->end = max(tlb->end, address + PAGE_SIZE);
/*
* Track the last address with which we adjusted the range. This
* will be used later to adjust again after a mmu_flush due to
* failed __tlb_remove_page
*/
tlb->addr = address;
tlb->end = max(tlb->end, address + range_size);
}
static inline void __tlb_reset_range(struct mmu_gather *tlb)
@@ -150,15 +140,11 @@ static inline void __tlb_reset_range(struct mmu_gather *tlb)
static inline void tlb_remove_page_size(struct mmu_gather *tlb,
struct page *page, int page_size)
{
if (__tlb_remove_page_size(tlb, page, page_size)) {
if (__tlb_remove_page_size(tlb, page, page_size))
tlb_flush_mmu(tlb);
tlb->page_size = page_size;
__tlb_adjust_range(tlb, tlb->addr);
__tlb_remove_page_size(tlb, page, page_size);
}
}
static bool __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
static inline bool __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
return __tlb_remove_page_size(tlb, page, PAGE_SIZE);
}
@@ -172,14 +158,21 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
return tlb_remove_page_size(tlb, page, PAGE_SIZE);
}
static inline bool __tlb_remove_pte_page(struct mmu_gather *tlb, struct page *page)
#ifndef tlb_remove_check_page_size_change
#define tlb_remove_check_page_size_change tlb_remove_check_page_size_change
static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
unsigned int page_size)
{
/* active->nr should be zero when we call this */
VM_BUG_ON_PAGE(tlb->active->nr, page);
tlb->page_size = PAGE_SIZE;
__tlb_adjust_range(tlb, tlb->addr);
return __tlb_remove_page(tlb, page);
/*
* We don't care about page size change, just update
* mmu_gather page size here so that debug checks
* doesn't throw false warning.
*/
#ifdef CONFIG_DEBUG_VM
tlb->page_size = page_size;
#endif
}
#endif
/*
* In the case of tlb vma handling, we can optimise these away in the
@@ -215,10 +208,16 @@ static inline bool __tlb_remove_pte_page(struct mmu_gather *tlb, struct page *pa
*/
#define tlb_remove_tlb_entry(tlb, ptep, address) \
do { \
__tlb_adjust_range(tlb, address); \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
__tlb_remove_tlb_entry(tlb, ptep, address); \
} while (0)
#define tlb_remove_huge_tlb_entry(h, tlb, ptep, address) \
do { \
__tlb_adjust_range(tlb, address, huge_page_size(h)); \
__tlb_remove_tlb_entry(tlb, ptep, address); \
} while (0)
/**
* tlb_remove_pmd_tlb_entry - remember a pmd mapping for later tlb invalidation
* This is a nop so far, because only x86 needs it.
@@ -227,29 +226,47 @@ static inline bool __tlb_remove_pte_page(struct mmu_gather *tlb, struct page *pa
#define __tlb_remove_pmd_tlb_entry(tlb, pmdp, address) do {} while (0)
#endif
#define tlb_remove_pmd_tlb_entry(tlb, pmdp, address) \
do { \
__tlb_adjust_range(tlb, address); \
__tlb_remove_pmd_tlb_entry(tlb, pmdp, address); \
#define tlb_remove_pmd_tlb_entry(tlb, pmdp, address) \
do { \
__tlb_adjust_range(tlb, address, HPAGE_PMD_SIZE); \
__tlb_remove_pmd_tlb_entry(tlb, pmdp, address); \
} while (0)
/*
* For things like page tables caches (ie caching addresses "inside" the
* page tables, like x86 does), for legacy reasons, flushing an
* individual page had better flush the page table caches behind it. This
* is definitely how x86 works, for example. And if you have an
* architected non-legacy page table cache (which I'm not aware of
* anybody actually doing), you're going to have some architecturally
* explicit flushing for that, likely *separate* from a regular TLB entry
* flush, and thus you'd need more than just some range expansion..
*
* So if we ever find an architecture
* that would want something that odd, I think it is up to that
* architecture to do its own odd thing, not cause pain for others
* http://lkml.kernel.org/r/CA+55aFzBggoXtNXQeng5d_mRoDnaMBE5Y+URs+PHR67nUpMtaw@mail.gmail.com
*
* For now w.r.t page table cache, mark the range_size as PAGE_SIZE
*/
#define pte_free_tlb(tlb, ptep, address) \
do { \
__tlb_adjust_range(tlb, address); \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
__pte_free_tlb(tlb, ptep, address); \
} while (0)
#ifndef __ARCH_HAS_4LEVEL_HACK
#define pud_free_tlb(tlb, pudp, address) \
do { \
__tlb_adjust_range(tlb, address); \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
__pud_free_tlb(tlb, pudp, address); \
} while (0)
#endif
#define pmd_free_tlb(tlb, pmdp, address) \
do { \
__tlb_adjust_range(tlb, address); \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
__pmd_free_tlb(tlb, pmdp, address); \
} while (0)

69
include/asm-generic/vmlinux.lds.h
View File

@@ -114,7 +114,7 @@
#ifdef CONFIG_KPROBES
#define KPROBE_BLACKLIST() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_kprobe_blacklist) = .; \
*(_kprobe_blacklist) \
KEEP(*(_kprobe_blacklist)) \
VMLINUX_SYMBOL(__stop_kprobe_blacklist) = .;
#else
#define KPROBE_BLACKLIST()
@@ -123,10 +123,10 @@
#ifdef CONFIG_EVENT_TRACING
#define FTRACE_EVENTS() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_ftrace_events) = .; \
*(_ftrace_events) \
KEEP(*(_ftrace_events)) \
VMLINUX_SYMBOL(__stop_ftrace_events) = .; \
VMLINUX_SYMBOL(__start_ftrace_enum_maps) = .; \
*(_ftrace_enum_map) \
KEEP(*(_ftrace_enum_map)) \
VMLINUX_SYMBOL(__stop_ftrace_enum_maps) = .;
#else
#define FTRACE_EVENTS()
@@ -134,10 +134,10 @@
#ifdef CONFIG_TRACING
#define TRACE_PRINTKS() VMLINUX_SYMBOL(__start___trace_bprintk_fmt) = .; \
*(__trace_printk_fmt) /* Trace_printk fmt' pointer */ \
KEEP(*(__trace_printk_fmt)) /* Trace_printk fmt' pointer */ \
VMLINUX_SYMBOL(__stop___trace_bprintk_fmt) = .;
#define TRACEPOINT_STR() VMLINUX_SYMBOL(__start___tracepoint_str) = .; \
*(__tracepoint_str) /* Trace_printk fmt' pointer */ \
KEEP(*(__tracepoint_str)) /* Trace_printk fmt' pointer */ \
VMLINUX_SYMBOL(__stop___tracepoint_str) = .;
#else
#define TRACE_PRINTKS()
@@ -147,7 +147,7 @@
#ifdef CONFIG_FTRACE_SYSCALLS
#define TRACE_SYSCALLS() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_syscalls_metadata) = .; \
*(__syscalls_metadata) \
KEEP(*(__syscalls_metadata)) \
VMLINUX_SYMBOL(__stop_syscalls_metadata) = .;
#else
#define TRACE_SYSCALLS()
@@ -156,7 +156,7 @@
#ifdef CONFIG_SERIAL_EARLYCON
#define EARLYCON_TABLE() STRUCT_ALIGN(); \
VMLINUX_SYMBOL(__earlycon_table) = .; \
*(__earlycon_table) \
KEEP(*(__earlycon_table)) \
VMLINUX_SYMBOL(__earlycon_table_end) = .;
#else
#define EARLYCON_TABLE()
@@ -169,8 +169,8 @@
#define _OF_TABLE_1(name) \
. = ALIGN(8); \
VMLINUX_SYMBOL(__##name##_of_table) = .; \
*(__##name##_of_table) \
*(__##name##_of_table_end)
KEEP(*(__##name##_of_table)) \
KEEP(*(__##name##_of_table_end))
#define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc)
#define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip)
@@ -184,7 +184,7 @@
#define ACPI_PROBE_TABLE(name) \
. = ALIGN(8); \
VMLINUX_SYMBOL(__##name##_acpi_probe_table) = .; \
*(__##name##_acpi_probe_table) \
KEEP(*(__##name##_acpi_probe_table)) \
VMLINUX_SYMBOL(__##name##_acpi_probe_table_end) = .;
#else
#define ACPI_PROBE_TABLE(name)
@@ -193,7 +193,7 @@
#define KERNEL_DTB() \
STRUCT_ALIGN(); \
VMLINUX_SYMBOL(__dtb_start) = .; \
*(.dtb.init.rodata) \
KEEP(*(.dtb.init.rodata)) \
VMLINUX_SYMBOL(__dtb_end) = .;
/*
@@ -214,11 +214,11 @@
/* implement dynamic printk debug */ \
. = ALIGN(8); \
VMLINUX_SYMBOL(__start___jump_table) = .; \
*(__jump_table) \
KEEP(*(__jump_table)) \
VMLINUX_SYMBOL(__stop___jump_table) = .; \
. = ALIGN(8); \
VMLINUX_SYMBOL(__start___verbose) = .; \
*(__verbose) \
KEEP(*(__verbose)) \
VMLINUX_SYMBOL(__stop___verbose) = .; \
LIKELY_PROFILE() \
BRANCH_PROFILE() \
@@ -274,10 +274,10 @@
VMLINUX_SYMBOL(__start_rodata) = .; \
*(.rodata) *(.rodata.*) \
RO_AFTER_INIT_DATA /* Read only after init */ \
*(__vermagic) /* Kernel version magic */ \
KEEP(*(__vermagic)) /* Kernel version magic */ \
. = ALIGN(8); \
VMLINUX_SYMBOL(__start___tracepoints_ptrs) = .; \
*(__tracepoints_ptrs) /* Tracepoints: pointer array */\
KEEP(*(__tracepoints_ptrs)) /* Tracepoints: pointer array */ \
VMLINUX_SYMBOL(__stop___tracepoints_ptrs) = .; \
*(__tracepoints_strings)/* Tracepoints: strings */ \
} \
@@ -291,35 +291,35 @@
/* PCI quirks */ \
.pci_fixup : AT(ADDR(.pci_fixup) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start_pci_fixups_early) = .; \
*(.pci_fixup_early) \
KEEP(*(.pci_fixup_early)) \
VMLINUX_SYMBOL(__end_pci_fixups_early) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_header) = .; \
*(.pci_fixup_header) \
KEEP(*(.pci_fixup_header)) \
VMLINUX_SYMBOL(__end_pci_fixups_header) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_final) = .; \
*(.pci_fixup_final) \
KEEP(*(.pci_fixup_final)) \
VMLINUX_SYMBOL(__end_pci_fixups_final) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_enable) = .; \
*(.pci_fixup_enable) \
KEEP(*(.pci_fixup_enable)) \
VMLINUX_SYMBOL(__end_pci_fixups_enable) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_resume) = .; \
*(.pci_fixup_resume) \
KEEP(*(.pci_fixup_resume)) \
VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_resume_early) = .; \
*(.pci_fixup_resume_early) \
KEEP(*(.pci_fixup_resume_early)) \
VMLINUX_SYMBOL(__end_pci_fixups_resume_early) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \
*(.pci_fixup_suspend) \
KEEP(*(.pci_fixup_suspend)) \
VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_suspend_late) = .; \
*(.pci_fixup_suspend_late) \
KEEP(*(.pci_fixup_suspend_late)) \
VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \
} \
\
/* Built-in firmware blobs */ \
.builtin_fw : AT(ADDR(.builtin_fw) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start_builtin_fw) = .; \
*(.builtin_fw) \
KEEP(*(.builtin_fw)) \
VMLINUX_SYMBOL(__end_builtin_fw) = .; \
} \
\
@@ -397,7 +397,7 @@
\
/* Kernel symbol table: strings */ \
__ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) { \
KEEP(*(__ksymtab_strings)) \
*(__ksymtab_strings) \
} \
\
/* __*init sections */ \
@@ -410,14 +410,14 @@
/* Built-in module parameters. */ \
__param : AT(ADDR(__param) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___param) = .; \
*(__param) \
KEEP(*(__param)) \
VMLINUX_SYMBOL(__stop___param) = .; \
} \
\
/* Built-in module versions. */ \
__modver : AT(ADDR(__modver) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___modver) = .; \
*(__modver) \
KEEP(*(__modver)) \
VMLINUX_SYMBOL(__stop___modver) = .; \
. = ALIGN((align)); \
VMLINUX_SYMBOL(__end_rodata) = .; \
@@ -520,7 +520,7 @@
. = ALIGN(align); \
__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___ex_table) = .; \
*(__ex_table) \
KEEP(*(__ex_table)) \
VMLINUX_SYMBOL(__stop___ex_table) = .; \
}
@@ -536,9 +536,9 @@
#ifdef CONFIG_CONSTRUCTORS
#define KERNEL_CTORS() . = ALIGN(8); \
VMLINUX_SYMBOL(__ctors_start) = .; \
*(.ctors) \
*(SORT(.init_array.*)) \
*(.init_array) \
KEEP(*(.ctors)) \
KEEP(*(SORT(.init_array.*))) \
KEEP(*(.init_array)) \
VMLINUX_SYMBOL(__ctors_end) = .;
#else
#define KERNEL_CTORS()
@@ -566,6 +566,7 @@
IRQCHIP_OF_MATCH_TABLE() \
ACPI_PROBE_TABLE(irqchip) \
ACPI_PROBE_TABLE(clksrc) \
ACPI_PROBE_TABLE(iort) \
EARLYCON_TABLE()
#define INIT_TEXT \
@@ -662,7 +663,7 @@
. = ALIGN(8); \
__bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___bug_table) = .; \
*(__bug_table) \
KEEP(*(__bug_table)) \
VMLINUX_SYMBOL(__stop___bug_table) = .; \
}
#else
@@ -674,7 +675,7 @@
. = ALIGN(4); \
.tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__tracedata_start) = .; \
*(.tracedata) \
KEEP(*(.tracedata)) \
VMLINUX_SYMBOL(__tracedata_end) = .; \
}
#else
@@ -691,7 +692,7 @@
#define INIT_SETUP(initsetup_align) \
. = ALIGN(initsetup_align); \
VMLINUX_SYMBOL(__setup_start) = .; \
*(.init.setup) \
KEEP(*(.init.setup)) \
VMLINUX_SYMBOL(__setup_end) = .;
#define INIT_CALLS_LEVEL(level) \

3
include/clocksource/pxa.h
View File

@@ -12,7 +12,6 @@
#ifndef _CLOCKSOURCE_PXA_H
#define _CLOCKSOURCE_PXA_H
extern void pxa_timer_nodt_init(int irq, void __iomem *base,
unsigned long clock_tick_rate);
extern void pxa_timer_nodt_init(int irq, void __iomem *base);
#endif

269
include/crypto/acompress.h Normal file
View File

@@ -0,0 +1,269 @@
/*
* Asynchronous Compression operations
*
* Copyright (c) 2016, Intel Corporation
* Authors: Weigang Li <weigang.li@intel.com>
* Giovanni Cabiddu <giovanni.cabiddu@intel.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
*/
#ifndef _CRYPTO_ACOMP_H
#define _CRYPTO_ACOMP_H
#include <linux/crypto.h>
#define CRYPTO_ACOMP_ALLOC_OUTPUT 0x00000001
/**
* struct acomp_req - asynchronous (de)compression request
*
* @base: Common attributes for asynchronous crypto requests
* @src: Source Data
* @dst: Destination data
* @slen: Size of the input buffer
* @dlen: Size of the output buffer and number of bytes produced
* @flags: Internal flags
* @__ctx: Start of private context data
*/
struct acomp_req {
struct crypto_async_request base;
struct scatterlist *src;
struct scatterlist *dst;
unsigned int slen;
unsigned int dlen;
u32 flags;
void *__ctx[] CRYPTO_MINALIGN_ATTR;
};
/**
* struct crypto_acomp - user-instantiated objects which encapsulate
* algorithms and core processing logic
*
* @compress: Function performs a compress operation
* @decompress: Function performs a de-compress operation
* @dst_free: Frees destination buffer if allocated inside the
* algorithm
* @reqsize: Context size for (de)compression requests
* @base: Common crypto API algorithm data structure
*/
struct crypto_acomp {
int (*compress)(struct acomp_req *req);
int (*decompress)(struct acomp_req *req);
void (*dst_free)(struct scatterlist *dst);
unsigned int reqsize;
struct crypto_tfm base;
};
/**
* struct acomp_alg - asynchronous compression algorithm
*
* @compress: Function performs a compress operation
* @decompress: Function performs a de-compress operation
* @dst_free: Frees destination buffer if allocated inside the algorithm
* @init: Initialize the cryptographic transformation object.
* This function is used to initialize the cryptographic
* transformation object. This function is called only once at
* the instantiation time, right after the transformation context
* was allocated. In case the cryptographic hardware has some
* special requirements which need to be handled by software, this
* function shall check for the precise requirement of the
* transformation and put any software fallbacks in place.
* @exit: Deinitialize the cryptographic transformation object. This is a
* counterpart to @init, used to remove various changes set in
* @init.
*
* @reqsize: Context size for (de)compression requests
* @base: Common crypto API algorithm data structure
*/
struct acomp_alg {
int (*compress)(struct acomp_req *req);
int (*decompress)(struct acomp_req *req);
void (*dst_free)(struct scatterlist *dst);
int (*init)(struct crypto_acomp *tfm);
void (*exit)(struct crypto_acomp *tfm);
unsigned int reqsize;
struct crypto_alg base;
};
/**
* DOC: Asynchronous Compression API
*
* The Asynchronous Compression API is used with the algorithms of type
* CRYPTO_ALG_TYPE_ACOMPRESS (listed as type "acomp" in /proc/crypto)
*/
/**
* crypto_alloc_acomp() -- allocate ACOMPRESS tfm handle
* @alg_name: is the cra_name / name or cra_driver_name / driver name of the
* compression algorithm e.g. "deflate"
* @type: specifies the type of the algorithm
* @mask: specifies the mask for the algorithm
*
* Allocate a handle for a compression algorithm. The returned struct
* crypto_acomp is the handle that is required for any subsequent
* API invocation for the compression operations.
*
* Return: allocated handle in case of success; IS_ERR() is true in case
* of an error, PTR_ERR() returns the error code.
*/
struct crypto_acomp *crypto_alloc_acomp(const char *alg_name, u32 type,
u32 mask);
static inline struct crypto_tfm *crypto_acomp_tfm(struct crypto_acomp *tfm)
{
return &tfm->base;
}
static inline struct acomp_alg *__crypto_acomp_alg(struct crypto_alg *alg)
{
return container_of(alg, struct acomp_alg, base);
}
static inline struct crypto_acomp *__crypto_acomp_tfm(struct crypto_tfm *tfm)
{
return container_of(tfm, struct crypto_acomp, base);
}
static inline struct acomp_alg *crypto_acomp_alg(struct crypto_acomp *tfm)
{
return __crypto_acomp_alg(crypto_acomp_tfm(tfm)->__crt_alg);
}
static inline unsigned int crypto_acomp_reqsize(struct crypto_acomp *tfm)
{
return tfm->reqsize;
}
static inline void acomp_request_set_tfm(struct acomp_req *req,
struct crypto_acomp *tfm)
{
req->base.tfm = crypto_acomp_tfm(tfm);
}
static inline struct crypto_acomp *crypto_acomp_reqtfm(struct acomp_req *req)
{
return __crypto_acomp_tfm(req->base.tfm);
}
/**
* crypto_free_acomp() -- free ACOMPRESS tfm handle
*
* @tfm: ACOMPRESS tfm handle allocated with crypto_alloc_acomp()
*/
static inline void crypto_free_acomp(struct crypto_acomp *tfm)
{
crypto_destroy_tfm(tfm, crypto_acomp_tfm(tfm));
}
static inline int crypto_has_acomp(const char *alg_name, u32 type, u32 mask)
{
type &= ~CRYPTO_ALG_TYPE_MASK;
type |= CRYPTO_ALG_TYPE_ACOMPRESS;
mask |= CRYPTO_ALG_TYPE_MASK;
return crypto_has_alg(alg_name, type, mask);
}
/**
* acomp_request_alloc() -- allocates asynchronous (de)compression request
*
* @tfm: ACOMPRESS tfm handle allocated with crypto_alloc_acomp()
*
* Return: allocated handle in case of success or NULL in case of an error
*/
struct acomp_req *acomp_request_alloc(struct crypto_acomp *tfm);
/**
* acomp_request_free() -- zeroize and free asynchronous (de)compression
* request as well as the output buffer if allocated
* inside the algorithm
*
* @req: request to free
*/
void acomp_request_free(struct acomp_req *req);
/**
* acomp_request_set_callback() -- Sets an asynchronous callback
*
* Callback will be called when an asynchronous operation on a given
* request is finished.
*
* @req: request that the callback will be set for
* @flgs: specify for instance if the operation may backlog
* @cmlp: callback which will be called
* @data: private data used by the caller
*/
static inline void acomp_request_set_callback(struct acomp_req *req,
u32 flgs,
crypto_completion_t cmpl,
void *data)
{
req->base.complete = cmpl;
req->base.data = data;
req->base.flags = flgs;
}
/**
* acomp_request_set_params() -- Sets request parameters
*
* Sets parameters required by an acomp operation
*
* @req: asynchronous compress request
* @src: pointer to input buffer scatterlist
* @dst: pointer to output buffer scatterlist. If this is NULL, the
* acomp layer will allocate the output memory
* @slen: size of the input buffer
* @dlen: size of the output buffer. If dst is NULL, this can be used by
* the user to specify the maximum amount of memory to allocate
*/
static inline void acomp_request_set_params(struct acomp_req *req,
struct scatterlist *src,
struct scatterlist *dst,
unsigned int slen,
unsigned int dlen)
{
req->src = src;
req->dst = dst;
req->slen = slen;
req->dlen = dlen;
if (!req->dst)
req->flags |= CRYPTO_ACOMP_ALLOC_OUTPUT;
}
/**
* crypto_acomp_compress() -- Invoke asynchronous compress operation
*
* Function invokes the asynchronous compress operation
*
* @req: asynchronous compress request
*
* Return: zero on success; error code in case of error
*/
static inline int crypto_acomp_compress(struct acomp_req *req)
{
struct crypto_acomp *tfm = crypto_acomp_reqtfm(req);
return tfm->compress(req);
}
/**
* crypto_acomp_decompress() -- Invoke asynchronous decompress operation
*
* Function invokes the asynchronous decompress operation
*
* @req: asynchronous compress request
*
* Return: zero on success; error code in case of error
*/
static inline int crypto_acomp_decompress(struct acomp_req *req)
{
struct crypto_acomp *tfm = crypto_acomp_reqtfm(req);
return tfm->decompress(req);
}
#endif

46
include/crypto/aead.h
View File

@@ -55,14 +55,14 @@
* The scatter list pointing to the input data must contain:
*
* * for RFC4106 ciphers, the concatenation of
* associated authentication data || IV || plaintext or ciphertext. Note, the
* same IV (buffer) is also set with the aead_request_set_crypt call. Note,
* the API call of aead_request_set_ad must provide the length of the AAD and
* the IV. The API call of aead_request_set_crypt only points to the size of
* the input plaintext or ciphertext.
* associated authentication data || IV || plaintext or ciphertext. Note, the
* same IV (buffer) is also set with the aead_request_set_crypt call. Note,
* the API call of aead_request_set_ad must provide the length of the AAD and
* the IV. The API call of aead_request_set_crypt only points to the size of
* the input plaintext or ciphertext.
*
* * for "normal" AEAD ciphers, the concatenation of
* associated authentication data || plaintext or ciphertext.
* associated authentication data || plaintext or ciphertext.
*
* It is important to note that if multiple scatter gather list entries form
* the input data mentioned above, the first entry must not point to a NULL
@@ -452,7 +452,7 @@ static inline void aead_request_free(struct aead_request *req)
* completes
*
* The callback function is registered with the aead_request handle and
* must comply with the following template
* must comply with the following template::
*
* void callback_function(struct crypto_async_request *req, int error)
*/
@@ -483,30 +483,18 @@ static inline void aead_request_set_callback(struct aead_request *req,
* destination is the ciphertext. For a decryption operation, the use is
* reversed - the source is the ciphertext and the destination is the plaintext.
*
* For both src/dst the layout is associated data, plain/cipher text,
* authentication tag.
* The memory structure for cipher operation has the following structure:
*
* The content of the AD in the destination buffer after processing
* will either be untouched, or it will contain a copy of the AD
* from the source buffer. In order to ensure that it always has
* a copy of the AD, the user must copy the AD over either before
* or after processing. Of course this is not relevant if the user
* is doing in-place processing where src == dst.
* - AEAD encryption input: assoc data || plaintext
* - AEAD encryption output: assoc data || cipherntext || auth tag
* - AEAD decryption input: assoc data || ciphertext || auth tag
* - AEAD decryption output: assoc data || plaintext
*
* IMPORTANT NOTE AEAD requires an authentication tag (MAC). For decryption,
* the caller must concatenate the ciphertext followed by the
* authentication tag and provide the entire data stream to the
* decryption operation (i.e. the data length used for the
* initialization of the scatterlist and the data length for the
* decryption operation is identical). For encryption, however,
* the authentication tag is created while encrypting the data.
* The destination buffer must hold sufficient space for the
* ciphertext and the authentication tag while the encryption
* invocation must only point to the plaintext data size. The
* following code snippet illustrates the memory usage
* buffer = kmalloc(ptbuflen + (enc ? authsize : 0));
* sg_init_one(&sg, buffer, ptbuflen + (enc ? authsize : 0));
* aead_request_set_crypt(req, &sg, &sg, ptbuflen, iv);
* Albeit the kernel requires the presence of the AAD buffer, however,
* the kernel does not fill the AAD buffer in the output case. If the
* caller wants to have that data buffer filled, the caller must either
* use an in-place cipher operation (i.e. same memory location for
* input/output memory location).
*/
static inline void aead_request_set_crypt(struct aead_request *req,
struct scatterlist *src,

146
include/crypto/cbc.h Normal file
View File

@@ -0,0 +1,146 @@
/*
* CBC: Cipher Block Chaining mode
*
* Copyright (c) 2016 Herbert Xu <herbert@gondor.apana.org.au>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
*/
#ifndef _CRYPTO_CBC_H
#define _CRYPTO_CBC_H
#include <crypto/internal/skcipher.h>
#include <linux/string.h>
#include <linux/types.h>
static inline int crypto_cbc_encrypt_segment(
struct skcipher_walk *walk, struct crypto_skcipher *tfm,
void (*fn)(struct crypto_skcipher *, const u8 *, u8 *))
{
unsigned int bsize = crypto_skcipher_blocksize(tfm);
unsigned int nbytes = walk->nbytes;
u8 *src = walk->src.virt.addr;
u8 *dst = walk->dst.virt.addr;
u8 *iv = walk->iv;
do {
crypto_xor(iv, src, bsize);
fn(tfm, iv, dst);
memcpy(iv, dst, bsize);
src += bsize;
dst += bsize;
} while ((nbytes -= bsize) >= bsize);
return nbytes;
}
static inline int crypto_cbc_encrypt_inplace(
struct skcipher_walk *walk, struct crypto_skcipher *tfm,
void (*fn)(struct crypto_skcipher *, const u8 *, u8 *))
{
unsigned int bsize = crypto_skcipher_blocksize(tfm);
unsigned int nbytes = walk->nbytes;
u8 *src = walk->src.virt.addr;
u8 *iv = walk->iv;
do {
crypto_xor(src, iv, bsize);
fn(tfm, src, src);
iv = src;
src += bsize;
} while ((nbytes -= bsize) >= bsize);
memcpy(walk->iv, iv, bsize);
return nbytes;
}
static inline int crypto_cbc_encrypt_walk(struct skcipher_request *req,
void (*fn)(struct crypto_skcipher *,
const u8 *, u8 *))
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
struct skcipher_walk walk;
int err;
err = skcipher_walk_virt(&walk, req, false);
while (walk.nbytes) {
if (walk.src.virt.addr == walk.dst.virt.addr)
err = crypto_cbc_encrypt_inplace(&walk, tfm, fn);
else
err = crypto_cbc_encrypt_segment(&walk, tfm, fn);
err = skcipher_walk_done(&walk, err);
}
return err;
}
static inline int crypto_cbc_decrypt_segment(
struct skcipher_walk *walk, struct crypto_skcipher *tfm,
void (*fn)(struct crypto_skcipher *, const u8 *, u8 *))
{
unsigned int bsize = crypto_skcipher_blocksize(tfm);
unsigned int nbytes = walk->nbytes;
u8 *src = walk->src.virt.addr;
u8 *dst = walk->dst.virt.addr;
u8 *iv = walk->iv;
do {
fn(tfm, src, dst);
crypto_xor(dst, iv, bsize);
iv = src;
src += bsize;
dst += bsize;
} while ((nbytes -= bsize) >= bsize);
memcpy(walk->iv, iv, bsize);
return nbytes;
}
static inline int crypto_cbc_decrypt_inplace(
struct skcipher_walk *walk, struct crypto_skcipher *tfm,
void (*fn)(struct crypto_skcipher *, const u8 *, u8 *))
{
unsigned int bsize = crypto_skcipher_blocksize(tfm);
unsigned int nbytes = walk->nbytes;
u8 *src = walk->src.virt.addr;
u8 last_iv[bsize];
/* Start of the last block. */
src += nbytes - (nbytes & (bsize - 1)) - bsize;
memcpy(last_iv, src, bsize);
for (;;) {
fn(tfm, src, src);
if ((nbytes -= bsize) < bsize)
break;
crypto_xor(src, src - bsize, bsize);
src -= bsize;
}
crypto_xor(src, walk->iv, bsize);
memcpy(walk->iv, last_iv, bsize);
return nbytes;
}
static inline int crypto_cbc_decrypt_blocks(
struct skcipher_walk *walk, struct crypto_skcipher *tfm,
void (*fn)(struct crypto_skcipher *, const u8 *, u8 *))
{
if (walk->src.virt.addr == walk->dst.virt.addr)
return crypto_cbc_decrypt_inplace(walk, tfm, fn);
else
return crypto_cbc_decrypt_segment(walk, tfm, fn);
}
#endif /* _CRYPTO_CBC_H */

13
include/crypto/cryptd.h
View File

@@ -12,10 +12,10 @@
#ifndef _CRYPTO_CRYPT_H
#define _CRYPTO_CRYPT_H
#include <linux/crypto.h>
#include <linux/kernel.h>
#include <crypto/aead.h>
#include <crypto/hash.h>
#include <crypto/skcipher.h>
struct cryptd_ablkcipher {
struct crypto_ablkcipher base;
@@ -34,6 +34,17 @@ struct crypto_blkcipher *cryptd_ablkcipher_child(struct cryptd_ablkcipher *tfm);
bool cryptd_ablkcipher_queued(struct cryptd_ablkcipher *tfm);
void cryptd_free_ablkcipher(struct cryptd_ablkcipher *tfm);
struct cryptd_skcipher {
struct crypto_skcipher base;
};
struct cryptd_skcipher *cryptd_alloc_skcipher(const char *alg_name,
u32 type, u32 mask);
struct crypto_skcipher *cryptd_skcipher_child(struct cryptd_skcipher *tfm);
/* Must be called without moving CPUs. */
bool cryptd_skcipher_queued(struct cryptd_skcipher *tfm);
void cryptd_free_skcipher(struct cryptd_skcipher *tfm);
struct cryptd_ahash {
struct crypto_ahash base;
};

58
include/crypto/dh.h
View File

@@ -13,6 +13,27 @@
#ifndef _CRYPTO_DH_
#define _CRYPTO_DH_
/**
* DOC: DH Helper Functions
*
* To use DH with the KPP cipher API, the following data structure and
* functions should be used.
*
* To use DH with KPP, the following functions should be used to operate on
* a DH private key. The packet private key that can be set with
* the KPP API function call of crypto_kpp_set_secret.
*/
/**
* struct dh - define a DH private key
*
* @key: Private DH key
* @p: Diffie-Hellman parameter P
* @g: Diffie-Hellman generator G
* @key_size: Size of the private DH key
* @p_size: Size of DH parameter P
* @g_size: Size of DH generator G
*/
struct dh {
void *key;
void *p;
@@ -22,8 +43,45 @@ struct dh {
unsigned int g_size;
};
/**
* crypto_dh_key_len() - Obtain the size of the private DH key
* @params: private DH key
*
* This function returns the packet DH key size. A caller can use that
* with the provided DH private key reference to obtain the required
* memory size to hold a packet key.
*
* Return: size of the key in bytes
*/
int crypto_dh_key_len(const struct dh *params);
/**
* crypto_dh_encode_key() - encode the private key
* @buf: Buffer allocated by the caller to hold the packet DH
* private key. The buffer should be at least crypto_dh_key_len
* bytes in size.
* @len: Length of the packet private key buffer
* @params: Buffer with the caller-specified private key
*
* The DH implementations operate on a packet representation of the private
* key.
*
* Return: -EINVAL if buffer has insufficient size, 0 on success
*/
int crypto_dh_encode_key(char *buf, unsigned int len, const struct dh *params);
/**
* crypto_dh_decode_key() - decode a private key
* @buf: Buffer holding a packet key that should be decoded
* @len: Lenth of the packet private key buffer
* @params: Buffer allocated by the caller that is filled with the
* unpacket DH private key.
*
* The unpacking obtains the private key by pointing @p to the correct location
* in @buf. Thus, both pointers refer to the same memory.
*
* Return: -EINVAL if buffer has insufficient size, 0 on success
*/
int crypto_dh_decode_key(const char *buf, unsigned int len, struct dh *params);
#endif

2
include/crypto/drbg.h
View File

@@ -124,6 +124,8 @@ struct drbg_state {
struct skcipher_request *ctr_req; /* CTR mode request handle */
__u8 *ctr_null_value_buf; /* CTR mode unaligned buffer */
__u8 *ctr_null_value; /* CTR mode aligned zero buf */
__u8 *outscratchpadbuf; /* CTR mode output scratchpad */
__u8 *outscratchpad; /* CTR mode aligned outbuf */
struct completion ctr_completion; /* CTR mode async handler */
int ctr_async_err; /* CTR mode async error */

58
include/crypto/ecdh.h
View File

@@ -13,18 +13,76 @@
#ifndef _CRYPTO_ECDH_
#define _CRYPTO_ECDH_
/**
* DOC: ECDH Helper Functions
*
* To use ECDH with the KPP cipher API, the following data structure and
* functions should be used.
*
* The ECC curves known to the ECDH implementation are specified in this
* header file.
*
* To use ECDH with KPP, the following functions should be used to operate on
* an ECDH private key. The packet private key that can be set with
* the KPP API function call of crypto_kpp_set_secret.
*/
/* Curves IDs */
#define ECC_CURVE_NIST_P192 0x0001
#define ECC_CURVE_NIST_P256 0x0002
/**
* struct ecdh - define an ECDH private key
*
* @curve_id: ECC curve the key is based on.
* @key: Private ECDH key
* @key_size: Size of the private ECDH key
*/
struct ecdh {
unsigned short curve_id;
char *key;
unsigned short key_size;
};
/**
* crypto_ecdh_key_len() - Obtain the size of the private ECDH key
* @params: private ECDH key
*
* This function returns the packet ECDH key size. A caller can use that
* with the provided ECDH private key reference to obtain the required
* memory size to hold a packet key.
*
* Return: size of the key in bytes
*/
int crypto_ecdh_key_len(const struct ecdh *params);
/**
* crypto_ecdh_encode_key() - encode the private key
* @buf: Buffer allocated by the caller to hold the packet ECDH
* private key. The buffer should be at least crypto_ecdh_key_len
* bytes in size.
* @len: Length of the packet private key buffer
* @p: Buffer with the caller-specified private key
*
* The ECDH implementations operate on a packet representation of the private
* key.
*
* Return: -EINVAL if buffer has insufficient size, 0 on success
*/
int crypto_ecdh_encode_key(char *buf, unsigned int len, const struct ecdh *p);
/**
* crypto_ecdh_decode_key() - decode a private key
* @buf: Buffer holding a packet key that should be decoded
* @len: Lenth of the packet private key buffer
* @p: Buffer allocated by the caller that is filled with the
* unpacket ECDH private key.
*
* The unpacking obtains the private key by pointing @p to the correct location
* in @buf. Thus, both pointers refer to the same memory.
*
* Return: -EINVAL if buffer has insufficient size, 0 on success
*/
int crypto_ecdh_decode_key(const char *buf, unsigned int len, struct ecdh *p);
#endif

6
include/crypto/engine.h
View File

@@ -43,8 +43,7 @@
* @prepare_hash_request: do some prepare if need before handle the current request
* @unprepare_hash_request: undo any work done by prepare_hash_request()
* @hash_one_request: do hash for current request
* @kworker: thread struct for request pump
* @kworker_task: pointer to task for request pump kworker thread
* @kworker: kthread worker struct for request pump
* @pump_requests: work struct for scheduling work to the request pump
* @priv_data: the engine private data
* @cur_req: the current request which is on processing
@@ -78,8 +77,7 @@ struct crypto_engine {
int (*hash_one_request)(struct crypto_engine *engine,
struct ahash_request *req);
struct kthread_worker kworker;
struct task_struct *kworker_task;
struct kthread_worker *kworker;
struct kthread_work pump_requests;
void *priv_data;

15
include/crypto/gf128mul.h
View File

@@ -177,24 +177,23 @@ void gf128mul_4k_bbe(be128 *a, struct gf128mul_4k *t);
static inline void gf128mul_free_4k(struct gf128mul_4k *t)
{
kfree(t);
kzfree(t);
}
/* 64k table optimization, implemented for lle and bbe */
/* 64k table optimization, implemented for bbe */
struct gf128mul_64k {
struct gf128mul_4k *t[16];
};
/* first initialize with the constant factor with which you
* want to multiply and then call gf128_64k_lle with the other
* factor in the first argument, the table in the second and a
* scratch register in the third. Afterwards *a = *r. */
struct gf128mul_64k *gf128mul_init_64k_lle(const be128 *g);
/* First initialize with the constant factor with which you
* want to multiply and then call gf128mul_64k_bbe with the other
* factor in the first argument, and the table in the second.
* Afterwards, the result is stored in *a.
*/
struct gf128mul_64k *gf128mul_init_64k_bbe(const be128 *g);
void gf128mul_free_64k(struct gf128mul_64k *t);
void gf128mul_64k_lle(be128 *a, struct gf128mul_64k *t);
void gf128mul_64k_bbe(be128 *a, struct gf128mul_64k *t);
#endif /* _CRYPTO_GF128MUL_H */

2
include/crypto/hash.h
View File

@@ -605,7 +605,7 @@ static inline struct ahash_request *ahash_request_cast(
* the cipher operation completes.
*
* The callback function is registered with the &ahash_request handle and
* must comply with the following template
* must comply with the following template::
*
* void callback_function(struct crypto_async_request *req, int error)
*/

81
include/crypto/internal/acompress.h Normal file
View File

@@ -0,0 +1,81 @@
/*
* Asynchronous Compression operations
*
* Copyright (c) 2016, Intel Corporation
* Authors: Weigang Li <weigang.li@intel.com>
* Giovanni Cabiddu <giovanni.cabiddu@intel.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
*/
#ifndef _CRYPTO_ACOMP_INT_H
#define _CRYPTO_ACOMP_INT_H
#include <crypto/acompress.h>
/*
* Transform internal helpers.
*/
static inline void *acomp_request_ctx(struct acomp_req *req)
{
return req->__ctx;
}
static inline void *acomp_tfm_ctx(struct crypto_acomp *tfm)
{
return tfm->base.__crt_ctx;
}
static inline void acomp_request_complete(struct acomp_req *req,
int err)
{
req->base.complete(&req->base, err);
}
static inline const char *acomp_alg_name(struct crypto_acomp *tfm)
{
return crypto_acomp_tfm(tfm)->__crt_alg->cra_name;
}
static inline struct acomp_req *__acomp_request_alloc(struct crypto_acomp *tfm)
{
struct acomp_req *req;
req = kzalloc(sizeof(*req) + crypto_acomp_reqsize(tfm), GFP_KERNEL);
if (likely(req))
acomp_request_set_tfm(req, tfm);
return req;
}
static inline void __acomp_request_free(struct acomp_req *req)
{
kzfree(req);
}
/**
* crypto_register_acomp() -- Register asynchronous compression algorithm
*
* Function registers an implementation of an asynchronous
* compression algorithm
*
* @alg: algorithm definition
*
* Return: zero on success; error code in case of error
*/
int crypto_register_acomp(struct acomp_alg *alg);
/**
* crypto_unregister_acomp() -- Unregister asynchronous compression algorithm
*
* Function unregisters an implementation of an asynchronous
* compression algorithm
*
* @alg: algorithm definition
*
* Return: zero on success; error code in case of error
*/
int crypto_unregister_acomp(struct acomp_alg *alg);
#endif

136
include/crypto/internal/scompress.h Normal file
View File

@@ -0,0 +1,136 @@
/*
* Synchronous Compression operations
*
* Copyright 2015 LG Electronics Inc.
* Copyright (c) 2016, Intel Corporation
* Author: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
*/
#ifndef _CRYPTO_SCOMP_INT_H
#define _CRYPTO_SCOMP_INT_H
#include <linux/crypto.h>
#define SCOMP_SCRATCH_SIZE 131072
struct crypto_scomp {
struct crypto_tfm base;
};
/**
* struct scomp_alg - synchronous compression algorithm
*
* @alloc_ctx: Function allocates algorithm specific context
* @free_ctx: Function frees context allocated with alloc_ctx
* @compress: Function performs a compress operation
* @decompress: Function performs a de-compress operation
* @init: Initialize the cryptographic transformation object.
* This function is used to initialize the cryptographic
* transformation object. This function is called only once at
* the instantiation time, right after the transformation context
* was allocated. In case the cryptographic hardware has some
* special requirements which need to be handled by software, this
* function shall check for the precise requirement of the
* transformation and put any software fallbacks in place.
* @exit: Deinitialize the cryptographic transformation object. This is a
* counterpart to @init, used to remove various changes set in
* @init.
* @base: Common crypto API algorithm data structure
*/
struct scomp_alg {
void *(*alloc_ctx)(struct crypto_scomp *tfm);
void (*free_ctx)(struct crypto_scomp *tfm, void *ctx);
int (*compress)(struct crypto_scomp *tfm, const u8 *src,
unsigned int slen, u8 *dst, unsigned int *dlen,
void *ctx);
int (*decompress)(struct crypto_scomp *tfm, const u8 *src,
unsigned int slen, u8 *dst, unsigned int *dlen,
void *ctx);
struct crypto_alg base;
};
static inline struct scomp_alg *__crypto_scomp_alg(struct crypto_alg *alg)
{
return container_of(alg, struct scomp_alg, base);
}
static inline struct crypto_scomp *__crypto_scomp_tfm(struct crypto_tfm *tfm)
{
return container_of(tfm, struct crypto_scomp, base);
}
static inline struct crypto_tfm *crypto_scomp_tfm(struct crypto_scomp *tfm)
{
return &tfm->base;
}
static inline void crypto_free_scomp(struct crypto_scomp *tfm)
{
crypto_destroy_tfm(tfm, crypto_scomp_tfm(tfm));
}
static inline struct scomp_alg *crypto_scomp_alg(struct crypto_scomp *tfm)
{
return __crypto_scomp_alg(crypto_scomp_tfm(tfm)->__crt_alg);
}
static inline void *crypto_scomp_alloc_ctx(struct crypto_scomp *tfm)
{
return crypto_scomp_alg(tfm)->alloc_ctx(tfm);
}
static inline void crypto_scomp_free_ctx(struct crypto_scomp *tfm,
void *ctx)
{
return crypto_scomp_alg(tfm)->free_ctx(tfm, ctx);
}
static inline int crypto_scomp_compress(struct crypto_scomp *tfm,
const u8 *src, unsigned int slen,
u8 *dst, unsigned int *dlen, void *ctx)
{
return crypto_scomp_alg(tfm)->compress(tfm, src, slen, dst, dlen, ctx);
}
static inline int crypto_scomp_decompress(struct crypto_scomp *tfm,
const u8 *src, unsigned int slen,
u8 *dst, unsigned int *dlen,
void *ctx)
{
return crypto_scomp_alg(tfm)->decompress(tfm, src, slen, dst, dlen,
ctx);
}
int crypto_init_scomp_ops_async(struct crypto_tfm *tfm);
struct acomp_req *crypto_acomp_scomp_alloc_ctx(struct acomp_req *req);
void crypto_acomp_scomp_free_ctx(struct acomp_req *req);
/**
* crypto_register_scomp() -- Register synchronous compression algorithm
*
* Function registers an implementation of a synchronous
* compression algorithm
*
* @alg: algorithm definition
*
* Return: zero on success; error code in case of error
*/
int crypto_register_scomp(struct scomp_alg *alg);
/**
* crypto_unregister_scomp() -- Unregister synchronous compression algorithm
*
* Function unregisters an implementation of a synchronous
* compression algorithm
*
* @alg: algorithm definition
*
* Return: zero on success; error code in case of error
*/
int crypto_unregister_scomp(struct scomp_alg *alg);
#endif

17
include/crypto/internal/simd.h Normal file
View File

@@ -0,0 +1,17 @@
/*
* Shared crypto simd helpers
*/
#ifndef _CRYPTO_INTERNAL_SIMD_H
#define _CRYPTO_INTERNAL_SIMD_H
struct simd_skcipher_alg;
struct simd_skcipher_alg *simd_skcipher_create_compat(const char *algname,
const char *drvname,
const char *basename);
struct simd_skcipher_alg *simd_skcipher_create(const char *algname,
const char *basename);
void simd_skcipher_free(struct simd_skcipher_alg *alg);
#endif /* _CRYPTO_INTERNAL_SIMD_H */

65
include/crypto/internal/skcipher.h
View File

@@ -15,8 +15,10 @@
#include <crypto/algapi.h>
#include <crypto/skcipher.h>
#include <linux/list.h>
#include <linux/types.h>
struct aead_request;
struct rtattr;
struct skcipher_instance {
@@ -34,6 +36,40 @@ struct crypto_skcipher_spawn {
struct crypto_spawn base;
};
struct skcipher_walk {
union {
struct {
struct page *page;
unsigned long offset;
} phys;
struct {
u8 *page;
void *addr;
} virt;
} src, dst;
struct scatter_walk in;
unsigned int nbytes;
struct scatter_walk out;
unsigned int total;
struct list_head buffers;
u8 *page;
u8 *buffer;
u8 *oiv;
void *iv;
unsigned int ivsize;
int flags;
unsigned int blocksize;
unsigned int chunksize;
unsigned int alignmask;
};
extern const struct crypto_type crypto_givcipher_type;
static inline struct crypto_instance *skcipher_crypto_instance(
@@ -68,14 +104,6 @@ static inline void crypto_set_skcipher_spawn(
int crypto_grab_skcipher(struct crypto_skcipher_spawn *spawn, const char *name,
u32 type, u32 mask);
static inline int crypto_grab_skcipher2(struct crypto_skcipher_spawn *spawn,
const char *name, u32 type, u32 mask)
{
return crypto_grab_skcipher(spawn, name, type, mask);
}
struct crypto_alg *crypto_lookup_skcipher(const char *name, u32 type, u32 mask);
static inline void crypto_drop_skcipher(struct crypto_skcipher_spawn *spawn)
{
crypto_drop_spawn(&spawn->base);
@@ -99,12 +127,6 @@ static inline struct crypto_skcipher *crypto_spawn_skcipher(
return crypto_spawn_tfm2(&spawn->base);
}
static inline struct crypto_skcipher *crypto_spawn_skcipher2(
struct crypto_skcipher_spawn *spawn)
{
return crypto_spawn_skcipher(spawn);
}
static inline void crypto_skcipher_set_reqsize(
struct crypto_skcipher *skcipher, unsigned int reqsize)
{
@@ -118,6 +140,21 @@ void crypto_unregister_skciphers(struct skcipher_alg *algs, int count);
int skcipher_register_instance(struct crypto_template *tmpl,
struct skcipher_instance *inst);
int skcipher_walk_done(struct skcipher_walk *walk, int err);
int skcipher_walk_virt(struct skcipher_walk *walk,
struct skcipher_request *req,
bool atomic);
void skcipher_walk_atomise(struct skcipher_walk *walk);
int skcipher_walk_async(struct skcipher_walk *walk,
struct skcipher_request *req);
int skcipher_walk_aead(struct skcipher_walk *walk, struct aead_request *req,
bool atomic);
int skcipher_walk_aead_encrypt(struct skcipher_walk *walk,
struct aead_request *req, bool atomic);
int skcipher_walk_aead_decrypt(struct skcipher_walk *walk,
struct aead_request *req, bool atomic);
void skcipher_walk_complete(struct skcipher_walk *walk, int err);
static inline void ablkcipher_request_complete(struct ablkcipher_request *req,
int err)
{

15
include/crypto/kpp.h
View File

@@ -71,7 +71,7 @@ struct crypto_kpp {
*
* @reqsize: Request context size required by algorithm
* implementation
* @base Common crypto API algorithm data structure
* @base: Common crypto API algorithm data structure
*/
struct kpp_alg {
int (*set_secret)(struct crypto_kpp *tfm, void *buffer,
@@ -89,7 +89,7 @@ struct kpp_alg {
};
/**
* DOC: Generic Key-agreement Protocol Primitevs API
* DOC: Generic Key-agreement Protocol Primitives API
*
* The KPP API is used with the algorithm type
* CRYPTO_ALG_TYPE_KPP (listed as type "kpp" in /proc/crypto)
@@ -264,6 +264,12 @@ struct kpp_secret {
* Function invokes the specific kpp operation for a given alg.
*
* @tfm: tfm handle
* @buffer: Buffer holding the packet representation of the private
* key. The structure of the packet key depends on the particular
* KPP implementation. Packing and unpacking helpers are provided
* for ECDH and DH (see the respective header files for those
* implementations).
* @len: Length of the packet private key buffer.
*
* Return: zero on success; error code in case of error
*/
@@ -279,7 +285,10 @@ static inline int crypto_kpp_set_secret(struct crypto_kpp *tfm, void *buffer,
* crypto_kpp_generate_public_key() - Invoke kpp operation
*
* Function invokes the specific kpp operation for generating the public part
* for a given kpp algorithm
* for a given kpp algorithm.
*
* To generate a private key, the caller should use a random number generator.
* The output of the requested length serves as the private key.
*
* @req: kpp key request
*

4
include/crypto/skcipher.h
View File

@@ -516,7 +516,7 @@ static inline void skcipher_request_zero(struct skcipher_request *req)
* skcipher_request_set_callback() - set asynchronous callback function
* @req: request handle
* @flags: specify zero or an ORing of the flags
* CRYPTO_TFM_REQ_MAY_BACKLOG the request queue may back log and
* CRYPTO_TFM_REQ_MAY_BACKLOG the request queue may back log and
* increase the wait queue beyond the initial maximum size;
* CRYPTO_TFM_REQ_MAY_SLEEP the request processing may sleep
* @compl: callback function pointer to be registered with the request handle
@@ -533,7 +533,7 @@ static inline void skcipher_request_zero(struct skcipher_request *req)
* cipher operation completes.
*
* The callback function is registered with the skcipher_request handle and
* must comply with the following template
* must comply with the following template::
*
* void callback_function(struct crypto_async_request *req, int error)
*/

26
include/crypto/xts.h
View File

@@ -2,8 +2,7 @@
#define _CRYPTO_XTS_H
#include <crypto/b128ops.h>
#include <linux/crypto.h>
#include <crypto/algapi.h>
#include <crypto/internal/skcipher.h>
#include <linux/fips.h>
struct scatterlist;
@@ -51,4 +50,27 @@ static inline int xts_check_key(struct crypto_tfm *tfm,
return 0;
}
static inline int xts_verify_key(struct crypto_skcipher *tfm,
const u8 *key, unsigned int keylen)
{
/*
* key consists of keys of equal size concatenated, therefore
* the length must be even.
*/
if (keylen % 2) {
crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
return -EINVAL;
}
/* ensure that the AES and tweak key are not identical */
if ((fips_enabled || crypto_skcipher_get_flags(tfm) &
CRYPTO_TFM_REQ_WEAK_KEY) &&
!crypto_memneq(key, key + (keylen / 2), keylen / 2)) {
crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_WEAK_KEY);
return -EINVAL;
}
return 0;
}
#endif /* _CRYPTO_XTS_H */

2
include/drm/drmP.h
View File

@@ -61,7 +61,7 @@
#include <asm/mman.h>
#include <asm/pgalloc.h>
#include <asm/uaccess.h>
#include <linux/uaccess.h>
#include <uapi/drm/drm.h>
#include <uapi/drm/drm_mode.h>

35
include/drm/drm_connector.h
View File

@@ -194,11 +194,41 @@ int drm_display_info_set_bus_formats(struct drm_display_info *info,
const u32 *formats,
unsigned int num_formats);
/**
* struct drm_tv_connector_state - TV connector related states
* @subconnector: selected subconnector
* @margins: left/right/top/bottom margins
* @mode: TV mode
* @brightness: brightness in percent
* @contrast: contrast in percent
* @flicker_reduction: flicker reduction in percent
* @overscan: overscan in percent
* @saturation: saturation in percent
* @hue: hue in percent
*/
struct drm_tv_connector_state {
enum drm_mode_subconnector subconnector;
struct {
unsigned int left;
unsigned int right;
unsigned int top;
unsigned int bottom;
} margins;
unsigned int mode;
unsigned int brightness;
unsigned int contrast;
unsigned int flicker_reduction;
unsigned int overscan;
unsigned int saturation;
unsigned int hue;
};
/**
* struct drm_connector_state - mutable connector state
* @connector: backpointer to the connector
* @best_encoder: can be used by helpers and drivers to select the encoder
* @state: backpointer to global drm_atomic_state
* @tv: TV connector state
*/
struct drm_connector_state {
struct drm_connector *connector;
@@ -214,6 +244,8 @@ struct drm_connector_state {
struct drm_encoder *best_encoder;
struct drm_atomic_state *state;
struct drm_tv_connector_state tv;
};
/**
@@ -262,6 +294,9 @@ struct drm_connector_funcs {
* connector due to a user request. force can be used by the driver to
* avoid expensive, destructive operations during automated probing.
*
* This callback is optional, if not implemented the connector will be
* considered as always being attached.
*
* FIXME:
*
* Note that this hook is only called by the probe helper. It's not in

4
include/drm/drm_plane.h
View File

@@ -513,7 +513,7 @@ struct drm_plane {
extern __printf(8, 9)
int drm_universal_plane_init(struct drm_device *dev,
struct drm_plane *plane,
unsigned long possible_crtcs,
uint32_t possible_crtcs,
const struct drm_plane_funcs *funcs,
const uint32_t *formats,
unsigned int format_count,
@@ -521,7 +521,7 @@ int drm_universal_plane_init(struct drm_device *dev,
const char *name, ...);
extern int drm_plane_init(struct drm_device *dev,
struct drm_plane *plane,
unsigned long possible_crtcs,
uint32_t possible_crtcs,
const struct drm_plane_funcs *funcs,
const uint32_t *formats, unsigned int format_count,
bool is_primary);

48
include/dt-bindings/clock/hi3516cv300-clock.h Normal file
View File

@@ -0,0 +1,48 @@
/*
* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __DTS_HI3516CV300_CLOCK_H
#define __DTS_HI3516CV300_CLOCK_H
/* hi3516CV300 core CRG */
#define HI3516CV300_APB_CLK 0
#define HI3516CV300_UART0_CLK 1
#define HI3516CV300_UART1_CLK 2
#define HI3516CV300_UART2_CLK 3
#define HI3516CV300_SPI0_CLK 4
#define HI3516CV300_SPI1_CLK 5
#define HI3516CV300_FMC_CLK 6
#define HI3516CV300_MMC0_CLK 7
#define HI3516CV300_MMC1_CLK 8
#define HI3516CV300_MMC2_CLK 9
#define HI3516CV300_MMC3_CLK 10
#define HI3516CV300_ETH_CLK 11
#define HI3516CV300_ETH_MACIF_CLK 12
#define HI3516CV300_DMAC_CLK 13
#define HI3516CV300_PWM_CLK 14
#define HI3516CV300_USB2_BUS_CLK 15
#define HI3516CV300_USB2_OHCI48M_CLK 16
#define HI3516CV300_USB2_OHCI12M_CLK 17
#define HI3516CV300_USB2_OTG_UTMI_CLK 18
#define HI3516CV300_USB2_HST_PHY_CLK 19
#define HI3516CV300_USB2_UTMI0_CLK 20
#define HI3516CV300_USB2_PHY_CLK 21
/* hi3516CV300 sysctrl CRG */
#define HI3516CV300_WDT_CLK 1
#endif /* __DTS_HI3516CV300_CLOCK_H */

66
include/dt-bindings/clock/histb-clock.h Normal file
View File

@@ -0,0 +1,66 @@
/*
* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __DTS_HISTB_CLOCK_H
#define __DTS_HISTB_CLOCK_H
/* clocks provided by core CRG */
#define HISTB_OSC_CLK 0
#define HISTB_APB_CLK 1
#define HISTB_AHB_CLK 2
#define HISTB_UART1_CLK 3
#define HISTB_UART2_CLK 4
#define HISTB_UART3_CLK 5
#define HISTB_I2C0_CLK 6
#define HISTB_I2C1_CLK 7
#define HISTB_I2C2_CLK 8
#define HISTB_I2C3_CLK 9
#define HISTB_I2C4_CLK 10
#define HISTB_I2C5_CLK 11
#define HISTB_SPI0_CLK 12
#define HISTB_SPI1_CLK 13
#define HISTB_SPI2_CLK 14
#define HISTB_SCI_CLK 15
#define HISTB_FMC_CLK 16
#define HISTB_MMC_BIU_CLK 17
#define HISTB_MMC_CIU_CLK 18
#define HISTB_MMC_DRV_CLK 19
#define HISTB_MMC_SAMPLE_CLK 20
#define HISTB_SDIO0_BIU_CLK 21
#define HISTB_SDIO0_CIU_CLK 22
#define HISTB_SDIO0_DRV_CLK 23
#define HISTB_SDIO0_SAMPLE_CLK 24
#define HISTB_PCIE_AUX_CLK 25
#define HISTB_PCIE_PIPE_CLK 26
#define HISTB_PCIE_SYS_CLK 27
#define HISTB_PCIE_BUS_CLK 28
#define HISTB_ETH0_MAC_CLK 29
#define HISTB_ETH0_MACIF_CLK 30
#define HISTB_ETH1_MAC_CLK 31
#define HISTB_ETH1_MACIF_CLK 32
#define HISTB_COMBPHY1_CLK 33
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1
#define HISTB_IR_CLK 2
#define HISTB_TIMER01_CLK 3
#define HISTB_LEDC_CLK 4
#define HISTB_UART0_CLK 5
#define HISTB_LSADC_CLK 6
#endif /* __DTS_HISTB_CLOCK_H */

15
include/dt-bindings/clock/imx6ul-clock.h
View File

@@ -236,6 +236,19 @@
#define IMX6UL_CLK_PLL3_120M 223
#define IMX6UL_CLK_KPP 224
#define IMX6UL_CLK_END 225
/* For i.MX6ULL */
#define IMX6ULL_CLK_ESAI_PRED 225
#define IMX6ULL_CLK_ESAI_PODF 226
#define IMX6ULL_CLK_ESAI_EXTAL 227
#define IMX6ULL_CLK_ESAI_MEM 228
#define IMX6ULL_CLK_ESAI_IPG 229
#define IMX6ULL_CLK_DCP_CLK 230
#define IMX6ULL_CLK_EPDC_PRE_SEL 231
#define IMX6ULL_CLK_EPDC_SEL 232
#define IMX6ULL_CLK_EPDC_PODF 233
#define IMX6ULL_CLK_EPDC_ACLK 234
#define IMX6ULL_CLK_EPDC_PIX 235
#define IMX6ULL_CLK_ESAI_SEL 236
#define IMX6UL_CLK_END 237
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */

30
include/dt-bindings/clock/oxsemi,ox810se.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef DT_CLOCK_OXSEMI_OX810SE_H
#define DT_CLOCK_OXSEMI_OX810SE_H
#define CLK_810_LEON 0
#define CLK_810_DMA_SGDMA 1
#define CLK_810_CIPHER 2
#define CLK_810_SATA 3
#define CLK_810_AUDIO 4
#define CLK_810_USBMPH 5
#define CLK_810_ETHA 6
#define CLK_810_PCIEA 7
#define CLK_810_NAND 8
#endif /* DT_CLOCK_OXSEMI_OX810SE_H */

40
include/dt-bindings/clock/oxsemi,ox820.h Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef DT_CLOCK_OXSEMI_OX820_H
#define DT_CLOCK_OXSEMI_OX820_H
/* PLLs */
#define CLK_820_PLLA 0
#define CLK_820_PLLB 1
/* Gate Clocks */
#define CLK_820_LEON 2
#define CLK_820_DMA_SGDMA 3
#define CLK_820_CIPHER 4
#define CLK_820_SD 5
#define CLK_820_SATA 6
#define CLK_820_AUDIO 7
#define CLK_820_USBMPH 8
#define CLK_820_ETHA 9
#define CLK_820_PCIEA 10
#define CLK_820_NAND 11
#define CLK_820_PCIEB 12
#define CLK_820_ETHB 13
#define CLK_820_REF600 14
#define CLK_820_USBDEV 15
#endif /* DT_CLOCK_OXSEMI_OX820_H */

137
include/dt-bindings/clock/qcom,gcc-msm8994.h Normal file
View File

@@ -0,0 +1,137 @@
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
#define _DT_BINDINGS_CLK_MSM_GCC_8994_H
#define GPLL0_EARLY 0
#define GPLL0 1
#define GPLL4_EARLY 2
#define GPLL4 3
#define UFS_AXI_CLK_SRC 4
#define USB30_MASTER_CLK_SRC 5
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 6
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 7
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 8
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 9
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 10
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 11
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 12
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 13
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 14
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 15
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 16
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 17
#define BLSP1_UART1_APPS_CLK_SRC 18
#define BLSP1_UART2_APPS_CLK_SRC 19
#define BLSP1_UART3_APPS_CLK_SRC 20
#define BLSP1_UART4_APPS_CLK_SRC 21
#define BLSP1_UART5_APPS_CLK_SRC 22
#define BLSP1_UART6_APPS_CLK_SRC 23
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 24
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 25
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 26
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 27
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 28
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 29
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 30
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 31
#define BLSP2_QUP5_I2C_APPS_CLK_SRC 32
#define BLSP2_QUP5_SPI_APPS_CLK_SRC 33
#define BLSP2_QUP6_I2C_APPS_CLK_SRC 34
#define BLSP2_QUP6_SPI_APPS_CLK_SRC 35
#define BLSP2_UART1_APPS_CLK_SRC 36
#define BLSP2_UART2_APPS_CLK_SRC 37
#define BLSP2_UART3_APPS_CLK_SRC 38
#define BLSP2_UART4_APPS_CLK_SRC 39
#define BLSP2_UART5_APPS_CLK_SRC 40
#define BLSP2_UART6_APPS_CLK_SRC 41
#define GP1_CLK_SRC 42
#define GP2_CLK_SRC 43
#define GP3_CLK_SRC 44
#define PCIE_0_AUX_CLK_SRC 45
#define PCIE_0_PIPE_CLK_SRC 46
#define PCIE_1_AUX_CLK_SRC 47
#define PCIE_1_PIPE_CLK_SRC 48
#define PDM2_CLK_SRC 49
#define SDCC1_APPS_CLK_SRC 50
#define SDCC2_APPS_CLK_SRC 51
#define SDCC3_APPS_CLK_SRC 52
#define SDCC4_APPS_CLK_SRC 53
#define TSIF_REF_CLK_SRC 54
#define USB30_MOCK_UTMI_CLK_SRC 55
#define USB3_PHY_AUX_CLK_SRC 56
#define USB_HS_SYSTEM_CLK_SRC 57
#define GCC_BLSP1_AHB_CLK 58
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 59
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 60
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 61
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 62
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 63
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 64
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 65
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 66
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 67
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 68
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 69
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 70
#define GCC_BLSP1_UART1_APPS_CLK 71
#define GCC_BLSP1_UART2_APPS_CLK 72
#define GCC_BLSP1_UART3_APPS_CLK 73
#define GCC_BLSP1_UART4_APPS_CLK 74
#define GCC_BLSP1_UART5_APPS_CLK 75
#define GCC_BLSP1_UART6_APPS_CLK 76
#define GCC_BLSP2_AHB_CLK 77
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 78
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 79
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 80
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 81
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 82
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 83
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 84
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 85
#define GCC_BLSP2_QUP5_I2C_APPS_CLK 86
#define GCC_BLSP2_QUP5_SPI_APPS_CLK 87
#define GCC_BLSP2_QUP6_I2C_APPS_CLK 88
#define GCC_BLSP2_QUP6_SPI_APPS_CLK 89
#define GCC_BLSP2_UART1_APPS_CLK 90
#define GCC_BLSP2_UART2_APPS_CLK 91
#define GCC_BLSP2_UART3_APPS_CLK 92
#define GCC_BLSP2_UART4_APPS_CLK 93
#define GCC_BLSP2_UART5_APPS_CLK 94
#define GCC_BLSP2_UART6_APPS_CLK 95
#define GCC_GP1_CLK 96
#define GCC_GP2_CLK 97
#define GCC_GP3_CLK 98
#define GCC_PCIE_0_AUX_CLK 99
#define GCC_PCIE_0_PIPE_CLK 100
#define GCC_PCIE_1_AUX_CLK 101
#define GCC_PCIE_1_PIPE_CLK 102
#define GCC_PDM2_CLK 103
#define GCC_SDCC1_APPS_CLK 104
#define GCC_SDCC2_APPS_CLK 105
#define GCC_SDCC3_APPS_CLK 106
#define GCC_SDCC4_APPS_CLK 107
#define GCC_SYS_NOC_UFS_AXI_CLK 108
#define GCC_SYS_NOC_USB3_AXI_CLK 109
#define GCC_TSIF_REF_CLK 110
#define GCC_UFS_AXI_CLK 111
#define GCC_UFS_RX_CFG_CLK 112
#define GCC_UFS_TX_CFG_CLK 113
#define GCC_USB30_MASTER_CLK 114
#define GCC_USB30_MOCK_UTMI_CLK 115
#define GCC_USB3_PHY_AUX_CLK 116
#define GCC_USB_HS_SYSTEM_CLK 117
#endif

69
include/dt-bindings/clock/qcom,rpmcc.h Normal file
View File

@@ -0,0 +1,69 @@
/*
* Copyright 2015 Linaro Limited
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
#define _DT_BINDINGS_CLK_MSM_RPMCC_H
/* apq8064 */
#define RPM_PXO_CLK 0
#define RPM_PXO_A_CLK 1
#define RPM_CXO_CLK 2
#define RPM_CXO_A_CLK 3
#define RPM_APPS_FABRIC_CLK 4
#define RPM_APPS_FABRIC_A_CLK 5
#define RPM_CFPB_CLK 6
#define RPM_CFPB_A_CLK 7
#define RPM_QDSS_CLK 8
#define RPM_QDSS_A_CLK 9
#define RPM_DAYTONA_FABRIC_CLK 10
#define RPM_DAYTONA_FABRIC_A_CLK 11
#define RPM_EBI1_CLK 12
#define RPM_EBI1_A_CLK 13
#define RPM_MM_FABRIC_CLK 14
#define RPM_MM_FABRIC_A_CLK 15
#define RPM_MMFPB_CLK 16
#define RPM_MMFPB_A_CLK 17
#define RPM_SYS_FABRIC_CLK 18
#define RPM_SYS_FABRIC_A_CLK 19
#define RPM_SFPB_CLK 20
#define RPM_SFPB_A_CLK 21
/* msm8916 */
#define RPM_SMD_XO_CLK_SRC 0
#define RPM_SMD_XO_A_CLK_SRC 1
#define RPM_SMD_PCNOC_CLK 2
#define RPM_SMD_PCNOC_A_CLK 3
#define RPM_SMD_SNOC_CLK 4
#define RPM_SMD_SNOC_A_CLK 5
#define RPM_SMD_BIMC_CLK 6
#define RPM_SMD_BIMC_A_CLK 7
#define RPM_SMD_QDSS_CLK 8
#define RPM_SMD_QDSS_A_CLK 9
#define RPM_SMD_BB_CLK1 10
#define RPM_SMD_BB_CLK1_A 11
#define RPM_SMD_BB_CLK2 12
#define RPM_SMD_BB_CLK2_A 13
#define RPM_SMD_RF_CLK1 14
#define RPM_SMD_RF_CLK1_A 15
#define RPM_SMD_RF_CLK2 16
#define RPM_SMD_RF_CLK2_A 17
#define RPM_SMD_BB_CLK1_PIN 18
#define RPM_SMD_BB_CLK1_A_PIN 19
#define RPM_SMD_BB_CLK2_PIN 20
#define RPM_SMD_BB_CLK2_A_PIN 21
#define RPM_SMD_RF_CLK1_PIN 22
#define RPM_SMD_RF_CLK1_A_PIN 23
#define RPM_SMD_RF_CLK2_PIN 24
#define RPM_SMD_RF_CLK2_A_PIN 25
#endif

7
include/dt-bindings/clock/r7s72100-clock.h
View File

@@ -28,6 +28,9 @@
/* MSTP7 */
#define R7S72100_CLK_ETHER 4
/* MSTP8 */
#define R7S72100_CLK_MMCIF 4
/* MSTP9 */
#define R7S72100_CLK_I2C0 7
#define R7S72100_CLK_I2C1 6
@@ -41,4 +44,8 @@
#define R7S72100_CLK_SPI3 4
#define R7S72100_CLK_SPI4 3
/* MSTP12 */
#define R7S72100_CLK_SDHI0 3
#define R7S72100_CLK_SDHI1 2
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */

43
include/dt-bindings/clock/r8a7743-cpg-mssr.h Normal file
View File

@@ -0,0 +1,43 @@
/*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7743 CPG Core Clocks */
#define R8A7743_CLK_Z 0
#define R8A7743_CLK_ZG 1
#define R8A7743_CLK_ZTR 2
#define R8A7743_CLK_ZTRD2 3
#define R8A7743_CLK_ZT 4
#define R8A7743_CLK_ZX 5
#define R8A7743_CLK_ZS 6
#define R8A7743_CLK_HP 7
#define R8A7743_CLK_B 9
#define R8A7743_CLK_LB 10
#define R8A7743_CLK_P 11
#define R8A7743_CLK_CL 12
#define R8A7743_CLK_M2 13
#define R8A7743_CLK_ZB3 15
#define R8A7743_CLK_ZB3D2 16
#define R8A7743_CLK_DDR 17
#define R8A7743_CLK_SDH 18
#define R8A7743_CLK_SD0 19
#define R8A7743_CLK_SD2 20
#define R8A7743_CLK_SD3 21
#define R8A7743_CLK_MMC0 22
#define R8A7743_CLK_MP 23
#define R8A7743_CLK_QSPI 26
#define R8A7743_CLK_CP 27
#define R8A7743_CLK_RCAN 28
#define R8A7743_CLK_R 29
#define R8A7743_CLK_OSC 30
#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */

44
include/dt-bindings/clock/r8a7745-cpg-mssr.h Normal file
View File

@@ -0,0 +1,44 @@
/*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7745 CPG Core Clocks */
#define R8A7745_CLK_Z2 0
#define R8A7745_CLK_ZG 1
#define R8A7745_CLK_ZTR 2
#define R8A7745_CLK_ZTRD2 3
#define R8A7745_CLK_ZT 4
#define R8A7745_CLK_ZX 5
#define R8A7745_CLK_ZS 6
#define R8A7745_CLK_HP 7
#define R8A7745_CLK_B 9
#define R8A7745_CLK_LB 10
#define R8A7745_CLK_P 11
#define R8A7745_CLK_CL 12
#define R8A7745_CLK_CP 13
#define R8A7745_CLK_M2 14
#define R8A7745_CLK_ZB3 16
#define R8A7745_CLK_ZB3D2 17
#define R8A7745_CLK_DDR 18
#define R8A7745_CLK_SDH 19
#define R8A7745_CLK_SD0 20
#define R8A7745_CLK_SD2 21
#define R8A7745_CLK_SD3 22
#define R8A7745_CLK_MMC0 23
#define R8A7745_CLK_MP 24
#define R8A7745_CLK_QSPI 25
#define R8A7745_CLK_CPEX 26
#define R8A7745_CLK_RCAN 27
#define R8A7745_CLK_R 28
#define R8A7745_CLK_OSC 29
#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */

3
include/dt-bindings/clock/r8a7794-clock.h
View File

@@ -20,8 +20,7 @@
#define R8A7794_CLK_QSPI 5
#define R8A7794_CLK_SDH 6
#define R8A7794_CLK_SD0 7
#define R8A7794_CLK_Z 8
#define R8A7794_CLK_RCAN 9
#define R8A7794_CLK_RCAN 8
/* MSTP0 */
#define R8A7794_CLK_MSIOF0 0

269
include/dt-bindings/clock/rk1108-cru.h Normal file
View File

@@ -0,0 +1,269 @@
/*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Shawn Lin <shawn.lin@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
/* pll id */
#define PLL_APLL 0
#define PLL_DPLL 1
#define PLL_GPLL 2
#define ARMCLK 3
/* sclk gates (special clocks) */
#define SCLK_SPI0 65
#define SCLK_NANDC 67
#define SCLK_SDMMC 68
#define SCLK_SDIO 69
#define SCLK_EMMC 71
#define SCLK_UART0 72
#define SCLK_UART1 73
#define SCLK_UART2 74
#define SCLK_I2S0 75
#define SCLK_I2S1 76
#define SCLK_I2S2 77
#define SCLK_TIMER0 78
#define SCLK_TIMER1 79
#define SCLK_SFC 80
#define SCLK_SDMMC_DRV 81
#define SCLK_SDIO_DRV 82
#define SCLK_EMMC_DRV 83
#define SCLK_SDMMC_SAMPLE 84
#define SCLK_SDIO_SAMPLE 85
#define SCLK_EMMC_SAMPLE 86
/* aclk gates */
#define ACLK_DMAC 192
#define ACLK_PRE 193
#define ACLK_CORE 194
#define ACLK_ENMCORE 195
/* pclk gates */
#define PCLK_GPIO1 256
#define PCLK_GPIO2 257
#define PCLK_GPIO3 258
#define PCLK_GRF 259
#define PCLK_I2C1 260
#define PCLK_I2C2 261
#define PCLK_I2C3 262
#define PCLK_SPI 263
#define PCLK_SFC 264
#define PCLK_UART0 265
#define PCLK_UART1 266
#define PCLK_UART2 267
#define PCLK_TSADC 268
#define PCLK_PWM 269
#define PCLK_TIMER 270
#define PCLK_PERI 271
/* hclk gates */
#define HCLK_I2S0_8CH 320
#define HCLK_I2S1_8CH 321
#define HCLK_I2S2_2CH 322
#define HCLK_NANDC 323
#define HCLK_SDMMC 324
#define HCLK_SDIO 325
#define HCLK_EMMC 326
#define HCLK_PERI 327
#define HCLK_SFC 328
#define CLK_NR_CLKS (HCLK_SFC + 1)
/* reset id */
#define SRST_CORE_PO_AD 0
#define SRST_CORE_AD 1
#define SRST_L2_AD 2
#define SRST_CPU_NIU_AD 3
#define SRST_CORE_PO 4
#define SRST_CORE 5
#define SRST_L2 6
#define SRST_CORE_DBG 8
#define PRST_DBG 9
#define RST_DAP 10
#define PRST_DBG_NIU 11
#define ARST_STRC_SYS_AD 15
#define SRST_DDRPHY_CLKDIV 16
#define SRST_DDRPHY 17
#define PRST_DDRPHY 18
#define PRST_HDMIPHY 19
#define PRST_VDACPHY 20
#define PRST_VADCPHY 21
#define PRST_MIPI_CSI_PHY 22
#define PRST_MIPI_DSI_PHY 23
#define PRST_ACODEC 24
#define ARST_BUS_NIU 25
#define PRST_TOP_NIU 26
#define ARST_INTMEM 27
#define HRST_ROM 28
#define ARST_DMAC 29
#define SRST_MSCH_NIU 30
#define PRST_MSCH_NIU 31
#define PRST_DDRUPCTL 32
#define NRST_DDRUPCTL 33
#define PRST_DDRMON 34
#define HRST_I2S0_8CH 35
#define MRST_I2S0_8CH 36
#define HRST_I2S1_2CH 37
#define MRST_IS21_2CH 38
#define HRST_I2S2_2CH 39
#define MRST_I2S2_2CH 40
#define HRST_CRYPTO 41
#define SRST_CRYPTO 42
#define PRST_SPI 43
#define SRST_SPI 44
#define PRST_UART0 45
#define PRST_UART1 46
#define PRST_UART2 47
#define SRST_UART0 48
#define SRST_UART1 49
#define SRST_UART2 50
#define PRST_I2C1 51
#define PRST_I2C2 52
#define PRST_I2C3 53
#define SRST_I2C1 54
#define SRST_I2C2 55
#define SRST_I2C3 56
#define PRST_PWM1 58
#define SRST_PWM1 60
#define PRST_WDT 61
#define PRST_GPIO1 62
#define PRST_GPIO2 63
#define PRST_GPIO3 64
#define PRST_GRF 65
#define PRST_EFUSE 66
#define PRST_EFUSE512 67
#define PRST_TIMER0 68
#define SRST_TIMER0 69
#define SRST_TIMER1 70
#define PRST_TSADC 71
#define SRST_TSADC 72
#define PRST_SARADC 73
#define SRST_SARADC 74
#define HRST_SYSBUS 75
#define PRST_USBGRF 76
#define ARST_PERIPH_NIU 80
#define HRST_PERIPH_NIU 81
#define PRST_PERIPH_NIU 82
#define HRST_PERIPH 83
#define HRST_SDMMC 84
#define HRST_SDIO 85
#define HRST_EMMC 86
#define HRST_NANDC 87
#define NRST_NANDC 88
#define HRST_SFC 89
#define SRST_SFC 90
#define ARST_GMAC 91
#define HRST_OTG 92
#define SRST_OTG 93
#define SRST_OTG_ADP 94
#define HRST_HOST0 95
#define HRST_HOST0_AUX 96
#define HRST_HOST0_ARB 97
#define SRST_HOST0_EHCIPHY 98
#define SRST_HOST0_UTMI 99
#define SRST_USBPOR 100
#define SRST_UTMI0 101
#define SRST_UTMI1 102
#define ARST_VIO0_NIU 102
#define ARST_VIO1_NIU 103
#define HRST_VIO_NIU 104
#define PRST_VIO_NIU 105
#define ARST_VOP 106
#define HRST_VOP 107
#define DRST_VOP 108
#define ARST_IEP 109
#define HRST_IEP 110
#define ARST_RGA 111
#define HRST_RGA 112
#define SRST_RGA 113
#define PRST_CVBS 114
#define PRST_HDMI 115
#define SRST_HDMI 116
#define PRST_MIPI_DSI 117
#define ARST_ISP_NIU 118
#define HRST_ISP_NIU 119
#define HRST_ISP 120
#define SRST_ISP 121
#define ARST_VIP0 122
#define HRST_VIP0 123
#define PRST_VIP0 124
#define ARST_VIP1 125
#define HRST_VIP1 126
#define PRST_VIP1 127
#define ARST_VIP2 128
#define HRST_VIP2 129
#define PRST_VIP2 120
#define ARST_VIP3 121
#define HRST_VIP3 122
#define PRST_VIP4 123
#define PRST_CIF1TO4 124
#define SRST_CVBS_CLK 125
#define HRST_CVBS 126
#define ARST_VPU_NIU 140
#define HRST_VPU_NIU 141
#define ARST_VPU 142
#define HRST_VPU 143
#define ARST_RKVDEC_NIU 144
#define HRST_RKVDEC_NIU 145
#define ARST_RKVDEC 146
#define HRST_RKVDEC 147
#define SRST_RKVDEC_CABAC 148
#define SRST_RKVDEC_CORE 149
#define ARST_RKVENC_NIU 150
#define HRST_RKVENC_NIU 151
#define ARST_RKVENC 152
#define HRST_RKVENC 153
#define SRST_RKVENC_CORE 154
#define SRST_DSP_CORE 156
#define SRST_DSP_SYS 157
#define SRST_DSP_GLOBAL 158
#define SRST_DSP_OECM 159
#define PRST_DSP_IOP_NIU 160
#define ARST_DSP_EPP_NIU 161
#define ARST_DSP_EDP_NIU 162
#define PRST_DSP_DBG_NIU 163
#define PRST_DSP_CFG_NIU 164
#define PRST_DSP_GRF 165
#define PRST_DSP_MAILBOX 166
#define PRST_DSP_INTC 167
#define PRST_DSP_PFM_MON 169
#define SRST_DSP_PFM_MON 170
#define ARST_DSP_EDAP_NIU 171
#define SRST_PMU 172
#define SRST_PMU_I2C0 173
#define PRST_PMU_I2C0 174
#define PRST_PMU_GPIO0 175
#define PRST_PMU_INTMEM 176
#define PRST_PMU_PWM0 177
#define SRST_PMU_PWM0 178
#define PRST_PMU_GRF 179
#define SRST_PMU_NIU 180
#define SRST_PMU_PVTM 181
#define ARST_DSP_EDP_PERF 184
#define ARST_DSP_EPP_PERF 185
#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H */

8
include/dt-bindings/clock/rk3188-cru-common.h
View File

@@ -72,6 +72,8 @@
#define ACLK_IPP 200
#define ACLK_RGA 201
#define ACLK_CIF0 202
#define ACLK_CPU 203
#define ACLK_PERI 204
/* pclk gates */
#define PCLK_GRF 320
@@ -104,6 +106,8 @@
#define PCLK_EFUSE 347
#define PCLK_TZPC 348
#define PCLK_TSADC 349
#define PCLK_CPU 350
#define PCLK_PERI 351
/* hclk gates */
#define HCLK_SDMMC 448
@@ -126,8 +130,10 @@
#define HCLK_IPP 465
#define HCLK_RGA 466
#define HCLK_NANDC0 467
#define HCLK_CPU 468
#define HCLK_PERI 469
#define CLK_NR_CLKS (HCLK_NANDC0 + 1)
#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_MCORE 2

16
include/dt-bindings/clock/stih415-clks.h
View File

@@ -1,16 +0,0 @@
/*
* This header provides constants clk index STMicroelectronics
* STiH415 SoC.
*/
#ifndef _CLK_STIH415
#define _CLK_STIH415
/* CLOCKGEN A0 */
#define CLK_ICN_REG 0
#define CLK_ETH1_PHY 4
/* CLOCKGEN A1 */
#define CLK_ICN_IF_2 0
#define CLK_GMAC0_PHY 3
#endif

134
include/dt-bindings/clock/sun50i-a64-ccu.h Normal file
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@@ -0,0 +1,134 @@
/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
#define CLK_BUS_MIPI_DSI 28
#define CLK_BUS_CE 29
#define CLK_BUS_DMA 30
#define CLK_BUS_MMC0 31
#define CLK_BUS_MMC1 32
#define CLK_BUS_MMC2 33
#define CLK_BUS_NAND 34
#define CLK_BUS_DRAM 35
#define CLK_BUS_EMAC 36
#define CLK_BUS_TS 37
#define CLK_BUS_HSTIMER 38
#define CLK_BUS_SPI0 39
#define CLK_BUS_SPI1 40
#define CLK_BUS_OTG 41
#define CLK_BUS_EHCI0 42
#define CLK_BUS_EHCI1 43
#define CLK_BUS_OHCI0 44
#define CLK_BUS_OHCI1 45
#define CLK_BUS_VE 46
#define CLK_BUS_TCON0 47
#define CLK_BUS_TCON1 48
#define CLK_BUS_DEINTERLACE 49
#define CLK_BUS_CSI 50
#define CLK_BUS_HDMI 51
#define CLK_BUS_DE 52
#define CLK_BUS_GPU 53
#define CLK_BUS_MSGBOX 54
#define CLK_BUS_SPINLOCK 55
#define CLK_BUS_CODEC 56
#define CLK_BUS_SPDIF 57
#define CLK_BUS_PIO 58
#define CLK_BUS_THS 59
#define CLK_BUS_I2S0 60
#define CLK_BUS_I2S1 61
#define CLK_BUS_I2S2 62
#define CLK_BUS_I2C0 63
#define CLK_BUS_I2C1 64
#define CLK_BUS_I2C2 65
#define CLK_BUS_SCR 66
#define CLK_BUS_UART0 67
#define CLK_BUS_UART1 68
#define CLK_BUS_UART2 69
#define CLK_BUS_UART3 70
#define CLK_BUS_UART4 71
#define CLK_BUS_DBG 72
#define CLK_THS 73
#define CLK_NAND 74
#define CLK_MMC0 75
#define CLK_MMC1 76
#define CLK_MMC2 77
#define CLK_TS 78
#define CLK_CE 79
#define CLK_SPI0 80
#define CLK_SPI1 81
#define CLK_I2S0 82
#define CLK_I2S1 83
#define CLK_I2S2 84
#define CLK_SPDIF 85
#define CLK_USB_PHY0 86
#define CLK_USB_PHY1 87
#define CLK_USB_HSIC 88
#define CLK_USB_HSIC_12M 89
#define CLK_USB_OHCI0 91
#define CLK_USB_OHCI1 93
#define CLK_DRAM_VE 95
#define CLK_DRAM_CSI 96
#define CLK_DRAM_DEINTERLACE 97
#define CLK_DRAM_TS 98
#define CLK_DE 99
#define CLK_TCON0 100
#define CLK_TCON1 101
#define CLK_DEINTERLACE 102
#define CLK_CSI_MISC 103
#define CLK_CSI_SCLK 104
#define CLK_CSI_MCLK 105
#define CLK_VE 106
#define CLK_AC_DIG 107
#define CLK_AC_DIG_4X 108
#define CLK_AVS 109
#define CLK_HDMI 110
#define CLK_HDMI_DDC 111
#define CLK_DSI_DPHY 113
#define CLK_GPU 114
#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */

940
include/dt-bindings/clock/tegra186-clock.h Normal file
View File

@@ -0,0 +1,940 @@
/** @file */
#ifndef _MACH_T186_CLK_T186_H
#define _MACH_T186_CLK_T186_H
/**
* @defgroup clock_ids Clock Identifiers
* @{
* @defgroup extern_input external input clocks
* @{
* @def TEGRA186_CLK_OSC
* @def TEGRA186_CLK_CLK_32K
* @def TEGRA186_CLK_DTV_INPUT
* @def TEGRA186_CLK_SOR0_PAD_CLKOUT
* @def TEGRA186_CLK_SOR1_PAD_CLKOUT
* @def TEGRA186_CLK_I2S1_SYNC_INPUT
* @def TEGRA186_CLK_I2S2_SYNC_INPUT
* @def TEGRA186_CLK_I2S3_SYNC_INPUT
* @def TEGRA186_CLK_I2S4_SYNC_INPUT
* @def TEGRA186_CLK_I2S5_SYNC_INPUT
* @def TEGRA186_CLK_I2S6_SYNC_INPUT
* @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
* @}
*
* @defgroup extern_output external output clocks
* @{
* @def TEGRA186_CLK_EXTPERIPH1
* @def TEGRA186_CLK_EXTPERIPH2
* @def TEGRA186_CLK_EXTPERIPH3
* @def TEGRA186_CLK_EXTPERIPH4
* @}
*
* @defgroup display_clks display related clocks
* @{
* @def TEGRA186_CLK_CEC
* @def TEGRA186_CLK_DSIC
* @def TEGRA186_CLK_DSIC_LP
* @def TEGRA186_CLK_DSID
* @def TEGRA186_CLK_DSID_LP
* @def TEGRA186_CLK_DPAUX1
* @def TEGRA186_CLK_DPAUX
* @def TEGRA186_CLK_HDA2HDMICODEC
* @def TEGRA186_CLK_NVDISPLAY_DISP
* @def TEGRA186_CLK_NVDISPLAY_DSC
* @def TEGRA186_CLK_NVDISPLAY_P0
* @def TEGRA186_CLK_NVDISPLAY_P1
* @def TEGRA186_CLK_NVDISPLAY_P2
* @def TEGRA186_CLK_NVDISPLAYHUB
* @def TEGRA186_CLK_SOR_SAFE
* @def TEGRA186_CLK_SOR0
* @def TEGRA186_CLK_SOR0_OUT
* @def TEGRA186_CLK_SOR1
* @def TEGRA186_CLK_SOR1_OUT
* @def TEGRA186_CLK_DSI
* @def TEGRA186_CLK_MIPI_CAL
* @def TEGRA186_CLK_DSIA_LP
* @def TEGRA186_CLK_DSIB
* @def TEGRA186_CLK_DSIB_LP
* @}
*
* @defgroup camera_clks camera related clocks
* @{
* @def TEGRA186_CLK_NVCSI
* @def TEGRA186_CLK_NVCSILP
* @def TEGRA186_CLK_VI
* @}
*
* @defgroup audio_clks audio related clocks
* @{
* @def TEGRA186_CLK_ACLK
* @def TEGRA186_CLK_ADSP
* @def TEGRA186_CLK_ADSPNEON
* @def TEGRA186_CLK_AHUB
* @def TEGRA186_CLK_APE
* @def TEGRA186_CLK_APB2APE
* @def TEGRA186_CLK_AUD_MCLK
* @def TEGRA186_CLK_DMIC1
* @def TEGRA186_CLK_DMIC2
* @def TEGRA186_CLK_DMIC3
* @def TEGRA186_CLK_DMIC4
* @def TEGRA186_CLK_DSPK1
* @def TEGRA186_CLK_DSPK2
* @def TEGRA186_CLK_HDA
* @def TEGRA186_CLK_HDA2CODEC_2X
* @def TEGRA186_CLK_I2S1
* @def TEGRA186_CLK_I2S2
* @def TEGRA186_CLK_I2S3
* @def TEGRA186_CLK_I2S4
* @def TEGRA186_CLK_I2S5
* @def TEGRA186_CLK_I2S6
* @def TEGRA186_CLK_MAUD
* @def TEGRA186_CLK_PLL_A_OUT0
* @def TEGRA186_CLK_SPDIF_DOUBLER
* @def TEGRA186_CLK_SPDIF_IN
* @def TEGRA186_CLK_SPDIF_OUT
* @def TEGRA186_CLK_SYNC_DMIC1
* @def TEGRA186_CLK_SYNC_DMIC2
* @def TEGRA186_CLK_SYNC_DMIC3
* @def TEGRA186_CLK_SYNC_DMIC4
* @def TEGRA186_CLK_SYNC_DMIC5
* @def TEGRA186_CLK_SYNC_DSPK1
* @def TEGRA186_CLK_SYNC_DSPK2
* @def TEGRA186_CLK_SYNC_I2S1
* @def TEGRA186_CLK_SYNC_I2S2
* @def TEGRA186_CLK_SYNC_I2S3
* @def TEGRA186_CLK_SYNC_I2S4
* @def TEGRA186_CLK_SYNC_I2S5
* @def TEGRA186_CLK_SYNC_I2S6
* @def TEGRA186_CLK_SYNC_SPDIF
* @}
*
* @defgroup uart_clks UART clocks
* @{
* @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
* @def TEGRA186_CLK_UARTA
* @def TEGRA186_CLK_UARTB
* @def TEGRA186_CLK_UARTC
* @def TEGRA186_CLK_UARTD
* @def TEGRA186_CLK_UARTE
* @def TEGRA186_CLK_UARTF
* @def TEGRA186_CLK_UARTG
* @def TEGRA186_CLK_UART_FST_MIPI_CAL
* @}
*
* @defgroup i2c_clks I2C clocks
* @{
* @def TEGRA186_CLK_AON_I2C_SLOW
* @def TEGRA186_CLK_I2C1
* @def TEGRA186_CLK_I2C2
* @def TEGRA186_CLK_I2C3
* @def TEGRA186_CLK_I2C4
* @def TEGRA186_CLK_I2C5
* @def TEGRA186_CLK_I2C6
* @def TEGRA186_CLK_I2C8
* @def TEGRA186_CLK_I2C9
* @def TEGRA186_CLK_I2C1
* @def TEGRA186_CLK_I2C12
* @def TEGRA186_CLK_I2C13
* @def TEGRA186_CLK_I2C14
* @def TEGRA186_CLK_I2C_SLOW
* @def TEGRA186_CLK_VI_I2C
* @}
*
* @defgroup spi_clks SPI clocks
* @{
* @def TEGRA186_CLK_SPI1
* @def TEGRA186_CLK_SPI2
* @def TEGRA186_CLK_SPI3
* @def TEGRA186_CLK_SPI4
* @}
*
* @defgroup storage storage related clocks
* @{
* @def TEGRA186_CLK_SATA
* @def TEGRA186_CLK_SATA_OOB
* @def TEGRA186_CLK_SATA_IOBIST
* @def TEGRA186_CLK_SDMMC_LEGACY_TM
* @def TEGRA186_CLK_SDMMC1
* @def TEGRA186_CLK_SDMMC2
* @def TEGRA186_CLK_SDMMC3
* @def TEGRA186_CLK_SDMMC4
* @def TEGRA186_CLK_QSPI
* @def TEGRA186_CLK_QSPI_OUT
* @def TEGRA186_CLK_UFSDEV_REF
* @def TEGRA186_CLK_UFSHC
* @}
*
* @defgroup pwm_clks PWM clocks
* @{
* @def TEGRA186_CLK_PWM1
* @def TEGRA186_CLK_PWM2
* @def TEGRA186_CLK_PWM3
* @def TEGRA186_CLK_PWM4
* @def TEGRA186_CLK_PWM5
* @def TEGRA186_CLK_PWM6
* @def TEGRA186_CLK_PWM7
* @def TEGRA186_CLK_PWM8
* @}
*
* @defgroup plls PLLs and related clocks
* @{
* @def TEGRA186_CLK_PLLREFE_OUT_GATED
* @def TEGRA186_CLK_PLLREFE_OUT1
* @def TEGRA186_CLK_PLLD_OUT1
* @def TEGRA186_CLK_PLLP_OUT0
* @def TEGRA186_CLK_PLLP_OUT5
* @def TEGRA186_CLK_PLLA
* @def TEGRA186_CLK_PLLE_PWRSEQ
* @def TEGRA186_CLK_PLLA_OUT1
* @def TEGRA186_CLK_PLLREFE_REF
* @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
* @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
* @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
* @def TEGRA186_CLK_PLLREFE_PEX
* @def TEGRA186_CLK_PLLREFE_IDDQ
* @def TEGRA186_CLK_PLLC_OUT_AON
* @def TEGRA186_CLK_PLLC_OUT_ISP
* @def TEGRA186_CLK_PLLC_OUT_VE
* @def TEGRA186_CLK_PLLC4_OUT
* @def TEGRA186_CLK_PLLREFE_OUT
* @def TEGRA186_CLK_PLLREFE_PLL_REF
* @def TEGRA186_CLK_PLLE
* @def TEGRA186_CLK_PLLC
* @def TEGRA186_CLK_PLLP
* @def TEGRA186_CLK_PLLD
* @def TEGRA186_CLK_PLLD2
* @def TEGRA186_CLK_PLLREFE_VCO
* @def TEGRA186_CLK_PLLC2
* @def TEGRA186_CLK_PLLC3
* @def TEGRA186_CLK_PLLDP
* @def TEGRA186_CLK_PLLC4_VCO
* @def TEGRA186_CLK_PLLA1
* @def TEGRA186_CLK_PLLNVCSI
* @def TEGRA186_CLK_PLLDISPHUB
* @def TEGRA186_CLK_PLLD3
* @def TEGRA186_CLK_PLLBPMPCAM
* @def TEGRA186_CLK_PLLAON
* @def TEGRA186_CLK_PLLU
* @def TEGRA186_CLK_PLLC4_VCO_DIV2
* @def TEGRA186_CLK_PLL_REF
* @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
* @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
* @def TEGRA186_CLK_PLL_U_48M
* @def TEGRA186_CLK_PLL_U_480M
* @def TEGRA186_CLK_PLLC4_OUT0
* @def TEGRA186_CLK_PLLC4_OUT1
* @def TEGRA186_CLK_PLLC4_OUT2
* @def TEGRA186_CLK_PLLC4_OUT_MUX
* @def TEGRA186_CLK_DFLLDISP_DIV
* @def TEGRA186_CLK_PLLDISPHUB_DIV
* @def TEGRA186_CLK_PLLP_DIV8
* @}
*
* @defgroup nafll_clks NAFLL clock sources
* @{
* @def TEGRA186_CLK_NAFLL_AXI_CBB
* @def TEGRA186_CLK_NAFLL_BCPU
* @def TEGRA186_CLK_NAFLL_BPMP
* @def TEGRA186_CLK_NAFLL_DISP
* @def TEGRA186_CLK_NAFLL_GPU
* @def TEGRA186_CLK_NAFLL_ISP
* @def TEGRA186_CLK_NAFLL_MCPU
* @def TEGRA186_CLK_NAFLL_NVDEC
* @def TEGRA186_CLK_NAFLL_NVENC
* @def TEGRA186_CLK_NAFLL_NVJPG
* @def TEGRA186_CLK_NAFLL_SCE
* @def TEGRA186_CLK_NAFLL_SE
* @def TEGRA186_CLK_NAFLL_TSEC
* @def TEGRA186_CLK_NAFLL_TSECB
* @def TEGRA186_CLK_NAFLL_VI
* @def TEGRA186_CLK_NAFLL_VIC
* @}
*
* @defgroup mphy MPHY related clocks
* @{
* @def TEGRA186_CLK_MPHY_L0_RX_SYMB
* @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
* @def TEGRA186_CLK_MPHY_L0_TX_SYMB
* @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
* @def TEGRA186_CLK_MPHY_L0_RX_ANA
* @def TEGRA186_CLK_MPHY_L1_RX_ANA
* @def TEGRA186_CLK_MPHY_IOBIST
* @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
* @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
* @}
*
* @defgroup eavb EAVB related clocks
* @{
* @def TEGRA186_CLK_EQOS_AXI
* @def TEGRA186_CLK_EQOS_PTP_REF
* @def TEGRA186_CLK_EQOS_RX
* @def TEGRA186_CLK_EQOS_RX_INPUT
* @def TEGRA186_CLK_EQOS_TX
* @}
*
* @defgroup usb USB related clocks
* @{
* @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
* @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
* @def TEGRA186_CLK_HSIC_TRK
* @def TEGRA186_CLK_USB2_TRK
* @def TEGRA186_CLK_USB2_HSIC_TRK
* @def TEGRA186_CLK_XUSB_CORE_SS
* @def TEGRA186_CLK_XUSB_CORE_DEV
* @def TEGRA186_CLK_XUSB_FALCON
* @def TEGRA186_CLK_XUSB_FS
* @def TEGRA186_CLK_XUSB
* @def TEGRA186_CLK_XUSB_DEV
* @def TEGRA186_CLK_XUSB_HOST
* @def TEGRA186_CLK_XUSB_SS
* @}
*
* @defgroup bigblock compute block related clocks
* @{
* @def TEGRA186_CLK_GPCCLK
* @def TEGRA186_CLK_GPC2CLK
* @def TEGRA186_CLK_GPU
* @def TEGRA186_CLK_HOST1X
* @def TEGRA186_CLK_ISP
* @def TEGRA186_CLK_NVDEC
* @def TEGRA186_CLK_NVENC
* @def TEGRA186_CLK_NVJPG
* @def TEGRA186_CLK_SE
* @def TEGRA186_CLK_TSEC
* @def TEGRA186_CLK_TSECB
* @def TEGRA186_CLK_VIC
* @}
*
* @defgroup can CAN bus related clocks
* @{
* @def TEGRA186_CLK_CAN1
* @def TEGRA186_CLK_CAN1_HOST
* @def TEGRA186_CLK_CAN2
* @def TEGRA186_CLK_CAN2_HOST
* @}
*
* @defgroup system basic system clocks
* @{
* @def TEGRA186_CLK_ACTMON
* @def TEGRA186_CLK_AON_APB
* @def TEGRA186_CLK_AON_CPU_NIC
* @def TEGRA186_CLK_AON_NIC
* @def TEGRA186_CLK_AXI_CBB
* @def TEGRA186_CLK_BPMP_APB
* @def TEGRA186_CLK_BPMP_CPU_NIC
* @def TEGRA186_CLK_BPMP_NIC_RATE
* @def TEGRA186_CLK_CLK_M
* @def TEGRA186_CLK_EMC
* @def TEGRA186_CLK_MSS_ENCRYPT
* @def TEGRA186_CLK_SCE_APB
* @def TEGRA186_CLK_SCE_CPU_NIC
* @def TEGRA186_CLK_SCE_NIC
* @def TEGRA186_CLK_TSC
* @}
*
* @defgroup pcie_clks PCIe related clocks
* @{
* @def TEGRA186_CLK_AFI
* @def TEGRA186_CLK_PCIE
* @def TEGRA186_CLK_PCIE2_IOBIST
* @def TEGRA186_CLK_PCIERX0
* @def TEGRA186_CLK_PCIERX1
* @def TEGRA186_CLK_PCIERX2
* @def TEGRA186_CLK_PCIERX3
* @def TEGRA186_CLK_PCIERX4
* @}
*/
/** @brief output of gate CLK_ENB_FUSE */
#define TEGRA186_CLK_FUSE 0
/**
* @brief It's not what you think
* @details output of gate CLK_ENB_GPU. This output connects to the GPU
* pwrclk. @warning: This is almost certainly not the clock you think
* it is. If you're looking for the clock of the graphics engine, see
* TEGRA186_GPCCLK
*/
#define TEGRA186_CLK_GPU 1
/** @brief output of gate CLK_ENB_PCIE */
#define TEGRA186_CLK_PCIE 3
/** @brief output of the divider IPFS_CLK_DIVISOR */
#define TEGRA186_CLK_AFI 4
/** @brief output of gate CLK_ENB_PCIE2_IOBIST */
#define TEGRA186_CLK_PCIE2_IOBIST 5
/** @brief output of gate CLK_ENB_PCIERX0*/
#define TEGRA186_CLK_PCIERX0 6
/** @brief output of gate CLK_ENB_PCIERX1*/
#define TEGRA186_CLK_PCIERX1 7
/** @brief output of gate CLK_ENB_PCIERX2*/
#define TEGRA186_CLK_PCIERX2 8
/** @brief output of gate CLK_ENB_PCIERX3*/
#define TEGRA186_CLK_PCIERX3 9
/** @brief output of gate CLK_ENB_PCIERX4*/
#define TEGRA186_CLK_PCIERX4 10
/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
#define TEGRA186_CLK_PLLC_OUT_ISP 11
/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
#define TEGRA186_CLK_PLLC_OUT_VE 12
/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
#define TEGRA186_CLK_PLLC_OUT_AON 13
/** @brief output of gate CLK_ENB_SOR_SAFE */
#define TEGRA186_CLK_SOR_SAFE 39
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
#define TEGRA186_CLK_I2S2 42
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
#define TEGRA186_CLK_I2S3 43
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
#define TEGRA186_CLK_SPDIF_IN 44
/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
#define TEGRA186_CLK_SPDIF_DOUBLER 45
/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
#define TEGRA186_CLK_SPI3 46
/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
#define TEGRA186_CLK_I2C1 47
/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
#define TEGRA186_CLK_I2C5 48
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
#define TEGRA186_CLK_SPI1 49
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
#define TEGRA186_CLK_ISP 50
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
#define TEGRA186_CLK_VI 51
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
#define TEGRA186_CLK_SDMMC1 52
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
#define TEGRA186_CLK_SDMMC2 53
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
#define TEGRA186_CLK_SDMMC4 54
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
#define TEGRA186_CLK_UARTA 55
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
#define TEGRA186_CLK_UARTB 56
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
#define TEGRA186_CLK_HOST1X 57
/**
* @brief controls the EMC clock frequency.
* @details Doing a clk_set_rate on this clock will select the
* appropriate clock source, program the source rate and execute a
* specific sequence to switch to the new clock source for both memory
* controllers. This can be used to control the balance between memory
* throughput and memory controller power.
*/
#define TEGRA186_CLK_EMC 58
/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
#define TEGRA186_CLK_EXTPERIPH4 73
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
#define TEGRA186_CLK_SPI4 74
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
#define TEGRA186_CLK_I2C3 75
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
#define TEGRA186_CLK_SDMMC3 76
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
#define TEGRA186_CLK_UARTD 77
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
#define TEGRA186_CLK_I2S1 79
/** output of gate CLK_ENB_DTV */
#define TEGRA186_CLK_DTV 80
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
#define TEGRA186_CLK_TSEC 81
/** @brief output of gate CLK_ENB_DP2 */
#define TEGRA186_CLK_DP2 82
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
#define TEGRA186_CLK_I2S4 84
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
#define TEGRA186_CLK_I2S5 85
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
#define TEGRA186_CLK_I2C4 86
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
#define TEGRA186_CLK_AHUB 87
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
#define TEGRA186_CLK_HDA2CODEC_2X 88
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
#define TEGRA186_CLK_EXTPERIPH1 89
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
#define TEGRA186_CLK_EXTPERIPH2 90
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
#define TEGRA186_CLK_EXTPERIPH3 91
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
#define TEGRA186_CLK_I2C_SLOW 92
/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
#define TEGRA186_CLK_SOR1 93
/** @brief output of gate CLK_ENB_CEC */
#define TEGRA186_CLK_CEC 94
/** @brief output of gate CLK_ENB_DPAUX1 */
#define TEGRA186_CLK_DPAUX1 95
/** @brief output of gate CLK_ENB_DPAUX */
#define TEGRA186_CLK_DPAUX 96
/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
#define TEGRA186_CLK_SOR0 97
/** @brief output of gate CLK_ENB_HDA2HDMICODEC */
#define TEGRA186_CLK_HDA2HDMICODEC 98
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
#define TEGRA186_CLK_SATA 99
/** @brief output of gate CLK_ENB_SATA_OOB */
#define TEGRA186_CLK_SATA_OOB 100
/** @brief output of gate CLK_ENB_SATA_IOBIST */
#define TEGRA186_CLK_SATA_IOBIST 101
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
#define TEGRA186_CLK_HDA 102
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
#define TEGRA186_CLK_SE 103
/** @brief output of gate CLK_ENB_APB2APE */
#define TEGRA186_CLK_APB2APE 104
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
#define TEGRA186_CLK_APE 105
/** @brief output of gate CLK_ENB_IQC1 */
#define TEGRA186_CLK_IQC1 106
/** @brief output of gate CLK_ENB_IQC2 */
#define TEGRA186_CLK_IQC2 107
/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
#define TEGRA186_CLK_PLLREFE_OUT 108
/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
#define TEGRA186_CLK_PLLREFE_PLL_REF 109
/** @brief output of gate CLK_ENB_PLLC4_OUT */
#define TEGRA186_CLK_PLLC4_OUT 110
/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB 111
/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_DEV 112
/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_HOST 113
/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_SS 114
/** @brief output of gate CLK_ENB_DSI */
#define TEGRA186_CLK_DSI 115
/** @brief output of gate CLK_ENB_MIPI_CAL */
#define TEGRA186_CLK_MIPI_CAL 116
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
#define TEGRA186_CLK_DSIA_LP 117
/** @brief output of gate CLK_ENB_DSIB */
#define TEGRA186_CLK_DSIB 118
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
#define TEGRA186_CLK_DSIB_LP 119
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
#define TEGRA186_CLK_DMIC1 122
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
#define TEGRA186_CLK_DMIC2 123
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
#define TEGRA186_CLK_AUD_MCLK 124
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
#define TEGRA186_CLK_I2C6 125
/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
#define TEGRA186_CLK_UART_FST_MIPI_CAL 126
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
#define TEGRA186_CLK_VIC 127
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
#define TEGRA186_CLK_SDMMC_LEGACY_TM 128
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
#define TEGRA186_CLK_NVDEC 129
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
#define TEGRA186_CLK_NVJPG 130
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
#define TEGRA186_CLK_NVENC 131
/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
#define TEGRA186_CLK_QSPI 132
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
#define TEGRA186_CLK_VI_I2C 133
/** @brief output of gate CLK_ENB_HSIC_TRK */
#define TEGRA186_CLK_HSIC_TRK 134
/** @brief output of gate CLK_ENB_USB2_TRK */
#define TEGRA186_CLK_USB2_TRK 135
/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
#define TEGRA186_CLK_MAUD 136
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
#define TEGRA186_CLK_TSECB 137
/** @brief output of gate CLK_ENB_ADSP */
#define TEGRA186_CLK_ADSP 138
/** @brief output of gate CLK_ENB_ADSPNEON */
#define TEGRA186_CLK_ADSPNEON 139
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
#define TEGRA186_CLK_MPHY_L0_RX_ANA 144
/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
#define TEGRA186_CLK_MPHY_L1_RX_ANA 145
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
#define TEGRA186_CLK_MPHY_IOBIST 146
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
#define TEGRA186_CLK_AXI_CBB 149
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
#define TEGRA186_CLK_DMIC3 150
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
#define TEGRA186_CLK_DMIC4 151
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
#define TEGRA186_CLK_DSPK1 152
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
#define TEGRA186_CLK_DSPK2 153
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
#define TEGRA186_CLK_I2S6 154
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
#define TEGRA186_CLK_NVDISPLAY_P0 155
/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
#define TEGRA186_CLK_NVDISPLAY_DISP 156
/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
#define TEGRA186_CLK_NVDISPLAY_DSC 157
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
#define TEGRA186_CLK_NVDISPLAYHUB 158
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
#define TEGRA186_CLK_NVDISPLAY_P1 159
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
#define TEGRA186_CLK_NVDISPLAY_P2 160
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
#define TEGRA186_CLK_TACH 166
/** @brief output of gate CLK_ENB_EQOS */
#define TEGRA186_CLK_EQOS_AXI 167
/** @brief output of gate CLK_ENB_EQOS_RX */
#define TEGRA186_CLK_EQOS_RX 168
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
#define TEGRA186_CLK_UFSHC 178
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
#define TEGRA186_CLK_UFSDEV_REF 179
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
#define TEGRA186_CLK_NVCSI 180
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
#define TEGRA186_CLK_NVCSILP 181
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
#define TEGRA186_CLK_I2C7 182
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
#define TEGRA186_CLK_I2C9 183
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
#define TEGRA186_CLK_I2C12 184
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
#define TEGRA186_CLK_I2C13 185
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
#define TEGRA186_CLK_I2C14 186
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
#define TEGRA186_CLK_PWM1 187
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
#define TEGRA186_CLK_PWM2 188
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
#define TEGRA186_CLK_PWM3 189
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
#define TEGRA186_CLK_PWM5 190
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
#define TEGRA186_CLK_PWM6 191
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
#define TEGRA186_CLK_PWM7 192
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
#define TEGRA186_CLK_PWM8 193
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
#define TEGRA186_CLK_UARTE 194
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
#define TEGRA186_CLK_UARTF 195
/** @deprecated */
#define TEGRA186_CLK_DBGAPB 196
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
#define TEGRA186_CLK_BPMP_CPU_NIC 197
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
#define TEGRA186_CLK_BPMP_APB 199
/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
#define TEGRA186_CLK_ACTMON 201
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
#define TEGRA186_CLK_AON_CPU_NIC 208
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
#define TEGRA186_CLK_CAN1 210
/** @brief output of gate CLK_ENB_CAN1_HOST */
#define TEGRA186_CLK_CAN1_HOST 211
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
#define TEGRA186_CLK_CAN2 212
/** @brief output of gate CLK_ENB_CAN2_HOST */
#define TEGRA186_CLK_CAN2_HOST 213
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
#define TEGRA186_CLK_AON_APB 214
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
#define TEGRA186_CLK_UARTC 215
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
#define TEGRA186_CLK_UARTG 216
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
#define TEGRA186_CLK_I2C2 218
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
#define TEGRA186_CLK_I2C8 219
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
#define TEGRA186_CLK_I2C10 220
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
#define TEGRA186_CLK_AON_I2C_SLOW 221
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
#define TEGRA186_CLK_SPI2 222
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
#define TEGRA186_CLK_DMIC5 223
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
#define TEGRA186_CLK_AON_TOUCH 224
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
#define TEGRA186_CLK_PWM4 225
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
#define TEGRA186_CLK_TSC 226
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
#define TEGRA186_CLK_MSS_ENCRYPT 227
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
#define TEGRA186_CLK_SCE_CPU_NIC 228
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
#define TEGRA186_CLK_SCE_APB 230
/** @brief output of gate CLK_ENB_DSIC */
#define TEGRA186_CLK_DSIC 231
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
#define TEGRA186_CLK_DSIC_LP 232
/** @brief output of gate CLK_ENB_DSID */
#define TEGRA186_CLK_DSID 233
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
#define TEGRA186_CLK_DSID_LP 234
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
#define TEGRA186_CLK_SPDIF_OUT 238
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
#define TEGRA186_CLK_EQOS_PTP_REF 239
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
#define TEGRA186_CLK_EQOS_TX 240
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
#define TEGRA186_CLK_USB2_HSIC_TRK 241
/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_CORE_SS 242
/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_CORE_DEV 243
/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_FALCON 244
/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
#define TEGRA186_CLK_XUSB_FS 245
/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
#define TEGRA186_CLK_PLL_A_OUT0 246
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
#define TEGRA186_CLK_SYNC_I2S1 247
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
#define TEGRA186_CLK_SYNC_I2S2 248
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
#define TEGRA186_CLK_SYNC_I2S3 249
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
#define TEGRA186_CLK_SYNC_I2S4 250
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
#define TEGRA186_CLK_SYNC_I2S5 251
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
#define TEGRA186_CLK_SYNC_I2S6 252
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
#define TEGRA186_CLK_SYNC_DSPK1 253
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
#define TEGRA186_CLK_SYNC_DSPK2 254
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
#define TEGRA186_CLK_SYNC_DMIC1 255
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
#define TEGRA186_CLK_SYNC_DMIC2 256
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
#define TEGRA186_CLK_SYNC_DMIC3 257
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
#define TEGRA186_CLK_SYNC_DMIC4 259
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
#define TEGRA186_CLK_SYNC_SPDIF 260
/** @brief output of gate CLK_ENB_PLLREFE_OUT */
#define TEGRA186_CLK_PLLREFE_OUT_GATED 261
/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
* * VCO/pdiv defined by this clock object
* * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
*/
#define TEGRA186_CLK_PLLREFE_OUT1 262
#define TEGRA186_CLK_PLLD_OUT1 267
/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
#define TEGRA186_CLK_PLLP_OUT0 269
/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
#define TEGRA186_CLK_PLLP_OUT5 270
/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
#define TEGRA186_CLK_PLLA 271
/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
#define TEGRA186_CLK_ACLK 273
/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
#define TEGRA186_CLK_PLL_U_48M 274
/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
#define TEGRA186_CLK_PLL_U_480M 275
/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
#define TEGRA186_CLK_PLLC4_OUT0 276
/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
#define TEGRA186_CLK_PLLC4_OUT1 277
/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
#define TEGRA186_CLK_PLLC4_OUT2 278
/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
#define TEGRA186_CLK_PLLC4_OUT_MUX 279
/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
#define TEGRA186_CLK_DFLLDISP_DIV 284
/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
#define TEGRA186_CLK_PLLDISPHUB_DIV 285
/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
#define TEGRA186_CLK_PLLP_DIV8 286
/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
#define TEGRA186_CLK_BPMP_NIC 287
/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
#define TEGRA186_CLK_PLL_A_OUT1 288
/** @deprecated */
#define TEGRA186_CLK_GPC2CLK 289
/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
#define TEGRA186_CLK_KFUSE 293
/**
* @brief controls the PLLE hardware sequencer.
* @details This clock only has enable and disable methods. When the
* PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
* hw based on the control signals from the PCIe, SATA and XUSB
* clocks. When the PLLE hw sequencer is disabled, the state of PLLE
* is controlled by sw using clk_enable/clk_disable on
* TEGRA186_CLK_PLLE.
*/
#define TEGRA186_CLK_PLLE_PWRSEQ 294
/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
#define TEGRA186_CLK_PLLREFE_REF 295
/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
#define TEGRA186_CLK_SOR0_OUT 296
/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
#define TEGRA186_CLK_SOR1_OUT 297
/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
/** @brief controls the UPHY_PLL0 hardware sqeuencer */
#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
/** @brief controls the UPHY_PLL1 hardware sqeuencer */
#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
#define TEGRA186_CLK_PLLREFE_PEX 307
/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
#define TEGRA186_CLK_PLLREFE_IDDQ 308
/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
#define TEGRA186_CLK_QSPI_OUT 309
/**
* @brief GPC2CLK-div-2
* @details fixed /2 divider. Output frequency is
* TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
* frequency at which the GPU graphics engine runs. */
#define TEGRA186_CLK_GPCCLK 310
/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
#define TEGRA186_CLK_AON_NIC 450
/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
#define TEGRA186_CLK_SCE_NIC 451
/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
#define TEGRA186_CLK_PLLE 512
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
#define TEGRA186_CLK_PLLC 513
/** Fixed 408MHz PLL for use by peripheral clocks */
#define TEGRA186_CLK_PLLP 516
/** @deprecated */
#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
#define TEGRA186_CLK_PLLD 518
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
#define TEGRA186_CLK_PLLD2 519
/**
* @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
* @details Note that this clock only controls the VCO output, before
* the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
* information.
*/
#define TEGRA186_CLK_PLLREFE_VCO 520
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
#define TEGRA186_CLK_PLLC2 521
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
#define TEGRA186_CLK_PLLC3 522
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
#define TEGRA186_CLK_PLLDP 523
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
#define TEGRA186_CLK_PLLC4_VCO 524
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
#define TEGRA186_CLK_PLLA1 525
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
#define TEGRA186_CLK_PLLNVCSI 526
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
#define TEGRA186_CLK_PLLDISPHUB 527
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
#define TEGRA186_CLK_PLLD3 528
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
#define TEGRA186_CLK_PLLBPMPCAM 531
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
#define TEGRA186_CLK_PLLAON 532
/** Fixed frequency 960MHz PLL for USB and EAVB */
#define TEGRA186_CLK_PLLU 533
/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
#define TEGRA186_CLK_PLLC4_VCO_DIV2 535
/** @brief NAFLL clock source for AXI_CBB */
#define TEGRA186_CLK_NAFLL_AXI_CBB 564
/** @brief NAFLL clock source for BPMP */
#define TEGRA186_CLK_NAFLL_BPMP 565
/** @brief NAFLL clock source for ISP */
#define TEGRA186_CLK_NAFLL_ISP 566
/** @brief NAFLL clock source for NVDEC */
#define TEGRA186_CLK_NAFLL_NVDEC 567
/** @brief NAFLL clock source for NVENC */
#define TEGRA186_CLK_NAFLL_NVENC 568
/** @brief NAFLL clock source for NVJPG */
#define TEGRA186_CLK_NAFLL_NVJPG 569
/** @brief NAFLL clock source for SCE */
#define TEGRA186_CLK_NAFLL_SCE 570
/** @brief NAFLL clock source for SE */
#define TEGRA186_CLK_NAFLL_SE 571
/** @brief NAFLL clock source for TSEC */
#define TEGRA186_CLK_NAFLL_TSEC 572
/** @brief NAFLL clock source for TSECB */
#define TEGRA186_CLK_NAFLL_TSECB 573
/** @brief NAFLL clock source for VI */
#define TEGRA186_CLK_NAFLL_VI 574
/** @brief NAFLL clock source for VIC */
#define TEGRA186_CLK_NAFLL_VIC 575
/** @brief NAFLL clock source for DISP */
#define TEGRA186_CLK_NAFLL_DISP 576
/** @brief NAFLL clock source for GPU */
#define TEGRA186_CLK_NAFLL_GPU 577
/** @brief NAFLL clock source for M-CPU cluster */
#define TEGRA186_CLK_NAFLL_MCPU 578
/** @brief NAFLL clock source for B-CPU cluster */
#define TEGRA186_CLK_NAFLL_BCPU 579
/** @brief input from Tegra's CLK_32K_IN pad */
#define TEGRA186_CLK_CLK_32K 608
/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
#define TEGRA186_CLK_CLK_M 609
/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
#define TEGRA186_CLK_PLL_REF 610
/** @brief input from Tegra's XTAL_IN */
#define TEGRA186_CLK_OSC 612
/** @brief clock recovered from EAVB input */
#define TEGRA186_CLK_EQOS_RX_INPUT 613
/** @brief clock recovered from DTV input */
#define TEGRA186_CLK_DTV_INPUT 614
/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
/** @brief clock recovered from I2S1 input */
#define TEGRA186_CLK_I2S1_SYNC_INPUT 617
/** @brief clock recovered from I2S2 input */
#define TEGRA186_CLK_I2S2_SYNC_INPUT 618
/** @brief clock recovered from I2S3 input */
#define TEGRA186_CLK_I2S3_SYNC_INPUT 619
/** @brief clock recovered from I2S4 input */
#define TEGRA186_CLK_I2S4_SYNC_INPUT 620
/** @brief clock recovered from I2S5 input */
#define TEGRA186_CLK_I2S5_SYNC_INPUT 621
/** @brief clock recovered from I2S6 input */
#define TEGRA186_CLK_I2S6_SYNC_INPUT 622
/** @brief clock recovered from SPDIFIN input */
#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
/**
* @brief subject to change
* @details maximum clock identifier value plus one.
*/
#define TEGRA186_CLK_CLK_MAX 624
/** @} */
#endif

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include/dt-bindings/gpio/meson-gxl-gpio.h Normal file
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/*
* GPIO definitions for Amlogic Meson GXL SoCs
*
* Copyright (C) 2016 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H
#define _DT_BINDINGS_MESON_GXL_GPIO_H
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define GPIOZ_11 11
#define GPIOZ_12 12
#define GPIOZ_13 13
#define GPIOZ_14 14
#define GPIOZ_15 15
#define GPIOH_0 16
#define GPIOH_1 17
#define GPIOH_2 18
#define GPIOH_3 19
#define GPIOH_4 20
#define GPIOH_5 21
#define GPIOH_6 22
#define GPIOH_7 23
#define GPIOH_8 24
#define GPIOH_9 25
#define BOOT_0 26
#define BOOT_1 27
#define BOOT_2 28
#define BOOT_3 29
#define BOOT_4 30
#define BOOT_5 31
#define BOOT_6 32
#define BOOT_7 33
#define BOOT_8 34
#define BOOT_9 35
#define BOOT_10 36
#define BOOT_11 37
#define BOOT_12 38
#define BOOT_13 39
#define BOOT_14 40
#define BOOT_15 41
#define CARD_0 42
#define CARD_1 43
#define CARD_2 44
#define CARD_3 45
#define CARD_4 46
#define CARD_5 47
#define CARD_6 48
#define GPIODV_0 49
#define GPIODV_1 50
#define GPIODV_2 51
#define GPIODV_3 52
#define GPIODV_4 53
#define GPIODV_5 54
#define GPIODV_6 55
#define GPIODV_7 56
#define GPIODV_8 57
#define GPIODV_9 58
#define GPIODV_10 59
#define GPIODV_11 60
#define GPIODV_12 61
#define GPIODV_13 62
#define GPIODV_14 63
#define GPIODV_15 64
#define GPIODV_16 65
#define GPIODV_17 66
#define GPIODV_18 67
#define GPIODV_19 68
#define GPIODV_20 69
#define GPIODV_21 70
#define GPIODV_22 71
#define GPIODV_23 72
#define GPIODV_24 73
#define GPIODV_25 74
#define GPIODV_26 75
#define GPIODV_27 76
#define GPIODV_28 77
#define GPIODV_29 78
#define GPIOX_0 79
#define GPIOX_1 80
#define GPIOX_2 81
#define GPIOX_3 82
#define GPIOX_4 83
#define GPIOX_5 84
#define GPIOX_6 85
#define GPIOX_7 86
#define GPIOX_8 87
#define GPIOX_9 88
#define GPIOX_10 89
#define GPIOX_11 90
#define GPIOX_12 91
#define GPIOX_13 92
#define GPIOX_14 93
#define GPIOX_15 94
#define GPIOX_16 95
#define GPIOX_17 96
#define GPIOX_18 97
#define GPIOCLK_0 98
#define GPIOCLK_1 99
#define GPIO_TEST_N 100
#endif

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include/dt-bindings/mailbox/tegra186-hsp.h Normal file
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@@ -0,0 +1,24 @@
/*
* This header provides constants for binding nvidia,tegra186-hsp.
*/
#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
/*
* These define the type of mailbox that is to be used (doorbell, shared
* mailbox, shared semaphore or arbitrated semaphore).
*/
#define TEGRA_HSP_MBOX_TYPE_DB 0x0
#define TEGRA_HSP_MBOX_TYPE_SM 0x1
#define TEGRA_HSP_MBOX_TYPE_SS 0x2
#define TEGRA_HSP_MBOX_TYPE_AS 0x3
/*
* These defines represent the bit associated with the given master ID in the
* doorbell registers.
*/
#define TEGRA_HSP_DB_MASTER_CCPLEX 17
#define TEGRA_HSP_DB_MASTER_BPMP 19
#endif

22
include/linux/platform_data/drv260x-pdata.h → include/dt-bindings/mfd/tps65217.h
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@@ -1,9 +1,7 @@
/*
* Platform data for DRV260X haptics driver family
* This header provides macros for TI TPS65217 DT bindings.
*
* Author: Dan Murphy <dmurphy@ti.com>
*
* Copyright: (C) 2014 Texas Instruments, Inc.
* Copyright (C) 2016 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -13,16 +11,16 @@
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _LINUX_DRV260X_PDATA_H
#define _LINUX_DRV260X_PDATA_H
#ifndef __DT_BINDINGS_TPS65217_H__
#define __DT_BINDINGS_TPS65217_H__
struct drv260x_platform_data {
u32 library_selection;
u32 mode;
u32 vib_rated_voltage;
u32 vib_overdrive_voltage;
};
#define TPS65217_IRQ_USB 0
#define TPS65217_IRQ_AC 1
#define TPS65217_IRQ_PB 2
#endif

21
include/dt-bindings/net/mscc-phy-vsc8531.h
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@@ -1,21 +0,0 @@
/*
* Device Tree constants for Microsemi VSC8531 PHY
*
* Author: Nagaraju Lakkaraju
*
* License: Dual MIT/GPL
* Copyright (c) 2016 Microsemi Corporation
*/
#ifndef _DT_BINDINGS_MSCC_VSC8531_H
#define _DT_BINDINGS_MSCC_VSC8531_H
/* MAC interface Edge rate control VDDMAC in milli Volts */
#define MSCC_VDDMAC_3300 3300
#define MSCC_VDDMAC_2500 2500
#define MSCC_VDDMAC_1800 1800
#define MSCC_VDDMAC_1500 1500
#define MSCC_VDDMAC_MAX 4
#define MSCC_SLOWDOWN_MAX 8
#endif

2
include/dt-bindings/pinctrl/at91.h
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@@ -15,6 +15,8 @@
#define AT91_PINCTRL_DEGLITCH (1 << 2)
#define AT91_PINCTRL_PULL_DOWN (1 << 3)
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
#define AT91_PINCTRL_OUTPUT (1 << 7)
#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)

5
include/dt-bindings/pinctrl/bcm2835.h
View File

@@ -24,4 +24,9 @@
#define BCM2835_FSEL_ALT2 6
#define BCM2835_FSEL_ALT3 7
/* brcm,pull property */
#define BCM2835_PUD_OFF 0
#define BCM2835_PUD_DOWN 1
#define BCM2835_PUD_UP 2
#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */

4
include/dt-bindings/pinctrl/qcom,pmic-gpio.h
View File

@@ -89,6 +89,10 @@
#define PMA8084_GPIO_S4 2
#define PMA8084_GPIO_L6 3
#define PM8994_GPIO_VPH 0
#define PM8994_GPIO_S4 2
#define PM8994_GPIO_L12 3
/* To be used with "function" */
#define PMIC_GPIO_FUNC_NORMAL "normal"
#define PMIC_GPIO_FUNC_PAIRED "paired"

6
include/dt-bindings/pinctrl/qcom,pmic-mpp.h
View File

@@ -65,6 +65,12 @@
#define PMA8084_MPP_S4 2
#define PMA8084_MPP_L6 3
#define PM8994_MPP_VPH 0
/* Only supported for MPP_05-MPP_08 */
#define PM8994_MPP_L19 1
#define PM8994_MPP_S4 2
#define PM8994_MPP_L12 3
/*
* Analog Input - Set the source for analog input.
* To be used with "qcom,amux-route" property

33
include/dt-bindings/pinctrl/rockchip.h
View File

@@ -25,6 +25,39 @@
#define RK_GPIO4 4
#define RK_GPIO6 6
#define RK_PA0 0
#define RK_PA1 1
#define RK_PA2 2
#define RK_PA3 3
#define RK_PA4 4
#define RK_PA5 5
#define RK_PA6 6
#define RK_PA7 7
#define RK_PB0 8
#define RK_PB1 9
#define RK_PB2 10
#define RK_PB3 11
#define RK_PB4 12
#define RK_PB5 13
#define RK_PB6 14
#define RK_PB7 15
#define RK_PC0 16
#define RK_PC1 17
#define RK_PC2 18
#define RK_PC3 19
#define RK_PC4 20
#define RK_PC5 21
#define RK_PC6 22
#define RK_PC7 23
#define RK_PD0 24
#define RK_PD1 25
#define RK_PD2 26
#define RK_PD3 27
#define RK_PD4 28
#define RK_PD5 29
#define RK_PD6 30
#define RK_PD7 31
#define RK_FUNC_GPIO 0
#define RK_FUNC_1 1
#define RK_FUNC_2 2

27
include/dt-bindings/power/mt2701-power.h Normal file
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@@ -0,0 +1,27 @@
/*
* Copyright (C) 2015 MediaTek Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
#define _DT_BINDINGS_POWER_MT2701_POWER_H
#define MT2701_POWER_DOMAIN_CONN 0
#define MT2701_POWER_DOMAIN_DISP 1
#define MT2701_POWER_DOMAIN_MFG 2
#define MT2701_POWER_DOMAIN_VDEC 3
#define MT2701_POWER_DOMAIN_ISP 4
#define MT2701_POWER_DOMAIN_BDP 5
#define MT2701_POWER_DOMAIN_ETH 6
#define MT2701_POWER_DOMAIN_HIF 7
#define MT2701_POWER_DOMAIN_IFR_MSC 8
#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */

25
include/dt-bindings/power/r8a7743-sysc.h Normal file
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@@ -0,0 +1,25 @@
/*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7743_PD_CA15_CPU0 0
#define R8A7743_PD_CA15_CPU1 1
#define R8A7743_PD_CA15_SCU 12
#define R8A7743_PD_SGX 20
/* Always-on power area */
#define R8A7743_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */

25
include/dt-bindings/power/r8a7745-sysc.h Normal file
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@@ -0,0 +1,25 @@
/*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7745_PD_CA7_CPU0 5
#define R8A7745_PD_CA7_CPU1 6
#define R8A7745_PD_SGX 20
#define R8A7745_PD_CA7_SCU 21
/* Always-on power area */
#define R8A7745_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */

39
include/dt-bindings/power/tegra186-powergate.h Normal file
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@@ -0,0 +1,39 @@
/*
* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
#define TEGRA186_POWER_DOMAIN_AUD 0
#define TEGRA186_POWER_DOMAIN_DFD 1
#define TEGRA186_POWER_DOMAIN_DISP 2
#define TEGRA186_POWER_DOMAIN_DISPB 3
#define TEGRA186_POWER_DOMAIN_DISPC 4
#define TEGRA186_POWER_DOMAIN_ISPA 5
#define TEGRA186_POWER_DOMAIN_NVDEC 6
#define TEGRA186_POWER_DOMAIN_NVJPG 7
#define TEGRA186_POWER_DOMAIN_MPE 8
#define TEGRA186_POWER_DOMAIN_PCX 9
#define TEGRA186_POWER_DOMAIN_SAX 10
#define TEGRA186_POWER_DOMAIN_VE 11
#define TEGRA186_POWER_DOMAIN_VIC 12
#define TEGRA186_POWER_DOMAIN_XUSBA 13
#define TEGRA186_POWER_DOMAIN_XUSBB 14
#define TEGRA186_POWER_DOMAIN_XUSBC 15
#define TEGRA186_POWER_DOMAIN_GPU 43
#define TEGRA186_POWER_DOMAIN_MAX 44
#endif

53
include/dt-bindings/reset/oxsemi,ox810se.h Normal file
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@@ -0,0 +1,53 @@
/*
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef DT_RESET_OXSEMI_OX810SE_H
#define DT_RESET_OXSEMI_OX810SE_H
#define RESET_ARM 0
#define RESET_COPRO 1
/* Reserved 2 */
/* Reserved 3 */
#define RESET_USBHS 4
#define RESET_USBHSPHY 5
#define RESET_MAC 6
#define RESET_PCI 7
#define RESET_DMA 8
#define RESET_DPE 9
#define RESET_DDR 10
#define RESET_SATA 11
#define RESET_SATA_LINK 12
#define RESET_SATA_PHY 13
/* Reserved 14 */
#define RESET_NAND 15
#define RESET_GPIO 16
#define RESET_UART1 17
#define RESET_UART2 18
#define RESET_MISC 19
#define RESET_I2S 20
#define RESET_AHB_MON 21
#define RESET_UART3 22
#define RESET_UART4 23
#define RESET_SGDMA 24
/* Reserved 25 */
/* Reserved 26 */
/* Reserved 27 */
/* Reserved 28 */
/* Reserved 29 */
/* Reserved 30 */
#define RESET_BUS 31
#endif /* DT_RESET_OXSEMI_OX810SE_H */

53
include/dt-bindings/reset/oxsemi,ox820.h Normal file
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@@ -0,0 +1,53 @@
/*
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef DT_RESET_OXSEMI_OX820_H
#define DT_RESET_OXSEMI_OX820_H
#define RESET_SCU 0
#define RESET_LEON 1
#define RESET_ARM0 2
#define RESET_ARM1 3
#define RESET_USBHS 4
#define RESET_USBPHYA 5
#define RESET_MAC 6
#define RESET_PCIEA 7
#define RESET_SGDMA 8
#define RESET_CIPHER 9
#define RESET_DDR 10
#define RESET_SATA 11
#define RESET_SATA_LINK 12
#define RESET_SATA_PHY 13
#define RESET_PCIEPHY 14
#define RESET_NAND 15
#define RESET_GPIO 16
#define RESET_UART1 17
#define RESET_UART2 18
#define RESET_MISC 19
#define RESET_I2S 20
#define RESET_SD 21
#define RESET_MAC_2 22
#define RESET_PCIEB 23
#define RESET_VIDEO 24
#define RESET_DDR_PHY 25
#define RESET_USBPHYB 26
#define RESET_USBDEV 27
/* Reserved 29 */
#define RESET_ARMDBG 29
#define RESET_PLLA 30
#define RESET_PLLB 31
#endif /* DT_RESET_OXSEMI_OX820_H */

98
include/dt-bindings/reset/sun50i-a64-ccu.h Normal file
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@@ -0,0 +1,98 @@
/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
#define _DT_BINDINGS_RST_SUN50I_A64_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_HSIC 2
#define RST_DRAM 3
#define RST_MBUS 4
#define RST_BUS_MIPI_DSI 5
#define RST_BUS_CE 6
#define RST_BUS_DMA 7
#define RST_BUS_MMC0 8
#define RST_BUS_MMC1 9
#define RST_BUS_MMC2 10
#define RST_BUS_NAND 11
#define RST_BUS_DRAM 12
#define RST_BUS_EMAC 13
#define RST_BUS_TS 14
#define RST_BUS_HSTIMER 15
#define RST_BUS_SPI0 16
#define RST_BUS_SPI1 17
#define RST_BUS_OTG 18
#define RST_BUS_EHCI0 19
#define RST_BUS_EHCI1 20
#define RST_BUS_OHCI0 21
#define RST_BUS_OHCI1 22
#define RST_BUS_VE 23
#define RST_BUS_TCON0 24
#define RST_BUS_TCON1 25
#define RST_BUS_DEINTERLACE 26
#define RST_BUS_CSI 27
#define RST_BUS_HDMI0 28
#define RST_BUS_HDMI1 29
#define RST_BUS_DE 30
#define RST_BUS_GPU 31
#define RST_BUS_MSGBOX 32
#define RST_BUS_SPINLOCK 33
#define RST_BUS_DBG 34
#define RST_BUS_LVDS 35
#define RST_BUS_CODEC 36
#define RST_BUS_SPDIF 37
#define RST_BUS_THS 38
#define RST_BUS_I2S0 39
#define RST_BUS_I2S1 40
#define RST_BUS_I2S2 41
#define RST_BUS_I2C0 42
#define RST_BUS_I2C1 43
#define RST_BUS_I2C2 44
#define RST_BUS_SCR 45
#define RST_BUS_UART0 46
#define RST_BUS_UART1 47
#define RST_BUS_UART2 48
#define RST_BUS_UART3 49
#define RST_BUS_UART4 50
#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */

217
include/dt-bindings/reset/tegra186-reset.h Normal file
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@@ -0,0 +1,217 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _ABI_MACH_T186_RESET_T186_H_
#define _ABI_MACH_T186_RESET_T186_H_
#define TEGRA186_RESET_ACTMON 0
#define TEGRA186_RESET_AFI 1
#define TEGRA186_RESET_CEC 2
#define TEGRA186_RESET_CSITE 3
#define TEGRA186_RESET_DP2 4
#define TEGRA186_RESET_DPAUX 5
#define TEGRA186_RESET_DSI 6
#define TEGRA186_RESET_DSIB 7
#define TEGRA186_RESET_DTV 8
#define TEGRA186_RESET_DVFS 9
#define TEGRA186_RESET_ENTROPY 10
#define TEGRA186_RESET_EXTPERIPH1 11
#define TEGRA186_RESET_EXTPERIPH2 12
#define TEGRA186_RESET_EXTPERIPH3 13
#define TEGRA186_RESET_GPU 14
#define TEGRA186_RESET_HDA 15
#define TEGRA186_RESET_HDA2CODEC_2X 16
#define TEGRA186_RESET_HDA2HDMICODEC 17
#define TEGRA186_RESET_HOST1X 18
#define TEGRA186_RESET_I2C1 19
#define TEGRA186_RESET_I2C2 20
#define TEGRA186_RESET_I2C3 21
#define TEGRA186_RESET_I2C4 22
#define TEGRA186_RESET_I2C5 23
#define TEGRA186_RESET_I2C6 24
#define TEGRA186_RESET_ISP 25
#define TEGRA186_RESET_KFUSE 26
#define TEGRA186_RESET_LA 27
#define TEGRA186_RESET_MIPI_CAL 28
#define TEGRA186_RESET_PCIE 29
#define TEGRA186_RESET_PCIEXCLK 30
#define TEGRA186_RESET_SATA 31
#define TEGRA186_RESET_SATACOLD 32
#define TEGRA186_RESET_SDMMC1 33
#define TEGRA186_RESET_SDMMC2 34
#define TEGRA186_RESET_SDMMC3 35
#define TEGRA186_RESET_SDMMC4 36
#define TEGRA186_RESET_SE 37
#define TEGRA186_RESET_SOC_THERM 38
#define TEGRA186_RESET_SOR0 39
#define TEGRA186_RESET_SPI1 40
#define TEGRA186_RESET_SPI2 41
#define TEGRA186_RESET_SPI3 42
#define TEGRA186_RESET_SPI4 43
#define TEGRA186_RESET_TMR 44
#define TEGRA186_RESET_TRIG_SYS 45
#define TEGRA186_RESET_TSEC 46
#define TEGRA186_RESET_UARTA 47
#define TEGRA186_RESET_UARTB 48
#define TEGRA186_RESET_UARTC 49
#define TEGRA186_RESET_UARTD 50
#define TEGRA186_RESET_VI 51
#define TEGRA186_RESET_VIC 52
#define TEGRA186_RESET_XUSB_DEV 53
#define TEGRA186_RESET_XUSB_HOST 54
#define TEGRA186_RESET_XUSB_PADCTL 55
#define TEGRA186_RESET_XUSB_SS 56
#define TEGRA186_RESET_AON_APB 57
#define TEGRA186_RESET_AXI_CBB 58
#define TEGRA186_RESET_BPMP_APB 59
#define TEGRA186_RESET_CAN1 60
#define TEGRA186_RESET_CAN2 61
#define TEGRA186_RESET_DMIC5 62
#define TEGRA186_RESET_DSIC 63
#define TEGRA186_RESET_DSID 64
#define TEGRA186_RESET_EMC_EMC 65
#define TEGRA186_RESET_EMC_MEM 66
#define TEGRA186_RESET_EMCSB_EMC 67
#define TEGRA186_RESET_EMCSB_MEM 68
#define TEGRA186_RESET_EQOS 69
#define TEGRA186_RESET_GPCDMA 70
#define TEGRA186_RESET_GPIO_CTL0 71
#define TEGRA186_RESET_GPIO_CTL1 72
#define TEGRA186_RESET_GPIO_CTL2 73
#define TEGRA186_RESET_GPIO_CTL3 74
#define TEGRA186_RESET_GPIO_CTL4 75
#define TEGRA186_RESET_GPIO_CTL5 76
#define TEGRA186_RESET_I2C10 77
#define TEGRA186_RESET_I2C12 78
#define TEGRA186_RESET_I2C13 79
#define TEGRA186_RESET_I2C14 80
#define TEGRA186_RESET_I2C7 81
#define TEGRA186_RESET_I2C8 82
#define TEGRA186_RESET_I2C9 83
#define TEGRA186_RESET_JTAG2AXI 84
#define TEGRA186_RESET_MPHY_IOBIST 85
#define TEGRA186_RESET_MPHY_L0_RX 86
#define TEGRA186_RESET_MPHY_L0_TX 87
#define TEGRA186_RESET_NVCSI 88
#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89
#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90
#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91
#define TEGRA186_RESET_NVDISPLAY0_MISC 92
#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93
#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94
#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95
#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96
#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97
#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98
#define TEGRA186_RESET_PWM1 99
#define TEGRA186_RESET_PWM2 100
#define TEGRA186_RESET_PWM3 101
#define TEGRA186_RESET_PWM4 102
#define TEGRA186_RESET_PWM5 103
#define TEGRA186_RESET_PWM6 104
#define TEGRA186_RESET_PWM7 105
#define TEGRA186_RESET_PWM8 106
#define TEGRA186_RESET_SCE_APB 107
#define TEGRA186_RESET_SOR1 108
#define TEGRA186_RESET_TACH 109
#define TEGRA186_RESET_TSC 110
#define TEGRA186_RESET_UARTF 111
#define TEGRA186_RESET_UARTG 112
#define TEGRA186_RESET_UFSHC 113
#define TEGRA186_RESET_UFSHC_AXI_M 114
#define TEGRA186_RESET_UPHY 115
#define TEGRA186_RESET_ADSP 116
#define TEGRA186_RESET_ADSPDBG 117
#define TEGRA186_RESET_ADSPINTF 118
#define TEGRA186_RESET_ADSPNEON 119
#define TEGRA186_RESET_ADSPPERIPH 120
#define TEGRA186_RESET_ADSPSCU 121
#define TEGRA186_RESET_ADSPWDT 122
#define TEGRA186_RESET_APE 123
#define TEGRA186_RESET_DPAUX1 124
#define TEGRA186_RESET_NVDEC 125
#define TEGRA186_RESET_NVENC 126
#define TEGRA186_RESET_NVJPG 127
#define TEGRA186_RESET_PEX_USB_UPHY 128
#define TEGRA186_RESET_QSPI 129
#define TEGRA186_RESET_TSECB 130
#define TEGRA186_RESET_VI_I2C 131
#define TEGRA186_RESET_UARTE 132
#define TEGRA186_RESET_TOP_GTE 133
#define TEGRA186_RESET_SHSP 134
#define TEGRA186_RESET_PEX_USB_UPHY_L5 135
#define TEGRA186_RESET_PEX_USB_UPHY_L4 136
#define TEGRA186_RESET_PEX_USB_UPHY_L3 137
#define TEGRA186_RESET_PEX_USB_UPHY_L2 138
#define TEGRA186_RESET_PEX_USB_UPHY_L1 139
#define TEGRA186_RESET_PEX_USB_UPHY_L0 140
#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141
#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142
#define TEGRA186_RESET_TSCTNVI 143
#define TEGRA186_RESET_EXTPERIPH4 144
#define TEGRA186_RESET_DSIPADCTL 145
#define TEGRA186_RESET_AUD_MCLK 146
#define TEGRA186_RESET_MPHY_CLK_CTL 147
#define TEGRA186_RESET_MPHY_L1_RX 148
#define TEGRA186_RESET_MPHY_L1_TX 149
#define TEGRA186_RESET_UFSHC_LP 150
#define TEGRA186_RESET_BPMP_NIC 151
#define TEGRA186_RESET_BPMP_NSYSPORESET 152
#define TEGRA186_RESET_BPMP_NRESET 153
#define TEGRA186_RESET_BPMP_DBGRESETN 154
#define TEGRA186_RESET_BPMP_PRESETDBGN 155
#define TEGRA186_RESET_BPMP_PM 156
#define TEGRA186_RESET_BPMP_CVC 157
#define TEGRA186_RESET_BPMP_DMA 158
#define TEGRA186_RESET_BPMP_HSP 159
#define TEGRA186_RESET_TSCTNBPMP 160
#define TEGRA186_RESET_BPMP_TKE 161
#define TEGRA186_RESET_BPMP_GTE 162
#define TEGRA186_RESET_BPMP_PM_ACTMON 163
#define TEGRA186_RESET_AON_NIC 164
#define TEGRA186_RESET_AON_NSYSPORESET 165
#define TEGRA186_RESET_AON_NRESET 166
#define TEGRA186_RESET_AON_DBGRESETN 167
#define TEGRA186_RESET_AON_PRESETDBGN 168
#define TEGRA186_RESET_AON_ACTMON 169
#define TEGRA186_RESET_AOPM 170
#define TEGRA186_RESET_AOVC 171
#define TEGRA186_RESET_AON_DMA 172
#define TEGRA186_RESET_AON_GPIO 173
#define TEGRA186_RESET_AON_HSP 174
#define TEGRA186_RESET_TSCTNAON 175
#define TEGRA186_RESET_AON_TKE 176
#define TEGRA186_RESET_AON_GTE 177
#define TEGRA186_RESET_SCE_NIC 178
#define TEGRA186_RESET_SCE_NSYSPORESET 179
#define TEGRA186_RESET_SCE_NRESET 180
#define TEGRA186_RESET_SCE_DBGRESETN 181
#define TEGRA186_RESET_SCE_PRESETDBGN 182
#define TEGRA186_RESET_SCE_ACTMON 183
#define TEGRA186_RESET_SCE_PM 184
#define TEGRA186_RESET_SCE_DMA 185
#define TEGRA186_RESET_SCE_HSP 186
#define TEGRA186_RESET_TSCTNSCE 187
#define TEGRA186_RESET_SCE_TKE 188
#define TEGRA186_RESET_SCE_GTE 189
#define TEGRA186_RESET_SCE_CFG 190
#define TEGRA186_RESET_ADSP_ALL 191
/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
#define TEGRA186_RESET_UFSHC_LP_SEQ 192
#define TEGRA186_RESET_SIZE 193
#endif

73
include/dt-bindings/sound/cs42l42.h Normal file
View File

@@ -0,0 +1,73 @@
/*
* cs42l42.h -- CS42L42 ALSA SoC audio driver DT bindings header
*
* Copyright 2016 Cirrus Logic, Inc.
*
* Author: James Schulman <james.schulman@cirrus.com>
* Author: Brian Austin <brian.austin@cirrus.com>
* Author: Michael White <michael.white@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_CS42L42_H
#define __DT_CS42L42_H
/* HPOUT Load Capacity */
#define CS42L42_HPOUT_LOAD_1NF 0
#define CS42L42_HPOUT_LOAD_10NF 1
/* HPOUT Clamp to GND Overide */
#define CS42L42_HPOUT_CLAMP_EN 0
#define CS42L42_HPOUT_CLAMP_DIS 1
/* Tip Sense Inversion */
#define CS42L42_TS_INV_DIS 0
#define CS42L42_TS_INV_EN 1
/* Tip Sense Debounce */
#define CS42L42_TS_DBNCE_0 0
#define CS42L42_TS_DBNCE_125 1
#define CS42L42_TS_DBNCE_250 2
#define CS42L42_TS_DBNCE_500 3
#define CS42L42_TS_DBNCE_750 4
#define CS42L42_TS_DBNCE_1000 5
#define CS42L42_TS_DBNCE_1250 6
#define CS42L42_TS_DBNCE_1500 7
/* Button Press Software Debounce Times */
#define CS42L42_BTN_DET_INIT_DBNCE_MIN 0
#define CS42L42_BTN_DET_INIT_DBNCE_DEFAULT 100
#define CS42L42_BTN_DET_INIT_DBNCE_MAX 200
#define CS42L42_BTN_DET_EVENT_DBNCE_MIN 0
#define CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT 10
#define CS42L42_BTN_DET_EVENT_DBNCE_MAX 20
/* Button Detect Level Sensitivities */
#define CS42L42_NUM_BIASES 4
#define CS42L42_HS_DET_LEVEL_15 0x0F
#define CS42L42_HS_DET_LEVEL_8 0x08
#define CS42L42_HS_DET_LEVEL_4 0x04
#define CS42L42_HS_DET_LEVEL_1 0x01
#define CS42L42_HS_DET_LEVEL_MIN 0
#define CS42L42_HS_DET_LEVEL_MAX 0x3F
/* HS Bias Ramp Rate */
#define CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL 0
#define CS42L42_HSBIAS_RAMP_FAST 1
#define CS42L42_HSBIAS_RAMP_SLOW 2
#define CS42L42_HSBIAS_RAMP_SLOWEST 3
#define CS42L42_HSBIAS_RAMP_TIME0 10
#define CS42L42_HSBIAS_RAMP_TIME1 40
#define CS42L42_HSBIAS_RAMP_TIME2 90
#define CS42L42_HSBIAS_RAMP_TIME3 170
#endif /* __DT_CS42L42_H */

4
include/kvm/arm_arch_timer.h
View File

@@ -25,13 +25,13 @@
struct arch_timer_kvm {
/* Virtual offset */
cycle_t cntvoff;
u64 cntvoff;
};
struct arch_timer_cpu {
/* Registers: control register, timer value */
u32 cntv_ctl; /* Saved/restored */
cycle_t cntv_cval; /* Saved/restored */
u64 cntv_cval; /* Saved/restored */
/*
* Anything that is not used directly from assembly code goes

38
include/linux/acpi.h
View File

@@ -56,6 +56,27 @@ static inline acpi_handle acpi_device_handle(struct acpi_device *adev)
acpi_fwnode_handle(adev) : NULL)
#define ACPI_HANDLE(dev) acpi_device_handle(ACPI_COMPANION(dev))
static inline struct fwnode_handle *acpi_alloc_fwnode_static(void)
{
struct fwnode_handle *fwnode;
fwnode = kzalloc(sizeof(struct fwnode_handle), GFP_KERNEL);
if (!fwnode)
return NULL;
fwnode->type = FWNODE_ACPI_STATIC;
return fwnode;
}
static inline void acpi_free_fwnode_static(struct fwnode_handle *fwnode)
{
if (WARN_ON(!fwnode || fwnode->type != FWNODE_ACPI_STATIC))
return;
kfree(fwnode);
}
/**
* ACPI_DEVICE_CLASS - macro used to describe an ACPI device with
* the PCI-defined class-code information
@@ -220,10 +241,6 @@ int __init acpi_table_parse_entries(char *id, unsigned long table_size,
int entry_id,
acpi_tbl_entry_handler handler,
unsigned int max_entries);
int __init acpi_table_parse_entries(char *id, unsigned long table_size,
int entry_id,
acpi_tbl_entry_handler handler,
unsigned int max_entries);
int __init acpi_table_parse_entries_array(char *id, unsigned long table_size,
struct acpi_subtable_proc *proc, int proc_num,
unsigned int max_entries);
@@ -420,6 +437,8 @@ static inline int acpi_dev_filter_resource_type_cb(struct acpi_resource *ares,
return acpi_dev_filter_resource_type(ares, (unsigned long)arg);
}
struct acpi_device *acpi_resource_consumer(struct resource *res);
int acpi_check_resource_conflict(const struct resource *res);
int acpi_check_region(resource_size_t start, resource_size_t n,
@@ -469,6 +488,7 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
#define OSC_SB_CPCV2_SUPPORT 0x00000040
#define OSC_SB_PCLPI_SUPPORT 0x00000080
#define OSC_SB_OSLPI_SUPPORT 0x00000100
#define OSC_SB_CPC_DIVERSE_HIGH_SUPPORT 0x00001000
extern bool osc_sb_apei_support_acked;
extern bool osc_pc_lpi_support_confirmed;
@@ -744,6 +764,11 @@ static inline enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev)
return DEV_DMA_NOT_SUPPORTED;
}
static inline void acpi_dma_configure(struct device *dev,
enum dev_dma_attr attr) { }
static inline void acpi_dma_deconfigure(struct device *dev) { }
#define ACPI_PTR(_ptr) (NULL)
static inline void acpi_device_set_enumerated(struct acpi_device *adev)
@@ -764,6 +789,11 @@ static inline int acpi_reconfig_notifier_unregister(struct notifier_block *nb)
return -EINVAL;
}
static inline struct acpi_device *acpi_resource_consumer(struct resource *res)
{
return NULL;
}
#endif /* !CONFIG_ACPI */
#ifdef CONFIG_ACPI_HOTPLUG_IOAPIC

16
include/linux/acpi_iort.h
View File

@@ -23,20 +23,36 @@
#include <linux/fwnode.h>
#include <linux/irqdomain.h>
#define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL)
#define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL)
int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node);
void iort_deregister_domain_token(int trans_id);
struct fwnode_handle *iort_find_domain_token(int trans_id);
#ifdef CONFIG_ACPI_IORT
void acpi_iort_init(void);
bool iort_node_match(u8 type);
u32 iort_msi_map_rid(struct device *dev, u32 req_id);
struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id);
/* IOMMU interface */
void iort_set_dma_mask(struct device *dev);
const struct iommu_ops *iort_iommu_configure(struct device *dev);
#else
static inline void acpi_iort_init(void) { }
static inline bool iort_node_match(u8 type) { return false; }
static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id)
{ return req_id; }
static inline struct irq_domain *iort_get_device_domain(struct device *dev,
u32 req_id)
{ return NULL; }
/* IOMMU interface */
static inline void iort_set_dma_mask(struct device *dev) { }
static inline
const struct iommu_ops *iort_iommu_configure(struct device *dev)
{ return NULL; }
#endif
#define IORT_ACPI_DECLARE(name, table_id, fn) \
ACPI_DECLARE_PROBE_ENTRY(iort, name, table_id, 0, NULL, 0, fn)
#endif /* __ACPI_IORT_H__ */

28
include/linux/ahci-remap.h Normal file
View File

@@ -0,0 +1,28 @@
#ifndef _LINUX_AHCI_REMAP_H
#define _LINUX_AHCI_REMAP_H
#include <linux/sizes.h>
#define AHCI_VSCAP 0xa4
#define AHCI_REMAP_CAP 0x800
/* device class code */
#define AHCI_REMAP_N_DCC 0x880
/* remap-device base relative to ahci-bar */
#define AHCI_REMAP_N_OFFSET SZ_16K
#define AHCI_REMAP_N_SIZE SZ_16K
#define AHCI_MAX_REMAP 3
static inline unsigned int ahci_remap_dcc(int i)
{
return AHCI_REMAP_N_DCC + i * 0x80;
}
static inline unsigned int ahci_remap_base(int i)
{
return AHCI_REMAP_N_OFFSET + i * AHCI_REMAP_N_SIZE;
}
#endif /* _LINUX_AHCI_REMAP_H */

5
include/linux/aio.h
View File

@@ -14,14 +14,9 @@ typedef int (kiocb_cancel_fn)(struct kiocb *);
/* prototypes */
#ifdef CONFIG_AIO
extern void exit_aio(struct mm_struct *mm);
extern long do_io_submit(aio_context_t ctx_id, long nr,
struct iocb __user *__user *iocbpp, bool compat);
void kiocb_set_cancel_fn(struct kiocb *req, kiocb_cancel_fn *cancel);
#else
static inline void exit_aio(struct mm_struct *mm) { }
static inline long do_io_submit(aio_context_t ctx_id, long nr,
struct iocb __user * __user *iocbpp,
bool compat) { return 0; }
static inline void kiocb_set_cancel_fn(struct kiocb *req,
kiocb_cancel_fn *cancel) { }
#endif /* CONFIG_AIO */

5
include/linux/alarmtimer.h
View File

@@ -10,7 +10,12 @@ enum alarmtimer_type {
ALARM_REALTIME,
ALARM_BOOTTIME,
/* Supported types end here */
ALARM_NUMTYPE,
/* Used for tracing information. No usable types. */
ALARM_REALTIME_FREEZER,
ALARM_BOOTTIME_FREEZER,
};
enum alarmtimer_restart {

16
include/linux/amba/pl061.h
View File

@@ -1,16 +0,0 @@
#include <linux/types.h>
/* platform data for the PL061 GPIO driver */
struct pl061_platform_data {
/* number of the first GPIO */
unsigned gpio_base;
/* number of the first IRQ.
* If the IRQ functionality in not desired this must be set to 0.
*/
unsigned irq_base;
u8 directions; /* startup directions, 1: out, 0: in */
u8 values; /* startup values */
};

4
include/linux/amba/pl08x.h
View File

@@ -84,6 +84,8 @@ struct pl08x_channel_data {
* running any DMA transfer and multiplexing can be recycled
* @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
* @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
* @slave_map: DMA slave matching table
* @slave_map_len: number of elements in @slave_map
*/
struct pl08x_platform_data {
struct pl08x_channel_data *slave_channels;
@@ -93,6 +95,8 @@ struct pl08x_platform_data {
void (*put_xfer_signal)(const struct pl08x_channel_data *, int);
u8 lli_buses;
u8 mem_buses;
const struct dma_slave_map *slave_map;
int slave_map_len;
};
#ifdef CONFIG_AMBA_PL08X

6
include/linux/ata.h
View File

@@ -348,6 +348,7 @@ enum {
ATA_LOG_DEVSLP_DETO = 0x01,
ATA_LOG_DEVSLP_VALID = 0x07,
ATA_LOG_DEVSLP_VALID_MASK = 0x80,
ATA_LOG_NCQ_PRIO_OFFSET = 0x09,
/* NCQ send and receive log */
ATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET = 0x00,
@@ -940,6 +941,11 @@ static inline bool ata_id_has_ncq_non_data(const u16 *id)
return id[ATA_ID_SATA_CAPABILITY_2] & BIT(5);
}
static inline bool ata_id_has_ncq_prio(const u16 *id)
{
return id[ATA_ID_SATA_CAPABILITY] & BIT(12);
}
static inline bool ata_id_has_trim(const u16 *id)
{
if (ata_id_major_version(id) >= 7 &&

2
include/linux/audit.h
View File

@@ -147,7 +147,7 @@ extern void audit_log_d_path(struct audit_buffer *ab,
extern void audit_log_key(struct audit_buffer *ab,
char *key);
extern void audit_log_link_denied(const char *operation,
struct path *link);
const struct path *link);
extern void audit_log_lost(const char *message);
#ifdef CONFIG_SECURITY
extern void audit_log_secctx(struct audit_buffer *ab, u32 secid);

5
include/linux/backing-dev-defs.h
View File

@@ -116,6 +116,8 @@ struct bdi_writeback {
struct list_head work_list;
struct delayed_work dwork; /* work item used for writeback */
unsigned long dirty_sleep; /* last wait */
struct list_head bdi_node; /* anchored at bdi->wb_list */
#ifdef CONFIG_CGROUP_WRITEBACK
@@ -136,12 +138,13 @@ struct bdi_writeback {
struct backing_dev_info {
struct list_head bdi_list;
unsigned long ra_pages; /* max readahead in PAGE_SIZE units */
unsigned int capabilities; /* Device capabilities */
unsigned long io_pages; /* max allowed IO size */
congested_fn *congested_fn; /* Function pointer if device is md/dm */
void *congested_data; /* Pointer to aux data for congested func */
char *name;
unsigned int capabilities; /* Device capabilities */
unsigned int min_ratio;
unsigned int max_ratio, max_prop_frac;

49
include/linux/bio.h
View File

@@ -62,6 +62,12 @@
#define bio_sectors(bio) ((bio)->bi_iter.bi_size >> 9)
#define bio_end_sector(bio) ((bio)->bi_iter.bi_sector + bio_sectors((bio)))
/*
* Return the data direction, READ or WRITE.
*/
#define bio_data_dir(bio) \
(op_is_write(bio_op(bio)) ? WRITE : READ)
/*
* Check whether this bio carries any data or not. A NULL bio is allowed.
*/
@@ -70,7 +76,8 @@ static inline bool bio_has_data(struct bio *bio)
if (bio &&
bio->bi_iter.bi_size &&
bio_op(bio) != REQ_OP_DISCARD &&
bio_op(bio) != REQ_OP_SECURE_ERASE)
bio_op(bio) != REQ_OP_SECURE_ERASE &&
bio_op(bio) != REQ_OP_WRITE_ZEROES)
return true;
return false;
@@ -80,18 +87,8 @@ static inline bool bio_no_advance_iter(struct bio *bio)
{
return bio_op(bio) == REQ_OP_DISCARD ||
bio_op(bio) == REQ_OP_SECURE_ERASE ||
bio_op(bio) == REQ_OP_WRITE_SAME;
}
static inline bool bio_is_rw(struct bio *bio)
{
if (!bio_has_data(bio))
return false;
if (bio_no_advance_iter(bio))
return false;
return true;
bio_op(bio) == REQ_OP_WRITE_SAME ||
bio_op(bio) == REQ_OP_WRITE_ZEROES;
}
static inline bool bio_mergeable(struct bio *bio)
@@ -193,18 +190,20 @@ static inline unsigned bio_segments(struct bio *bio)
struct bvec_iter iter;
/*
* We special case discard/write same, because they interpret bi_size
* differently:
* We special case discard/write same/write zeroes, because they
* interpret bi_size differently:
*/
if (bio_op(bio) == REQ_OP_DISCARD)
return 1;
if (bio_op(bio) == REQ_OP_SECURE_ERASE)
return 1;
if (bio_op(bio) == REQ_OP_WRITE_SAME)
switch (bio_op(bio)) {
case REQ_OP_DISCARD:
case REQ_OP_SECURE_ERASE:
case REQ_OP_WRITE_ZEROES:
return 0;
case REQ_OP_WRITE_SAME:
return 1;
default:
break;
}
bio_for_each_segment(bv, bio, iter)
segs++;
@@ -409,6 +408,8 @@ static inline struct bio *bio_clone_kmalloc(struct bio *bio, gfp_t gfp_mask)
}
extern blk_qc_t submit_bio(struct bio *);
extern void bio_endio(struct bio *);
static inline void bio_io_error(struct bio *bio)
@@ -423,13 +424,15 @@ extern int bio_phys_segments(struct request_queue *, struct bio *);
extern int submit_bio_wait(struct bio *bio);
extern void bio_advance(struct bio *, unsigned);
extern void bio_init(struct bio *);
extern void bio_init(struct bio *bio, struct bio_vec *table,
unsigned short max_vecs);
extern void bio_reset(struct bio *);
void bio_chain(struct bio *, struct bio *);
extern int bio_add_page(struct bio *, struct page *, unsigned int,unsigned int);
extern int bio_add_pc_page(struct request_queue *, struct bio *, struct page *,
unsigned int, unsigned int);
int bio_iov_iter_get_pages(struct bio *bio, struct iov_iter *iter);
struct rq_map_data;
extern struct bio *bio_map_user_iov(struct request_queue *,
const struct iov_iter *, gfp_t);

11
include/linux/blk-cgroup.h
View File

@@ -581,15 +581,14 @@ static inline void blkg_rwstat_exit(struct blkg_rwstat *rwstat)
/**
* blkg_rwstat_add - add a value to a blkg_rwstat
* @rwstat: target blkg_rwstat
* @op: REQ_OP
* @op_flags: rq_flag_bits
* @op: REQ_OP and flags
* @val: value to add
*
* Add @val to @rwstat. The counters are chosen according to @rw. The
* caller is responsible for synchronizing calls to this function.
*/
static inline void blkg_rwstat_add(struct blkg_rwstat *rwstat,
int op, int op_flags, uint64_t val)
unsigned int op, uint64_t val)
{
struct percpu_counter *cnt;
@@ -600,7 +599,7 @@ static inline void blkg_rwstat_add(struct blkg_rwstat *rwstat,
__percpu_counter_add(cnt, val, BLKG_STAT_CPU_BATCH);
if (op_flags & REQ_SYNC)
if (op_is_sync(op))
cnt = &rwstat->cpu_cnt[BLKG_RWSTAT_SYNC];
else
cnt = &rwstat->cpu_cnt[BLKG_RWSTAT_ASYNC];
@@ -705,9 +704,9 @@ static inline bool blkcg_bio_issue_check(struct request_queue *q,
if (!throtl) {
blkg = blkg ?: q->root_blkg;
blkg_rwstat_add(&blkg->stat_bytes, bio_op(bio), bio->bi_opf,
blkg_rwstat_add(&blkg->stat_bytes, bio->bi_opf,
bio->bi_iter.bi_size);
blkg_rwstat_add(&blkg->stat_ios, bio_op(bio), bio->bi_opf, 1);
blkg_rwstat_add(&blkg->stat_ios, bio->bi_opf, 1);
}
rcu_read_unlock();

12
include/linux/blk-mq.h
View File

@@ -3,6 +3,7 @@
#include <linux/blkdev.h>
#include <linux/sbitmap.h>
#include <linux/srcu.h>
struct blk_mq_tags;
struct blk_flush_queue;
@@ -35,6 +36,8 @@ struct blk_mq_hw_ctx {
struct blk_mq_tags *tags;
struct srcu_struct queue_rq_srcu;
unsigned long queued;
unsigned long run;
#define BLK_MQ_MAX_DISPATCH_ORDER 7
@@ -215,18 +218,20 @@ void blk_mq_start_request(struct request *rq);
void blk_mq_end_request(struct request *rq, int error);
void __blk_mq_end_request(struct request *rq, int error);
void blk_mq_requeue_request(struct request *rq);
void blk_mq_add_to_requeue_list(struct request *rq, bool at_head);
void blk_mq_cancel_requeue_work(struct request_queue *q);
void blk_mq_requeue_request(struct request *rq, bool kick_requeue_list);
void blk_mq_add_to_requeue_list(struct request *rq, bool at_head,
bool kick_requeue_list);
void blk_mq_kick_requeue_list(struct request_queue *q);
void blk_mq_delay_kick_requeue_list(struct request_queue *q, unsigned long msecs);
void blk_mq_abort_requeue_list(struct request_queue *q);
void blk_mq_complete_request(struct request *rq, int error);
bool blk_mq_queue_stopped(struct request_queue *q);
void blk_mq_stop_hw_queue(struct blk_mq_hw_ctx *hctx);
void blk_mq_start_hw_queue(struct blk_mq_hw_ctx *hctx);
void blk_mq_stop_hw_queues(struct request_queue *q);
void blk_mq_start_hw_queues(struct request_queue *q);
void blk_mq_start_stopped_hw_queue(struct blk_mq_hw_ctx *hctx, bool async);
void blk_mq_start_stopped_hw_queues(struct request_queue *q, bool async);
void blk_mq_run_hw_queues(struct request_queue *q, bool async);
void blk_mq_delay_queue(struct blk_mq_hw_ctx *hctx, unsigned long msecs);
@@ -237,6 +242,7 @@ void blk_mq_unfreeze_queue(struct request_queue *q);
void blk_mq_freeze_queue_start(struct request_queue *q);
int blk_mq_reinit_tagset(struct blk_mq_tag_set *set);
int blk_mq_map_queues(struct blk_mq_tag_set *set);
void blk_mq_update_nr_hw_queues(struct blk_mq_tag_set *set, int nr_hw_queues);
/*

186
include/linux/blk_types.h
View File

@@ -17,7 +17,6 @@ struct io_context;
struct cgroup_subsys_state;
typedef void (bio_end_io_t) (struct bio *);
#ifdef CONFIG_BLOCK
/*
* main unit of I/O for the block layer and lower layers (ie drivers and
* stacking drivers)
@@ -88,24 +87,6 @@ struct bio {
struct bio_vec bi_inline_vecs[0];
};
#define BIO_OP_SHIFT (8 * FIELD_SIZEOF(struct bio, bi_opf) - REQ_OP_BITS)
#define bio_flags(bio) ((bio)->bi_opf & ((1 << BIO_OP_SHIFT) - 1))
#define bio_op(bio) ((bio)->bi_opf >> BIO_OP_SHIFT)
#define bio_set_op_attrs(bio, op, op_flags) do { \
if (__builtin_constant_p(op)) \
BUILD_BUG_ON((op) + 0U >= (1U << REQ_OP_BITS)); \
else \
WARN_ON_ONCE((op) + 0U >= (1U << REQ_OP_BITS)); \
if (__builtin_constant_p(op_flags)) \
BUILD_BUG_ON((op_flags) + 0U >= (1U << BIO_OP_SHIFT)); \
else \
WARN_ON_ONCE((op_flags) + 0U >= (1U << BIO_OP_SHIFT)); \
(bio)->bi_opf = bio_flags(bio); \
(bio)->bi_opf |= (((op) + 0U) << BIO_OP_SHIFT); \
(bio)->bi_opf |= (op_flags); \
} while (0)
#define BIO_RESET_BYTES offsetof(struct bio, bi_max_vecs)
/*
@@ -119,6 +100,8 @@ struct bio {
#define BIO_QUIET 6 /* Make BIO Quiet */
#define BIO_CHAIN 7 /* chained bio, ->bi_remaining in effect */
#define BIO_REFFED 8 /* bio has elevated ->bi_cnt */
#define BIO_THROTTLED 9 /* This bio has already been subjected to
* throttling rules. Don't do it again. */
/*
* Flags starting here get preserved by bio_reset() - this includes
@@ -142,53 +125,61 @@ struct bio {
#define BVEC_POOL_OFFSET (16 - BVEC_POOL_BITS)
#define BVEC_POOL_IDX(bio) ((bio)->bi_flags >> BVEC_POOL_OFFSET)
#endif /* CONFIG_BLOCK */
/*
* Request flags. For use in the cmd_flags field of struct request, and in
* bi_opf of struct bio. Note that some flags are only valid in either one.
* Operations and flags common to the bio and request structures.
* We use 8 bits for encoding the operation, and the remaining 24 for flags.
*
* The least significant bit of the operation number indicates the data
* transfer direction:
*
* - if the least significant bit is set transfers are TO the device
* - if the least significant bit is not set transfers are FROM the device
*
* If a operation does not transfer data the least significant bit has no
* meaning.
*/
enum rq_flag_bits {
/* common flags */
__REQ_FAILFAST_DEV, /* no driver retries of device errors */
#define REQ_OP_BITS 8
#define REQ_OP_MASK ((1 << REQ_OP_BITS) - 1)
#define REQ_FLAG_BITS 24
enum req_opf {
/* read sectors from the device */
REQ_OP_READ = 0,
/* write sectors to the device */
REQ_OP_WRITE = 1,
/* flush the volatile write cache */
REQ_OP_FLUSH = 2,
/* discard sectors */
REQ_OP_DISCARD = 3,
/* get zone information */
REQ_OP_ZONE_REPORT = 4,
/* securely erase sectors */
REQ_OP_SECURE_ERASE = 5,
/* seset a zone write pointer */
REQ_OP_ZONE_RESET = 6,
/* write the same sector many times */
REQ_OP_WRITE_SAME = 7,
/* write the zero filled sector many times */
REQ_OP_WRITE_ZEROES = 8,
REQ_OP_LAST,
};
enum req_flag_bits {
__REQ_FAILFAST_DEV = /* no driver retries of device errors */
REQ_OP_BITS,
__REQ_FAILFAST_TRANSPORT, /* no driver retries of transport errors */
__REQ_FAILFAST_DRIVER, /* no driver retries of driver errors */
__REQ_SYNC, /* request is sync (sync write or read) */
__REQ_META, /* metadata io request */
__REQ_PRIO, /* boost priority in cfq */
__REQ_NOIDLE, /* don't anticipate more IO after this one */
__REQ_NOMERGE, /* don't touch this for merging */
__REQ_IDLE, /* anticipate more IO after this one */
__REQ_INTEGRITY, /* I/O includes block integrity payload */
__REQ_FUA, /* forced unit access */
__REQ_PREFLUSH, /* request for cache flush */
/* bio only flags */
__REQ_RAHEAD, /* read ahead, can fail anytime */
__REQ_THROTTLED, /* This bio has already been subjected to
* throttling rules. Don't do it again. */
/* request only flags */
__REQ_SORTED, /* elevator knows about this request */
__REQ_SOFTBARRIER, /* may not be passed by ioscheduler */
__REQ_NOMERGE, /* don't touch this for merging */
__REQ_STARTED, /* drive already may have started this one */
__REQ_DONTPREP, /* don't call prep for this one */
__REQ_QUEUED, /* uses queueing */
__REQ_ELVPRIV, /* elevator private data attached */
__REQ_FAILED, /* set if the request failed */
__REQ_QUIET, /* don't worry about errors */
__REQ_PREEMPT, /* set for "ide_preempt" requests and also
for requests for which the SCSI "quiesce"
state must be ignored. */
__REQ_ALLOCED, /* request came from our alloc pool */
__REQ_COPY_USER, /* contains copies of user pages */
__REQ_FLUSH_SEQ, /* request for flush sequence */
__REQ_IO_STAT, /* account I/O stat */
__REQ_MIXED_MERGE, /* merge of different types, fail separately */
__REQ_PM, /* runtime pm request */
__REQ_HASHED, /* on IO scheduler merge hash */
__REQ_MQ_INFLIGHT, /* track inflight for MQ */
__REQ_BACKGROUND, /* background IO */
__REQ_NR_BITS, /* stops here */
};
@@ -198,54 +189,47 @@ enum rq_flag_bits {
#define REQ_SYNC (1ULL << __REQ_SYNC)
#define REQ_META (1ULL << __REQ_META)
#define REQ_PRIO (1ULL << __REQ_PRIO)
#define REQ_NOIDLE (1ULL << __REQ_NOIDLE)
#define REQ_NOMERGE (1ULL << __REQ_NOMERGE)
#define REQ_IDLE (1ULL << __REQ_IDLE)
#define REQ_INTEGRITY (1ULL << __REQ_INTEGRITY)
#define REQ_FUA (1ULL << __REQ_FUA)
#define REQ_PREFLUSH (1ULL << __REQ_PREFLUSH)
#define REQ_RAHEAD (1ULL << __REQ_RAHEAD)
#define REQ_BACKGROUND (1ULL << __REQ_BACKGROUND)
#define REQ_FAILFAST_MASK \
(REQ_FAILFAST_DEV | REQ_FAILFAST_TRANSPORT | REQ_FAILFAST_DRIVER)
#define REQ_COMMON_MASK \
(REQ_FAILFAST_MASK | REQ_SYNC | REQ_META | REQ_PRIO | REQ_NOIDLE | \
REQ_PREFLUSH | REQ_FUA | REQ_INTEGRITY | REQ_NOMERGE)
#define REQ_CLONE_MASK REQ_COMMON_MASK
/* This mask is used for both bio and request merge checking */
#define REQ_NOMERGE_FLAGS \
(REQ_NOMERGE | REQ_STARTED | REQ_SOFTBARRIER | REQ_PREFLUSH | REQ_FUA | REQ_FLUSH_SEQ)
(REQ_NOMERGE | REQ_PREFLUSH | REQ_FUA)
#define REQ_RAHEAD (1ULL << __REQ_RAHEAD)
#define REQ_THROTTLED (1ULL << __REQ_THROTTLED)
#define bio_op(bio) \
((bio)->bi_opf & REQ_OP_MASK)
#define req_op(req) \
((req)->cmd_flags & REQ_OP_MASK)
#define REQ_SORTED (1ULL << __REQ_SORTED)
#define REQ_SOFTBARRIER (1ULL << __REQ_SOFTBARRIER)
#define REQ_FUA (1ULL << __REQ_FUA)
#define REQ_NOMERGE (1ULL << __REQ_NOMERGE)
#define REQ_STARTED (1ULL << __REQ_STARTED)
#define REQ_DONTPREP (1ULL << __REQ_DONTPREP)
#define REQ_QUEUED (1ULL << __REQ_QUEUED)
#define REQ_ELVPRIV (1ULL << __REQ_ELVPRIV)
#define REQ_FAILED (1ULL << __REQ_FAILED)
#define REQ_QUIET (1ULL << __REQ_QUIET)
#define REQ_PREEMPT (1ULL << __REQ_PREEMPT)
#define REQ_ALLOCED (1ULL << __REQ_ALLOCED)
#define REQ_COPY_USER (1ULL << __REQ_COPY_USER)
#define REQ_PREFLUSH (1ULL << __REQ_PREFLUSH)
#define REQ_FLUSH_SEQ (1ULL << __REQ_FLUSH_SEQ)
#define REQ_IO_STAT (1ULL << __REQ_IO_STAT)
#define REQ_MIXED_MERGE (1ULL << __REQ_MIXED_MERGE)
#define REQ_PM (1ULL << __REQ_PM)
#define REQ_HASHED (1ULL << __REQ_HASHED)
#define REQ_MQ_INFLIGHT (1ULL << __REQ_MQ_INFLIGHT)
/* obsolete, don't use in new code */
static inline void bio_set_op_attrs(struct bio *bio, unsigned op,
unsigned op_flags)
{
bio->bi_opf = op | op_flags;
}
enum req_op {
REQ_OP_READ,
REQ_OP_WRITE,
REQ_OP_DISCARD, /* request to discard sectors */
REQ_OP_SECURE_ERASE, /* request to securely erase sectors */
REQ_OP_WRITE_SAME, /* write same block many times */
REQ_OP_FLUSH, /* request for cache flush */
};
static inline bool op_is_write(unsigned int op)
{
return (op & 1);
}
#define REQ_OP_BITS 3
/*
* Reads are always treated as synchronous, as are requests with the FUA or
* PREFLUSH flag. Other operations may be marked as synchronous using the
* REQ_SYNC flag.
*/
static inline bool op_is_sync(unsigned int op)
{
return (op & REQ_OP_MASK) == REQ_OP_READ ||
(op & (REQ_SYNC | REQ_FUA | REQ_PREFLUSH));
}
typedef unsigned int blk_qc_t;
#define BLK_QC_T_NONE -1U
@@ -271,4 +255,20 @@ static inline unsigned int blk_qc_t_to_tag(blk_qc_t cookie)
return cookie & ((1u << BLK_QC_T_SHIFT) - 1);
}
struct blk_issue_stat {
u64 time;
};
#define BLK_RQ_STAT_BATCH 64
struct blk_rq_stat {
s64 mean;
u64 min;
u64 max;
s32 nr_samples;
s32 nr_batch;
u64 batch;
s64 time;
};
#endif /* __LINUX_BLK_TYPES_H */

246
include/linux/blkdev.h
View File

@@ -24,6 +24,7 @@
#include <linux/rcupdate.h>
#include <linux/percpu-refcount.h>
#include <linux/scatterlist.h>
#include <linux/blkzoned.h>
struct module;
struct scsi_ioctl_command;
@@ -37,6 +38,7 @@ struct bsg_job;
struct blkcg_gq;
struct blk_flush_queue;
struct pr_ops;
struct rq_wb;
#define BLKDEV_MIN_RQ 4
#define BLKDEV_MAX_RQ 128 /* Default maximum */
@@ -77,6 +79,55 @@ enum rq_cmd_type_bits {
REQ_TYPE_DRV_PRIV, /* driver defined types from here */
};
/*
* request flags */
typedef __u32 __bitwise req_flags_t;
/* elevator knows about this request */
#define RQF_SORTED ((__force req_flags_t)(1 << 0))
/* drive already may have started this one */
#define RQF_STARTED ((__force req_flags_t)(1 << 1))
/* uses tagged queueing */
#define RQF_QUEUED ((__force req_flags_t)(1 << 2))
/* may not be passed by ioscheduler */
#define RQF_SOFTBARRIER ((__force req_flags_t)(1 << 3))
/* request for flush sequence */
#define RQF_FLUSH_SEQ ((__force req_flags_t)(1 << 4))
/* merge of different types, fail separately */
#define RQF_MIXED_MERGE ((__force req_flags_t)(1 << 5))
/* track inflight for MQ */
#define RQF_MQ_INFLIGHT ((__force req_flags_t)(1 << 6))
/* don't call prep for this one */
#define RQF_DONTPREP ((__force req_flags_t)(1 << 7))
/* set for "ide_preempt" requests and also for requests for which the SCSI
"quiesce" state must be ignored. */
#define RQF_PREEMPT ((__force req_flags_t)(1 << 8))
/* contains copies of user pages */
#define RQF_COPY_USER ((__force req_flags_t)(1 << 9))
/* vaguely specified driver internal error. Ignored by the block layer */
#define RQF_FAILED ((__force req_flags_t)(1 << 10))
/* don't warn about errors */
#define RQF_QUIET ((__force req_flags_t)(1 << 11))
/* elevator private data attached */
#define RQF_ELVPRIV ((__force req_flags_t)(1 << 12))
/* account I/O stat */
#define RQF_IO_STAT ((__force req_flags_t)(1 << 13))
/* request came from our alloc pool */
#define RQF_ALLOCED ((__force req_flags_t)(1 << 14))
/* runtime pm request */
#define RQF_PM ((__force req_flags_t)(1 << 15))
/* on IO scheduler merge hash */
#define RQF_HASHED ((__force req_flags_t)(1 << 16))
/* IO stats tracking on */
#define RQF_STATS ((__force req_flags_t)(1 << 17))
/* Look at ->special_vec for the actual data payload instead of the
bio chain. */
#define RQF_SPECIAL_PAYLOAD ((__force req_flags_t)(1 << 18))
/* flags that prevent us from merging requests: */
#define RQF_NOMERGE_FLAGS \
(RQF_STARTED | RQF_SOFTBARRIER | RQF_FLUSH_SEQ | RQF_SPECIAL_PAYLOAD)
#define BLK_MAX_CDB 16
/*
@@ -97,7 +148,8 @@ struct request {
int cpu;
unsigned cmd_type;
u64 cmd_flags;
unsigned int cmd_flags; /* op and common flags */
req_flags_t rq_flags;
unsigned long atomic_flags;
/* the following two fields are internal, NEVER access directly */
@@ -126,6 +178,7 @@ struct request {
*/
union {
struct rb_node rb_node; /* sort/lookup */
struct bio_vec special_vec;
void *completion_data;
};
@@ -151,6 +204,7 @@ struct request {
struct gendisk *rq_disk;
struct hd_struct *part;
unsigned long start_time;
struct blk_issue_stat issue_stat;
#ifdef CONFIG_BLK_CGROUP
struct request_list *rl; /* rl this rq is alloced from */
unsigned long long start_time_ns;
@@ -198,20 +252,6 @@ struct request {
struct request *next_rq;
};
#define REQ_OP_SHIFT (8 * sizeof(u64) - REQ_OP_BITS)
#define req_op(req) ((req)->cmd_flags >> REQ_OP_SHIFT)
#define req_set_op(req, op) do { \
WARN_ON(op >= (1 << REQ_OP_BITS)); \
(req)->cmd_flags &= ((1ULL << REQ_OP_SHIFT) - 1); \
(req)->cmd_flags |= ((u64) (op) << REQ_OP_SHIFT); \
} while (0)
#define req_set_op_attrs(req, op, flags) do { \
req_set_op(req, op); \
(req)->cmd_flags |= flags; \
} while (0)
static inline unsigned short req_get_ioprio(struct request *req)
{
return req->ioprio;
@@ -248,7 +288,6 @@ enum blk_queue_state {
struct blk_queue_tag {
struct request **tag_index; /* map of busy tags */
unsigned long *tag_map; /* bit map of free/busy tags */
int busy; /* current depth */
int max_depth; /* what we will send to device */
int real_max_depth; /* what the array can hold */
atomic_t refcnt; /* map can be shared */
@@ -261,6 +300,15 @@ struct blk_queue_tag {
#define BLK_SCSI_MAX_CMDS (256)
#define BLK_SCSI_CMD_PER_LONG (BLK_SCSI_MAX_CMDS / (sizeof(long) * 8))
/*
* Zoned block device models (zoned limit).
*/
enum blk_zoned_model {
BLK_ZONED_NONE, /* Regular block device */
BLK_ZONED_HA, /* Host-aware zoned block device */
BLK_ZONED_HM, /* Host-managed zoned block device */
};
struct queue_limits {
unsigned long bounce_pfn;
unsigned long seg_boundary_mask;
@@ -278,6 +326,7 @@ struct queue_limits {
unsigned int max_discard_sectors;
unsigned int max_hw_discard_sectors;
unsigned int max_write_same_sectors;
unsigned int max_write_zeroes_sectors;
unsigned int discard_granularity;
unsigned int discard_alignment;
@@ -290,8 +339,45 @@ struct queue_limits {
unsigned char cluster;
unsigned char discard_zeroes_data;
unsigned char raid_partial_stripes_expensive;
enum blk_zoned_model zoned;
};
#ifdef CONFIG_BLK_DEV_ZONED
struct blk_zone_report_hdr {
unsigned int nr_zones;
u8 padding[60];
};
extern int blkdev_report_zones(struct block_device *bdev,
sector_t sector, struct blk_zone *zones,
unsigned int *nr_zones, gfp_t gfp_mask);
extern int blkdev_reset_zones(struct block_device *bdev, sector_t sectors,
sector_t nr_sectors, gfp_t gfp_mask);
extern int blkdev_report_zones_ioctl(struct block_device *bdev, fmode_t mode,
unsigned int cmd, unsigned long arg);
extern int blkdev_reset_zones_ioctl(struct block_device *bdev, fmode_t mode,
unsigned int cmd, unsigned long arg);
#else /* CONFIG_BLK_DEV_ZONED */
static inline int blkdev_report_zones_ioctl(struct block_device *bdev,
fmode_t mode, unsigned int cmd,
unsigned long arg)
{
return -ENOTTY;
}
static inline int blkdev_reset_zones_ioctl(struct block_device *bdev,
fmode_t mode, unsigned int cmd,
unsigned long arg)
{
return -ENOTTY;
}
#endif /* CONFIG_BLK_DEV_ZONED */
struct request_queue {
/*
* Together with queue_head for cacheline sharing
@@ -302,6 +388,8 @@ struct request_queue {
int nr_rqs[2]; /* # allocated [a]sync rqs */
int nr_rqs_elvpriv; /* # allocated rqs w/ elvpriv */
struct rq_wb *rq_wb;
/*
* If blkcg is not used, @q->root_rl serves all requests. If blkcg
* is used, root blkg allocates from @q->root_rl and all other
@@ -327,6 +415,8 @@ struct request_queue {
struct blk_mq_ctx __percpu *queue_ctx;
unsigned int nr_queues;
unsigned int queue_depth;
/* hw dispatch queues */
struct blk_mq_hw_ctx **queue_hw_ctx;
unsigned int nr_hw_queues;
@@ -412,6 +502,9 @@ struct request_queue {
unsigned int nr_sorted;
unsigned int in_flight[2];
struct blk_rq_stat rq_stats[2];
/*
* Number of active block driver functions for which blk_drain_queue()
* must wait. Must be incremented around functions that unlock the
@@ -420,6 +513,7 @@ struct request_queue {
unsigned int request_fn_active;
unsigned int rq_timeout;
int poll_nsec;
struct timer_list timeout;
struct work_struct timeout_work;
struct list_head timeout_list;
@@ -505,6 +599,7 @@ struct request_queue {
#define QUEUE_FLAG_FUA 24 /* device supports FUA writes */
#define QUEUE_FLAG_FLUSH_NQ 25 /* flush not queueuable */
#define QUEUE_FLAG_DAX 26 /* device supports DAX */
#define QUEUE_FLAG_STATS 27 /* track rq completion times */
#define QUEUE_FLAG_DEFAULT ((1 << QUEUE_FLAG_IO_STAT) | \
(1 << QUEUE_FLAG_STACKABLE) | \
@@ -601,7 +696,7 @@ static inline void queue_flag_clear(unsigned int flag, struct request_queue *q)
REQ_FAILFAST_DRIVER))
#define blk_account_rq(rq) \
(((rq)->cmd_flags & REQ_STARTED) && \
(((rq)->rq_flags & RQF_STARTED) && \
((rq)->cmd_type == REQ_TYPE_FS))
#define blk_rq_cpu_valid(rq) ((rq)->cpu != -1)
@@ -627,17 +722,31 @@ static inline unsigned int blk_queue_cluster(struct request_queue *q)
return q->limits.cluster;
}
/*
* We regard a request as sync, if either a read or a sync write
*/
static inline bool rw_is_sync(int op, unsigned int rw_flags)
static inline enum blk_zoned_model
blk_queue_zoned_model(struct request_queue *q)
{
return op == REQ_OP_READ || (rw_flags & REQ_SYNC);
return q->limits.zoned;
}
static inline bool blk_queue_is_zoned(struct request_queue *q)
{
switch (blk_queue_zoned_model(q)) {
case BLK_ZONED_HA:
case BLK_ZONED_HM:
return true;
default:
return false;
}
}
static inline unsigned int blk_queue_zone_size(struct request_queue *q)
{
return blk_queue_is_zoned(q) ? q->limits.chunk_sectors : 0;
}
static inline bool rq_is_sync(struct request *rq)
{
return rw_is_sync(req_op(rq), rq->cmd_flags);
return op_is_sync(rq->cmd_flags);
}
static inline bool blk_rl_full(struct request_list *rl, bool sync)
@@ -669,8 +778,13 @@ static inline bool rq_mergeable(struct request *rq)
if (req_op(rq) == REQ_OP_FLUSH)
return false;
if (req_op(rq) == REQ_OP_WRITE_ZEROES)
return false;
if (rq->cmd_flags & REQ_NOMERGE_FLAGS)
return false;
if (rq->rq_flags & RQF_NOMERGE_FLAGS)
return false;
return true;
}
@@ -683,6 +797,14 @@ static inline bool blk_write_same_mergeable(struct bio *a, struct bio *b)
return false;
}
static inline unsigned int blk_queue_depth(struct request_queue *q)
{
if (q->queue_depth)
return q->queue_depth;
return q->nr_requests;
}
/*
* q->prep_rq_fn return values
*/
@@ -790,8 +912,6 @@ extern void __blk_put_request(struct request_queue *, struct request *);
extern struct request *blk_get_request(struct request_queue *, int, gfp_t);
extern void blk_rq_set_block_pc(struct request *);
extern void blk_requeue_request(struct request_queue *, struct request *);
extern void blk_add_request_payload(struct request *rq, struct page *page,
int offset, unsigned int len);
extern int blk_lld_busy(struct request_queue *q);
extern int blk_rq_prep_clone(struct request *rq, struct request *rq_src,
struct bio_set *bs, gfp_t gfp_mask,
@@ -824,6 +944,7 @@ extern void __blk_run_queue(struct request_queue *q);
extern void __blk_run_queue_uncond(struct request_queue *q);
extern void blk_run_queue(struct request_queue *);
extern void blk_run_queue_async(struct request_queue *q);
extern void blk_mq_quiesce_queue(struct request_queue *q);
extern int blk_rq_map_user(struct request_queue *, struct request *,
struct rq_map_data *, void __user *, unsigned long,
gfp_t);
@@ -837,7 +958,7 @@ extern int blk_execute_rq(struct request_queue *, struct gendisk *,
extern void blk_execute_rq_nowait(struct request_queue *, struct gendisk *,
struct request *, int, rq_end_io_fn *);
bool blk_poll(struct request_queue *q, blk_qc_t cookie);
bool blk_mq_poll(struct request_queue *q, blk_qc_t cookie);
static inline struct request_queue *bdev_get_queue(struct block_device *bdev)
{
@@ -888,6 +1009,9 @@ static inline unsigned int blk_queue_get_max_sectors(struct request_queue *q,
if (unlikely(op == REQ_OP_WRITE_SAME))
return q->limits.max_write_same_sectors;
if (unlikely(op == REQ_OP_WRITE_ZEROES))
return q->limits.max_write_zeroes_sectors;
return q->limits.max_sectors;
}
@@ -933,6 +1057,20 @@ static inline unsigned int blk_rq_count_bios(struct request *rq)
return nr_bios;
}
/*
* blk_rq_set_prio - associate a request with prio from ioc
* @rq: request of interest
* @ioc: target iocontext
*
* Assocate request prio with ioc prio so request based drivers
* can leverage priority information.
*/
static inline void blk_rq_set_prio(struct request *rq, struct io_context *ioc)
{
if (ioc)
rq->ioprio = ioc->ioprio;
}
/*
* Request issue related functions.
*/
@@ -991,6 +1129,8 @@ extern void blk_queue_max_discard_sectors(struct request_queue *q,
unsigned int max_discard_sectors);
extern void blk_queue_max_write_same_sectors(struct request_queue *q,
unsigned int max_write_same_sectors);
extern void blk_queue_max_write_zeroes_sectors(struct request_queue *q,
unsigned int max_write_same_sectors);
extern void blk_queue_logical_block_size(struct request_queue *, unsigned short);
extern void blk_queue_physical_block_size(struct request_queue *, unsigned int);
extern void blk_queue_alignment_offset(struct request_queue *q,
@@ -999,6 +1139,7 @@ extern void blk_limits_io_min(struct queue_limits *limits, unsigned int min);
extern void blk_queue_io_min(struct request_queue *q, unsigned int min);
extern void blk_limits_io_opt(struct queue_limits *limits, unsigned int opt);
extern void blk_queue_io_opt(struct request_queue *q, unsigned int opt);
extern void blk_set_queue_depth(struct request_queue *q, unsigned int depth);
extern void blk_set_default_limits(struct queue_limits *lim);
extern void blk_set_stacking_limits(struct queue_limits *lim);
extern int blk_stack_limits(struct queue_limits *t, struct queue_limits *b,
@@ -1027,6 +1168,13 @@ extern void blk_queue_flush_queueable(struct request_queue *q, bool queueable);
extern void blk_queue_write_cache(struct request_queue *q, bool enabled, bool fua);
extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev);
static inline unsigned short blk_rq_nr_phys_segments(struct request *rq)
{
if (rq->rq_flags & RQF_SPECIAL_PAYLOAD)
return 1;
return rq->nr_phys_segments;
}
extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *);
extern void blk_dump_rq_flags(struct request *, char *);
extern long nr_blockdev_pages(void);
@@ -1057,7 +1205,7 @@ static inline int blk_pre_runtime_suspend(struct request_queue *q)
static inline void blk_post_runtime_suspend(struct request_queue *q, int err) {}
static inline void blk_pre_runtime_resume(struct request_queue *q) {}
static inline void blk_post_runtime_resume(struct request_queue *q, int err) {}
extern inline void blk_set_runtime_active(struct request_queue *q) {}
static inline void blk_set_runtime_active(struct request_queue *q) {}
#endif
/*
@@ -1078,6 +1226,7 @@ struct blk_plug {
struct list_head cb_list; /* md requires an unplug callback */
};
#define BLK_MAX_REQUEST_COUNT 16
#define BLK_PLUG_FLUSH_SIZE (128 * 1024)
struct blk_plug_cb;
typedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);
@@ -1151,6 +1300,9 @@ extern int __blkdev_issue_discard(struct block_device *bdev, sector_t sector,
struct bio **biop);
extern int blkdev_issue_write_same(struct block_device *bdev, sector_t sector,
sector_t nr_sects, gfp_t gfp_mask, struct page *page);
extern int __blkdev_issue_zeroout(struct block_device *bdev, sector_t sector,
sector_t nr_sects, gfp_t gfp_mask, struct bio **biop,
bool discard);
extern int blkdev_issue_zeroout(struct block_device *bdev, sector_t sector,
sector_t nr_sects, gfp_t gfp_mask, bool discard);
static inline int sb_issue_discard(struct super_block *sb, sector_t block,
@@ -1354,6 +1506,46 @@ static inline unsigned int bdev_write_same(struct block_device *bdev)
return 0;
}
static inline unsigned int bdev_write_zeroes_sectors(struct block_device *bdev)
{
struct request_queue *q = bdev_get_queue(bdev);
if (q)
return q->limits.max_write_zeroes_sectors;
return 0;
}
static inline enum blk_zoned_model bdev_zoned_model(struct block_device *bdev)
{
struct request_queue *q = bdev_get_queue(bdev);
if (q)
return blk_queue_zoned_model(q);
return BLK_ZONED_NONE;
}
static inline bool bdev_is_zoned(struct block_device *bdev)
{
struct request_queue *q = bdev_get_queue(bdev);
if (q)
return blk_queue_is_zoned(q);
return false;
}
static inline unsigned int bdev_zone_size(struct block_device *bdev)
{
struct request_queue *q = bdev_get_queue(bdev);
if (q)
return blk_queue_zone_size(q);
return 0;
}
static inline int queue_dma_alignment(struct request_queue *q)
{
return q ? q->dma_alignment : 511;

2
include/linux/blktrace_api.h
View File

@@ -118,7 +118,7 @@ static inline int blk_cmd_buf_len(struct request *rq)
}
extern void blk_dump_cmd(char *buf, struct request *rq);
extern void blk_fill_rwbs(char *rwbs, int op, u32 rw, int bytes);
extern void blk_fill_rwbs(char *rwbs, unsigned int op, int bytes);
#endif /* CONFIG_EVENT_TRACING && CONFIG_BLOCK */

92
include/linux/bpf-cgroup.h Normal file
View File

@@ -0,0 +1,92 @@
#ifndef _BPF_CGROUP_H
#define _BPF_CGROUP_H
#include <linux/jump_label.h>
#include <uapi/linux/bpf.h>
struct sock;
struct cgroup;
struct sk_buff;
#ifdef CONFIG_CGROUP_BPF
extern struct static_key_false cgroup_bpf_enabled_key;
#define cgroup_bpf_enabled static_branch_unlikely(&cgroup_bpf_enabled_key)
struct cgroup_bpf {
/*
* Store two sets of bpf_prog pointers, one for programs that are
* pinned directly to this cgroup, and one for those that are effective
* when this cgroup is accessed.
*/
struct bpf_prog *prog[MAX_BPF_ATTACH_TYPE];
struct bpf_prog __rcu *effective[MAX_BPF_ATTACH_TYPE];
};
void cgroup_bpf_put(struct cgroup *cgrp);
void cgroup_bpf_inherit(struct cgroup *cgrp, struct cgroup *parent);
void __cgroup_bpf_update(struct cgroup *cgrp,
struct cgroup *parent,
struct bpf_prog *prog,
enum bpf_attach_type type);
/* Wrapper for __cgroup_bpf_update() protected by cgroup_mutex */
void cgroup_bpf_update(struct cgroup *cgrp,
struct bpf_prog *prog,
enum bpf_attach_type type);
int __cgroup_bpf_run_filter_skb(struct sock *sk,
struct sk_buff *skb,
enum bpf_attach_type type);
int __cgroup_bpf_run_filter_sk(struct sock *sk,
enum bpf_attach_type type);
/* Wrappers for __cgroup_bpf_run_filter_skb() guarded by cgroup_bpf_enabled. */
#define BPF_CGROUP_RUN_PROG_INET_INGRESS(sk, skb) \
({ \
int __ret = 0; \
if (cgroup_bpf_enabled) \
__ret = __cgroup_bpf_run_filter_skb(sk, skb, \
BPF_CGROUP_INET_INGRESS); \
\
__ret; \
})
#define BPF_CGROUP_RUN_PROG_INET_EGRESS(sk, skb) \
({ \
int __ret = 0; \
if (cgroup_bpf_enabled && sk && sk == skb->sk) { \
typeof(sk) __sk = sk_to_full_sk(sk); \
if (sk_fullsock(__sk)) \
__ret = __cgroup_bpf_run_filter_skb(__sk, skb, \
BPF_CGROUP_INET_EGRESS); \
} \
__ret; \
})
#define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) \
({ \
int __ret = 0; \
if (cgroup_bpf_enabled && sk) { \
__ret = __cgroup_bpf_run_filter_sk(sk, \
BPF_CGROUP_INET_SOCK_CREATE); \
} \
__ret; \
})
#else
struct cgroup_bpf {};
static inline void cgroup_bpf_put(struct cgroup *cgrp) {}
static inline void cgroup_bpf_inherit(struct cgroup *cgrp,
struct cgroup *parent) {}
#define BPF_CGROUP_RUN_PROG_INET_INGRESS(sk,skb) ({ 0; })
#define BPF_CGROUP_RUN_PROG_INET_EGRESS(sk,skb) ({ 0; })
#define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) ({ 0; })
#endif /* CONFIG_CGROUP_BPF */
#endif /* _BPF_CGROUP_H */

30
include/linux/bpf.h
View File

@@ -216,6 +216,7 @@ u64 bpf_tail_call(u64 ctx, u64 r2, u64 index, u64 r4, u64 r5);
u64 bpf_get_stackid(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5);
bool bpf_prog_array_compatible(struct bpf_array *array, const struct bpf_prog *fp);
int bpf_prog_calc_digest(struct bpf_prog *fp);
const struct bpf_func_proto *bpf_get_trace_printk_proto(void);
@@ -233,13 +234,16 @@ void bpf_register_map_type(struct bpf_map_type_list *tl);
struct bpf_prog *bpf_prog_get(u32 ufd);
struct bpf_prog *bpf_prog_get_type(u32 ufd, enum bpf_prog_type type);
struct bpf_prog *bpf_prog_add(struct bpf_prog *prog, int i);
struct bpf_prog *bpf_prog_inc(struct bpf_prog *prog);
struct bpf_prog * __must_check bpf_prog_add(struct bpf_prog *prog, int i);
void bpf_prog_sub(struct bpf_prog *prog, int i);
struct bpf_prog * __must_check bpf_prog_inc(struct bpf_prog *prog);
void bpf_prog_put(struct bpf_prog *prog);
int __bpf_prog_charge(struct user_struct *user, u32 pages);
void __bpf_prog_uncharge(struct user_struct *user, u32 pages);
struct bpf_map *bpf_map_get_with_uref(u32 ufd);
struct bpf_map *__bpf_map_get(struct fd f);
struct bpf_map *bpf_map_inc(struct bpf_map *map, bool uref);
struct bpf_map * __must_check bpf_map_inc(struct bpf_map *map, bool uref);
void bpf_map_put_with_uref(struct bpf_map *map);
void bpf_map_put(struct bpf_map *map);
int bpf_map_precharge_memlock(u32 pages);
@@ -298,18 +302,33 @@ static inline struct bpf_prog *bpf_prog_get_type(u32 ufd,
{
return ERR_PTR(-EOPNOTSUPP);
}
static inline struct bpf_prog *bpf_prog_add(struct bpf_prog *prog, int i)
static inline struct bpf_prog * __must_check bpf_prog_add(struct bpf_prog *prog,
int i)
{
return ERR_PTR(-EOPNOTSUPP);
}
static inline void bpf_prog_sub(struct bpf_prog *prog, int i)
{
}
static inline void bpf_prog_put(struct bpf_prog *prog)
{
}
static inline struct bpf_prog *bpf_prog_inc(struct bpf_prog *prog)
static inline struct bpf_prog * __must_check bpf_prog_inc(struct bpf_prog *prog)
{
return ERR_PTR(-EOPNOTSUPP);
}
static inline int __bpf_prog_charge(struct user_struct *user, u32 pages)
{
return 0;
}
static inline void __bpf_prog_uncharge(struct user_struct *user, u32 pages)
{
}
#endif /* CONFIG_BPF_SYSCALL */
/* verifier prototypes for helper functions called from eBPF programs */
@@ -319,6 +338,7 @@ extern const struct bpf_func_proto bpf_map_delete_elem_proto;
extern const struct bpf_func_proto bpf_get_prandom_u32_proto;
extern const struct bpf_func_proto bpf_get_smp_processor_id_proto;
extern const struct bpf_func_proto bpf_get_numa_node_id_proto;
extern const struct bpf_func_proto bpf_tail_call_proto;
extern const struct bpf_func_proto bpf_ktime_get_ns_proto;
extern const struct bpf_func_proto bpf_get_current_pid_tgid_proto;

14
include/linux/bpf_verifier.h
View File

@@ -18,19 +18,12 @@
struct bpf_reg_state {
enum bpf_reg_type type;
/*
* Used to determine if any memory access using this register will
* result in a bad access.
*/
s64 min_value;
u64 max_value;
union {
/* valid when type == CONST_IMM | PTR_TO_STACK | UNKNOWN_VALUE */
s64 imm;
/* valid when type == PTR_TO_PACKET* */
struct {
u32 id;
u16 off;
u16 range;
};
@@ -40,6 +33,13 @@ struct bpf_reg_state {
*/
struct bpf_map *map_ptr;
};
u32 id;
/* Used to determine if any memory access using this register will
* result in a bad access. These two fields must be last.
* See states_equal()
*/
s64 min_value;
u64 max_value;
};
enum bpf_stack_slot_type {

27
include/linux/brcmphy.h
View File

@@ -13,11 +13,13 @@
#define PHY_ID_BCM5241 0x0143bc30
#define PHY_ID_BCMAC131 0x0143bc70
#define PHY_ID_BCM5481 0x0143bca0
#define PHY_ID_BCM54810 0x03625d00
#define PHY_ID_BCM5482 0x0143bcb0
#define PHY_ID_BCM5411 0x00206070
#define PHY_ID_BCM5421 0x002060e0
#define PHY_ID_BCM5464 0x002060b0
#define PHY_ID_BCM5461 0x002060c0
#define PHY_ID_BCM54612E 0x03625e60
#define PHY_ID_BCM54616S 0x03625d10
#define PHY_ID_BCM57780 0x03625d90
@@ -55,6 +57,7 @@
#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
/* Broadcom BCM7xxx specific workarounds */
#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
@@ -105,11 +108,15 @@
#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN (1 << 4)
#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
/*
* Broadcom LED source encodings. These are used in BCM5461, BCM5481,
@@ -124,6 +131,7 @@
#define BCM_LED_SRC_INTR 0x6
#define BCM_LED_SRC_QUALITY 0x7
#define BCM_LED_SRC_RCVLED 0x8
#define BCM_LED_SRC_WIRESPEED 0x9
#define BCM_LED_SRC_MULTICOLOR1 0xa
#define BCM_LED_SRC_OPENSHORT 0xb
#define BCM_LED_SRC_OFF 0xe /* Tied high */
@@ -135,6 +143,14 @@
* Shadow values go into bits [14:10] of register 0x1c to select a shadow
* register to access.
*/
/* 00100: Reserved control register 2 */
#define BCM54XX_SHD_SCR2 0x04
#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2
#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2
#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7
/* 00101: Spare Control Register 3 */
#define BCM54XX_SHD_SCR3 0x05
#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
@@ -189,6 +205,12 @@
#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
/* BCM54810 Registers */
#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
#define BCM54810_SHD_CLK_CTL 0x3
#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
/*****************************************************************************/
/* Fast Ethernet Transceiver definitions. */
@@ -222,6 +244,9 @@
#define LPI_FEATURE_EN_DIG1000X 0x4000
/* Core register definitions*/
#define MII_BRCM_CORE_BASE12 0x12
#define MII_BRCM_CORE_BASE13 0x13
#define MII_BRCM_CORE_BASE14 0x14
#define MII_BRCM_CORE_BASE1E 0x1E
#define MII_BRCM_CORE_EXPB0 0xB0
#define MII_BRCM_CORE_EXPB1 0xB1

4
include/linux/bsg-lib.h
View File

@@ -40,6 +40,8 @@ struct bsg_job {
struct device *dev;
struct request *req;
struct kref kref;
/* Transport/driver specific request/reply structs */
void *request;
void *reply;
@@ -67,5 +69,7 @@ void bsg_job_done(struct bsg_job *job, int result,
int bsg_setup_queue(struct device *dev, struct request_queue *q, char *name,
bsg_job_fn *job_fn, int dd_job_size);
void bsg_request_fn(struct request_queue *q);
void bsg_job_put(struct bsg_job *job);
int __must_check bsg_job_get(struct bsg_job *job);
#endif

7
include/linux/buffer_head.h
View File

@@ -168,7 +168,12 @@ int inode_has_buffers(struct inode *);
void invalidate_inode_buffers(struct inode *);
int remove_inode_buffers(struct inode *inode);
int sync_mapping_buffers(struct address_space *mapping);
void unmap_underlying_metadata(struct block_device *bdev, sector_t block);
void clean_bdev_aliases(struct block_device *bdev, sector_t block,
sector_t len);
static inline void clean_bdev_bh_alias(struct buffer_head *bh)
{
clean_bdev_aliases(bh->b_bdev, bh->b_blocknr, 1);
}
void mark_buffer_async_write(struct buffer_head *bh);
void __wait_on_buffer(struct buffer_head *);

17
include/linux/bug.h
View File

@@ -121,4 +121,21 @@ static inline enum bug_trap_type report_bug(unsigned long bug_addr,
}
#endif /* CONFIG_GENERIC_BUG */
/*
* Since detected data corruption should stop operation on the affected
* structures, this returns false if the corruption condition is found.
*/
#define CHECK_DATA_CORRUPTION(condition, fmt, ...) \
do { \
if (unlikely(condition)) { \
if (IS_ENABLED(CONFIG_BUG_ON_DATA_CORRUPTION)) { \
pr_err(fmt, ##__VA_ARGS__); \
BUG(); \
} else \
WARN(1, fmt, ##__VA_ARGS__); \
return false; \
} \
} while (0)
#endif /* _LINUX_BUG_H */

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