MIPS: Flush TLB handlers directly after writing them
When having enabled MIPS_PGD_C0_CONTEXT, trap_init() might call the
generated tlbmiss_handler_setup_pgd before it was committed to memory,
causing boot failures:
trap_init()
|- per_cpu_trap_init()
| |- TLBMISS_HANDLER_SETUP()
| |- tlbmiss_handler_setup_pgd()
|- flush_tlb_handlers()
To avoid this, move flush_tlb_handlers() into build_tlb_refill_handler()
right after they were generated. We can do this as the cache handling is
initialized just before creating the tlb handlers.
This issue was introduced in 3d8bfdd030
("MIPS: Use C0_KScratch (if present) to hold PGD pointer.").
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/5539/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:

committato da
Ralf Baechle

parent
6a72015d3c
commit
a3d9086bb1
@@ -1627,7 +1627,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
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}
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extern void tlb_init(void);
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extern void flush_tlb_handlers(void);
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/*
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* Timer interrupt
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@@ -1956,7 +1955,6 @@ void __init trap_init(void)
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set_handler(0x080, &except_vec3_generic, 0x80);
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local_flush_icache_range(ebase, ebase + 0x400);
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flush_tlb_handlers();
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sort_extable(__start___dbe_table, __stop___dbe_table);
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