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clk: tegra: Add DFLL DVCO reset control for Tegra124

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The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block.  This reset line is asserted upon SoC
reset.  Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.

Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
saving hours of debugging time.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
[ttynkkynen: ported to tegra124 from tegra114]
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
[mikko.perttunen: ported to special reset callback]
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Paul Walmsley
2015-05-19 14:43:30 +03:00
committed by Thierry Reding
parent 66b6f3d074
commit a3c83ff20c
2 changed files with 80 additions and 0 deletions
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12
include/dt-bindings/reset/tegra124-car.h Normal file
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@@ -0,0 +1,12 @@
/*
* This header provides Tegra124-specific constants for binding
* nvidia,tegra124-car.
*/
#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H
#define _DT_BINDINGS_RESET_TEGRA124_CAR_H
#define TEGRA124_RESET(x) (6 * 32 + (x))
#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0)
#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */